^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/atm/suni.h - S/UNI PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef DRIVER_ATM_SUNI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DRIVER_ATM_SUNI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/atmioc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sonet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* SUNI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SUNI_MRI 0x00 /* Master Reset and Identity / Load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Meter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SUNI_MC 0x01 /* Master Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SUNI_MIS 0x02 /* Master Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* no 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SUNI_MCM 0x04 /* Master Clock Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SUNI_MCT 0x05 /* Master Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUNI_CSCS 0x06 /* Clock Synthesis Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUNI_CRCS 0x07 /* Clock Recovery Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* 0x08-0x0F reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUNI_RSOP_CIE 0x10 /* RSOP Control/Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUNI_RSOP_SIS 0x11 /* RSOP Status/Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUNI_RSOP_SBM 0x13 /* RSOP Section BIP-8 MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUNI_TSOP_CTRL 0x14 /* TSOP Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUNI_TSOP_DIAG 0x15 /* TSOP Diagnostic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* 0x16-0x17 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUNI_RLOP_CS 0x18 /* RLOP Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUNI_RLOP_IES 0x19 /* RLOP Interrupt Enable/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUNI_RLOP_LBL 0x1A /* RLOP Line BIP-8/24 LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUNI_RLOP_LB 0x1B /* RLOP Line BIP-8/24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUNI_RLOP_LBM 0x1C /* RLOP Line BIP-8/24 MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUNI_RLOP_LFL 0x1D /* RLOP Line FEBE LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUNI_RLOP_LF 0x1E /* RLOP Line FEBE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUNI_RLOP_LFM 0x1F /* RLOP Line FEBE MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUNI_TLOP_CTRL 0x20 /* TLOP Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUNI_TLOP_DIAG 0x21 /* TLOP Diagnostic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 0x22-0x27 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUNI_SSTB_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUNI_RPOP_SC 0x30 /* RPOP Status/Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUNI_RPOP_IS 0x31 /* RPOP Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* 0x32 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUNI_RPOP_IE 0x33 /* RPOP Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 0x34-0x36 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUNI_RPOP_PSL 0x37 /* RPOP Path Signal Label */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUNI_RPOP_PBL 0x38 /* RPOP Path BIP-8 LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUNI_RPOP_PBM 0x39 /* RPOP Path BIP-8 MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUNI_RPOP_PFL 0x3A /* RPOP Path FEBE LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SUNI_RPOP_PFM 0x3B /* RPOP Path FEBE MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* 0x3C reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SUNI_RPOP_PBC 0x3D /* RPOP Path BIP-8 Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SUNI_RPOP_RC 0x3D /* RPOP Ring Control (PM5355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* 0x3E-0x3F reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SUNI_TPOP_CD 0x40 /* TPOP Control/Diagnostic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SUNI_TPOP_PC 0x41 /* TPOP Pointer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* 0x42-0x44 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SUNI_TPOP_APL 0x45 /* TPOP Arbitrary Pointer LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SUNI_TPOP_APM 0x46 /* TPOP Arbitrary Pointer MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 0x47 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SUNI_TPOP_PSL 0x48 /* TPOP Path Signal Label */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SUNI_TPOP_PS 0x49 /* TPOP Path Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* 0x4A-0x4F reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SUNI_RACP_CS 0x50 /* RACP Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SUNI_RACP_IES 0x51 /* RACP Interrupt Enable/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SUNI_RACP_MHP 0x52 /* RACP Match Header Pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SUNI_RACP_MHM 0x53 /* RACP Match Header Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUNI_RACP_CHEC 0x54 /* RACP Correctable HCS Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUNI_RACP_UHEC 0x55 /* RACP Uncorrectable HCS Err Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SUNI_RACP_RCCL 0x56 /* RACP Receive Cell Counter LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SUNI_RACP_RCC 0x57 /* RACP Receive Cell Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SUNI_RACP_RCCM 0x58 /* RACP Receive Cell Counter MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SUNI_RACP_CFG 0x59 /* RACP Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* 0x5A-0x5F reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SUNI_TACP_CS 0x60 /* TACP Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SUNI_TACP_IUCHP 0x61 /* TACP Idle/Unassigned Cell Hdr Pat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SUNI_TACP_IUCPOP 0x62 /* TACP Idle/Unassigned Cell Payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) Octet Pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SUNI_TACP_FIFO 0x63 /* TACP FIFO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SUNI_TACP_TCCL 0x64 /* TACP Transmit Cell Counter LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SUNI_TACP_TCC 0x65 /* TACP Transmit Cell Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SUNI_TACP_TCCM 0x66 /* TACP Transmit Cell Counter MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SUNI_TACP_CFG 0x67 /* TACP Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SUNI_SPTB_CTRL 0x68 /* SPTB Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 0x69-0x7F reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SUNI_MT 0x80 /* Master Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* 0x81-0xFF reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* SUNI register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* MRI is reg 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SUNI_MRI_ID 0x0f /* R, SUNI revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SUNI_MRI_ID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SUNI_MRI_TYPE 0x70 /* R, SUNI type (lite is 011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SUNI_MRI_TYPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SUNI_MRI_TYPE_PM5346 0x3 /* S/UNI 155 LITE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SUNI_MRI_TYPE_PM5347 0x4 /* S/UNI 155 PLUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SUNI_MRI_TYPE_PM5350 0x7 /* S/UNI 155 ULTRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SUNI_MRI_TYPE_PM5355 0x1 /* S/UNI 622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SUNI_MRI_RESET 0x80 /* RW, reset & power down chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0: normal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 1: reset & low power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* MCM is reg 0x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SUNI_MCM_LLE 0x20 /* line loopback (PM5355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SUNI_MCM_DLE 0x10 /* diagnostic loopback (PM5355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* MCT is reg 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SUNI_MCT_LOOPT 0x01 /* RW, timing source, 0: from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TRCLK+/- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SUNI_MCT_DLE 0x02 /* RW, diagnostic loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SUNI_MCT_LLE 0x04 /* RW, line loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SUNI_MCT_FIXPTR 0x20 /* RW, disable transmit payload pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) adjustments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0: payload ptr controlled by TPOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ptr control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 1: payload pointer fixed at 522 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SUNI_MCT_LCDV 0x40 /* R, loss of cell delineation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SUNI_MCT_LCDE 0x80 /* RW, loss of cell delineation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) interrupt (1: on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* RSOP_CIE is reg 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SUNI_RSOP_CIE_OOFE 0x01 /* RW, enable interrupt on frame alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SUNI_RSOP_CIE_LOFE 0x02 /* RW, enable interrupt on loss of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) frame state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SUNI_RSOP_CIE_LOSE 0x04 /* RW, enable interrupt on loss of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) signal state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SUNI_RSOP_CIE_BIPEE 0x08 /* RW, enable interrupt on section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) BIP-8 error (B1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SUNI_RSOP_CIE_FOOF 0x20 /* W, force RSOP out of frame at next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SUNI_RSOP_CIE_DDS 0x40 /* RW, disable scrambling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* RSOP_SIS is reg 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SUNI_RSOP_SIS_OOFV 0x01 /* R, out of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SUNI_RSOP_SIS_LOFV 0x02 /* R, loss of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SUNI_RSOP_SIS_LOSV 0x04 /* R, loss of signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SUNI_RSOP_SIS_OOFI 0x08 /* R, out of frame interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SUNI_RSOP_SIS_LOFI 0x10 /* R, loss of frame interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SUNI_RSOP_SIS_LOSI 0x20 /* R, loss of signal interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SUNI_RSOP_SIS_BIPEI 0x40 /* R, section BIP-8 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* TSOP_CTRL is reg 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SUNI_TSOP_CTRL_LAIS 0x01 /* insert alarm indication signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SUNI_TSOP_CTRL_DS 0x40 /* disable scrambling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* TSOP_DIAG is reg 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SUNI_TSOP_DIAG_DFP 0x01 /* insert single bit error cont. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SUNI_TSOP_DIAG_DBIP8 0x02 /* insert section BIP err (cont) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SUNI_TSOP_DIAG_DLOS 0x04 /* set line to zero (loss of signal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* TLOP_DIAG is reg 0x21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SUNI_TLOP_DIAG_DBIP 0x01 /* insert line BIP err (continuously) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* SSTB_CTRL is reg 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SUNI_SSTB_CTRL_LEN16 0x01 /* path trace message length bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* RPOP_RC is reg 0x3D (PM5355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SUNI_RPOP_RC_ENSS 0x40 /* enable size bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* TPOP_DIAG is reg 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SUNI_TPOP_DIAG_PAIS 0x01 /* insert STS path alarm ind (cont) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SUNI_TPOP_DIAG_DB3 0x02 /* insert path BIP err (continuously) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* TPOP_APM is reg 0x46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SUNI_TPOP_APM_APTR 0x03 /* RW, arbitrary pointer, upper 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SUNI_TPOP_APM_APTR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SUNI_TPOP_APM_S 0x0c /* RW, "unused" bits of payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SUNI_TPOP_APM_S_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SUNI_TPOP_APM_NDF 0xf0 /* RW, NDF bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SUNI_TPOP_APM_NDF_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SUNI_TPOP_S_SONET 0 /* set S bits to 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SUNI_TPOP_S_SDH 2 /* set S bits to 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* RACP_IES is reg 0x51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SUNI_RACP_IES_FOVRI 0x02 /* R, FIFO overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SUNI_RACP_IES_UHCSI 0x04 /* R, uncorrectable HCS error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SUNI_RACP_IES_CHCSI 0x08 /* R, correctable HCS error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SUNI_RACP_IES_OOCDI 0x10 /* R, change of cell delineation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SUNI_RACP_IES_FIFOE 0x20 /* RW, enable FIFO overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SUNI_RACP_IES_HCSE 0x40 /* RW, enable HCS error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SUNI_RACP_IES_OOCDE 0x80 /* RW, enable cell delineation state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) change interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* TACP_CS is reg 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SUNI_TACP_CS_FIFORST 0x01 /* RW, reset transmit FIFO (sticky) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SUNI_TACP_CS_DSCR 0x02 /* RW, disable payload scrambling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SUNI_TACP_CS_HCAADD 0x04 /* RW, add coset polynomial to HCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SUNI_TACP_CS_DHCS 0x10 /* RW, insert HCS errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SUNI_TACP_CS_FOVRI 0x20 /* R, FIFO overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SUNI_TACP_CS_TSOCI 0x40 /* R, TSOC input high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SUNI_TACP_CS_FIFOE 0x80 /* RW, enable FIFO overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* TACP_IUCHP is reg 0x61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SUNI_TACP_IUCHP_CLP 0x01 /* RW, 8th bit of 4th octet of i/u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SUNI_TACP_IUCHP_PTI 0x0e /* RW, 5th-7th bits of 4th octet of i/u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SUNI_TACP_IUCHP_PTI_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SUNI_TACP_IUCHP_GFC 0xf0 /* RW, 1st-4th bits of 1st octet of i/u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SUNI_TACP_IUCHP_GFC_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* SPTB_CTRL is reg 0x68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SUNI_SPTB_CTRL_LEN16 0x01 /* path trace message length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* MT is reg 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SUNI_MT_HIZIO 0x01 /* RW, all but data bus & MP interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tri-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SUNI_MT_HIZDATA 0x02 /* W, also tri-state data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SUNI_MT_IOTST 0x04 /* RW, enable test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SUNI_MT_DBCTRL 0x08 /* W, control data bus by CSB pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SUNI_MT_PMCTST 0x10 /* W, PMC test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SUNI_MT_DS27_53 0x80 /* RW, select between 8- or 16- bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SUNI_IDLE_PATTERN 0x6a /* idle pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct suni_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct k_sonet_stats sonet_stats; /* link diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int loop_mode; /* loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int type; /* phy type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct atm_dev *dev; /* device back-pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct suni_priv *next; /* next SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int suni_init(struct atm_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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