^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Traverse Technologies -- https://www.traverse.com.au/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Xrio Limited -- http://www.xrio.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright © 2008 Traverse Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright © 2008 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Authors: Nathan Williams <nathan@traverse.com.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * David Woodhouse <dwmw2@infradead.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Treker Chen <treker@xrio.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/atm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/swab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VERSION "1.04"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_VERSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PTAG "solos-pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CONFIG_RAM_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FLAGS_ADDR 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQ_EN_ADDR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FPGA_VER 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IRQ_CLEAR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WRITE_FLASH 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PORTS 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FLASH_BLOCK 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FLASH_BUSY 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FPGA_MODE 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FLASH_MODE 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPIO_STATUS 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRIVER_VER 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DATA_RAM_SIZE 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BUF_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Old boards use ATMEL AD45DB161D flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ATMEL_FPGA_PAGE 528 /* FPGA flash page size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ATMEL_SOLOS_PAGE 512 /* Solos flash page size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATMEL_FPGA_BLOCK (ATMEL_FPGA_PAGE * 8) /* FPGA block size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATMEL_SOLOS_BLOCK (ATMEL_SOLOS_PAGE * 8) /* Solos block size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Current boards use M25P/M25PE SPI flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPI_FLASH_BLOCK (256 * 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RX_DMA_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FPGA_VERSION(a,b) (((a) << 8) + (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LEGACY_BUFFERS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DMA_SUPPORTED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int atmdebug = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int firmware_upgrade = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int fpga_upgrade = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int db_firmware_upgrade = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int db_fpga_upgrade = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pkt_hdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __le16 vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __le16 vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __le16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct solos_skb_cb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) uint32_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PKT_DATA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PKT_COMMAND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PKT_POPEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PKT_PCLOSE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PKT_STATUS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct solos_card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __iomem *config_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct atm_dev *atmdev[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct tasklet_struct tlet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) spinlock_t tx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spinlock_t tx_queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spinlock_t cli_queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spinlock_t param_queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct list_head param_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct sk_buff_head tx_queue[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct sk_buff_head cli_queue[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct sk_buff *tx_skb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sk_buff *rx_skb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned char *dma_bounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) wait_queue_head_t param_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) wait_queue_head_t fw_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int using_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int dma_alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int fpga_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int atmel_flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct solos_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pid_t pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct sk_buff *response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MODULE_DESCRIPTION("Solos PCI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_VERSION(VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MODULE_FIRMWARE("solos-FPGA.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MODULE_FIRMWARE("solos-Firmware.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MODULE_FIRMWARE("solos-db-FPGA.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MODULE_PARM_DESC(atmdebug, "Print ATM data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) module_param(reset, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) module_param(atmdebug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) module_param(firmware_upgrade, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) module_param(fpga_upgrade, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) module_param(db_firmware_upgrade, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) module_param(db_fpga_upgrade, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct atm_vcc *vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static uint32_t fpga_tx(struct solos_card *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static irqreturn_t solos_irq(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int atm_init(struct solos_card *, struct device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void atm_remove(struct solos_card *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void solos_bh(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int print_buffer(struct sk_buff *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct solos_card *card = atmdev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct solos_param prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct pkt_hdr *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) buflen = strlen(attr->attr.name) + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) header = skb_put(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) buflen = snprintf((void *)&header[1], buflen - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "L%05d\n%s\n", current->pid, attr->attr.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) skb_put(skb, buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) header->size = cpu_to_le16(buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) header->vpi = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) header->vci = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) header->type = cpu_to_le16(PKT_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) prm.pid = current->pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) prm.response = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) prm.port = SOLOS_CHAN(atmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_lock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) list_add(&prm.list, &card->param_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spin_unlock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) fpga_queue(card, prm.port, skb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) spin_lock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) list_del(&prm.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) spin_unlock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!prm.response)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) buflen = prm.response->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) memcpy(buf, prm.response->data, buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) kfree_skb(prm.response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct solos_card *card = atmdev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct solos_param prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct pkt_hdr *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) buflen = strlen(attr->attr.name) + 11 + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) header = skb_put(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) buflen = snprintf((void *)&header[1], buflen - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) skb_put(skb, buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) header->size = cpu_to_le16(buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) header->vpi = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) header->vci = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) header->type = cpu_to_le16(PKT_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) prm.pid = current->pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) prm.response = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) prm.port = SOLOS_CHAN(atmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) spin_lock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) list_add(&prm.list, &card->param_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_unlock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) fpga_queue(card, prm.port, skb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) spin_lock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) list_del(&prm.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_unlock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) skb = prm.response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) buflen = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Sometimes it has a newline, sometimes it doesn't. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (skb->data[buflen - 1] == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) buflen--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (buflen == 2 && !strncmp(skb->data, "OK", 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* We know we have enough space allocated for this; we allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) it ourselves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) skb->data[buflen] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static char *next_string(struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) char *this = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < skb->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (this[i] == '\n') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) this[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) skb_pull(skb, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!isprint(this[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Status packet has fields separated by \n, starting with a version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * for the information therein. Fields are....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * packet version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * RxBitRate (version >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * TxBitRate (version >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * State (version >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * LocalSNRMargin (version >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * LocalLineAttn (version >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) char *str, *state_str, *snr, *attn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int ver, rate_up, rate_down, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!card->atmdev[port])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) str = next_string(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = kstrtoint(str, 10, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_warn(&card->dev->dev, "Unexpected status interrupt version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ver < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) str = next_string(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!strcmp(str, "ERROR")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) err = kstrtoint(str, 10, &rate_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) str = next_string(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) err = kstrtoint(str, 10, &rate_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) state_str = next_string(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!state_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Anything but 'Showtime' is down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (strcmp(state_str, "Showtime")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_LOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) snr = next_string(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!snr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) attn = next_string(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!attn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) port, state_str, rate_down/1000, rate_up/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) card->atmdev[port]->link_rate = rate_down / 424;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) atm_dev_signal_change(card->atmdev[port], ATM_PHY_SIG_FOUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct solos_param *prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int cmdpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int found = 0, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (skb->len < 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) skb->data[6] != '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) err = kstrtoint(&skb->data[1], 10, &cmdpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spin_lock_irqsave(&card->param_queue_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) list_for_each_entry(prm, &card->param_queue, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (prm->port == port && prm->pid == cmdpid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) prm->response = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) skb_pull(skb, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) wake_up(&card->param_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spin_unlock_irqrestore(&card->param_queue_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static ssize_t console_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct solos_card *card = atmdev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) spin_lock(&card->cli_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) spin_unlock(&card->cli_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if(skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return sprintf(buf, "No data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) memcpy(buf, skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct pkt_hdr *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (size > (BUF_SIZE - sizeof(*header))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) header = skb_put(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) header->size = cpu_to_le16(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) header->vpi = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) header->vci = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) header->type = cpu_to_le16(PKT_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) skb_put_data(skb, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) fpga_queue(card, dev, skb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static ssize_t console_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct solos_card *card = atmdev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return err?:count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct geos_gpio_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct device_attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SOLOS_GPIO_ATTR(_name, _mode, _show, _store, _offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct geos_gpio_attr gpio_attr_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .attr = __ATTR(_name, _mode, _show, _store), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .offset = _offset }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static ssize_t geos_gpio_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct solos_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) uint32_t data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (count != 1 && (count != 2 || buf[1] != '\n'))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_lock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) data32 = ioread32(card->config_regs + GPIO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (buf[0] == '1') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) data32 |= 1 << gattr->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) iowrite32(data32, card->config_regs + GPIO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } else if (buf[0] == '0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) data32 &= ~(1 << gattr->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) iowrite32(data32, card->config_regs + GPIO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) count = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_unlock_irq(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static ssize_t geos_gpio_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct solos_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uint32_t data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) data32 = ioread32(card->config_regs + GPIO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) data32 = (data32 >> gattr->offset) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return sprintf(buf, "%d\n", data32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static ssize_t hardware_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct geos_gpio_attr *gattr = container_of(attr, struct geos_gpio_attr, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct solos_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint32_t data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) data32 = ioread32(card->config_regs + GPIO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) switch (gattr->offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* HardwareVersion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) data32 = data32 & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* HardwareVariant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) data32 = (data32 >> 5) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return sprintf(buf, "%d\n", data32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static DEVICE_ATTR_RW(console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #include "solos-attrlist.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static SOLOS_GPIO_ATTR(GPIO1, 0644, geos_gpio_show, geos_gpio_store, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static SOLOS_GPIO_ATTR(GPIO2, 0644, geos_gpio_show, geos_gpio_store, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static SOLOS_GPIO_ATTR(GPIO3, 0644, geos_gpio_show, geos_gpio_store, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static SOLOS_GPIO_ATTR(GPIO4, 0644, geos_gpio_show, geos_gpio_store, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static SOLOS_GPIO_ATTR(GPIO5, 0644, geos_gpio_show, geos_gpio_store, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static SOLOS_GPIO_ATTR(PushButton, 0444, geos_gpio_show, NULL, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static SOLOS_GPIO_ATTR(HardwareVersion, 0444, hardware_show, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static SOLOS_GPIO_ATTR(HardwareVariant, 0444, hardware_show, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #undef SOLOS_ATTR_RO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #undef SOLOS_ATTR_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static struct attribute *solos_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #include "solos-attrlist.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const struct attribute_group solos_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .attrs = solos_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "parameters",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct attribute *gpio_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &gpio_attr_GPIO1.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) &gpio_attr_GPIO2.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) &gpio_attr_GPIO3.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) &gpio_attr_GPIO4.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) &gpio_attr_GPIO5.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) &gpio_attr_PushButton.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &gpio_attr_HardwareVersion.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) &gpio_attr_HardwareVariant.attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const struct attribute_group gpio_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .attrs = gpio_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .name = "gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int flash_upgrade(struct solos_card *card, int chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) const char *fw_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int blocksize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int numblocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fw_name = "solos-FPGA.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (card->atmel_flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) blocksize = ATMEL_FPGA_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) blocksize = SPI_FLASH_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) fw_name = "solos-Firmware.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (card->atmel_flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) blocksize = ATMEL_SOLOS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) blocksize = SPI_FLASH_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (card->fpga_version > LEGACY_BUFFERS){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fw_name = "solos-db-FPGA.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (card->atmel_flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) blocksize = ATMEL_FPGA_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) blocksize = SPI_FLASH_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_info(&card->dev->dev, "FPGA version doesn't support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) " daughter board upgrades\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (card->fpga_version > LEGACY_BUFFERS){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) fw_name = "solos-Firmware.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (card->atmel_flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) blocksize = ATMEL_SOLOS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) blocksize = SPI_FLASH_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_info(&card->dev->dev, "FPGA version doesn't support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) " daughter board upgrades\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (request_firmware(&fw, fw_name, &card->dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_info(&card->dev->dev, "Flash upgrade starting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* New FPGAs require driver version before permitting flash upgrades */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) iowrite32(DRIVER_VERSION, card->config_regs + DRIVER_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) numblocks = fw->size / blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) iowrite32(1, card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) (void) ioread32(card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Set mode to Chip Erase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if(chip == 0 || chip == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if(chip == 1 || chip == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) iowrite32((chip * 2), card->config_regs + FLASH_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) iowrite32(1, card->config_regs + WRITE_FLASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) for (offset = 0; offset < fw->size; offset += blocksize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Clear write flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) iowrite32(0, card->config_regs + WRITE_FLASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Set mode to Block Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Copy block to buffer, swapping each 16 bits for Atmel flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) for(i = 0; i < blocksize; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) uint32_t word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (card->atmel_flash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) word = swahb32p((uint32_t *)(fw->data + offset + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) word = *(uint32_t *)(fw->data + offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if(card->fpga_version > LEGACY_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) iowrite32(word, FLASH_BUF + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) iowrite32(word, RX_BUF(card, 3) + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Specify block number and then trigger flash write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) iowrite32(1, card->config_regs + WRITE_FLASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) iowrite32(0, card->config_regs + WRITE_FLASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) iowrite32(0, card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) iowrite32(0, card->config_regs + FLASH_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static irqreturn_t solos_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct solos_card *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) iowrite32(0, card->config_regs + IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* If we're up and running, just kick the tasklet to process TX/RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (card->atmdev[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) tasklet_schedule(&card->tlet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) wake_up(&card->fw_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void solos_bh(unsigned long card_arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct solos_card *card = (void *)card_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) uint32_t card_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) uint32_t rx_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Since fpga_tx() is going to need to read the flags under its lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * it can return them to us so that we don't have to hit PCI MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * again for the same information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) card_flags = fpga_tx(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) for (port = 0; port < card->nr_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (card_flags & (0x10 << port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct pkt_hdr _hdr, *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (card->using_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) skb = card->rx_skb[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) card->rx_skb[port] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) RX_DMA_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) header = (void *)skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) size = le16_to_cpu(header->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) skb_put(skb, size + sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) skb_pull(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) header = &_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) rx_done |= 0x10 << port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) size = le16_to_cpu(header->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (size > (card->buffer_size - sizeof(*header))){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_warn(&card->dev->dev, "Invalid buffer size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Use netdev_alloc_skb() because it adds NET_SKB_PAD of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * headroom, and ensures we can route packets back out an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * Ethernet interface (for example) without having to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * reallocate. Adding NET_IP_ALIGN also ensures that both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * PPPoATM and PPPoEoBR2684 packets end up aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) skb = netdev_alloc_skb_ip_align(NULL, size + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) memcpy_fromio(skb_put(skb, size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) RX_BUF(card, port) + sizeof(*header),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (atmdebug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_info(&card->dev->dev, "Received: port %d\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) size, le16_to_cpu(header->vpi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) le16_to_cpu(header->vci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) print_buffer(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) switch (le16_to_cpu(header->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case PKT_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) le16_to_cpu(header->vci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_warn(&card->dev->dev, "Received packet for unknown VPI.VCI %d.%d on port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) le16_to_cpu(header->vpi), le16_to_cpu(header->vci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) atm_charge(vcc, skb->truesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) vcc->push(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) atomic_inc(&vcc->stats->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case PKT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (process_status(card, port, skb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) net_ratelimit()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) print_buffer(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case PKT_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) default: /* FIXME: Not really, surely? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (process_command(card, port, skb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) spin_lock(&card->cli_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (skb_queue_len(&card->cli_queue[port]) > 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) skb_queue_tail(&card->cli_queue[port], skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) spin_unlock(&card->cli_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Allocate RX skbs for any ports which need them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (card->using_dma && card->atmdev[port] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) !card->rx_skb[port]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Unlike the MMIO case (qv) we can't add NET_IP_ALIGN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * here; the FPGA can only DMA to addresses which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * aligned to 4 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct sk_buff *skb = dev_alloc_skb(RX_DMA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) SKB_CB(skb)->dma_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dma_map_single(&card->dev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) RX_DMA_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) iowrite32(SKB_CB(skb)->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) card->config_regs + RX_DMA_ADDR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) card->rx_skb[port] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_warn(&card->dev->dev, "Failed to allocate RX skb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* We'll have to try again later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) tasklet_schedule(&card->tlet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (rx_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct hlist_head *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct atm_vcc *vcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct sock *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) read_lock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) sk_for_each(s, head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) vcc = atm_sk(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (vcc->dev == dev && vcc->vci == vci &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) test_bit(ATM_VF_READY, &vcc->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) vcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int popen(struct atm_vcc *vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct solos_card *card = vcc->dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct pkt_hdr *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (vcc->qos.aal != ATM_AAL5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) vcc->qos.aal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) skb = alloc_skb(sizeof(*header), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) header = skb_put(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) header->size = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) header->vpi = cpu_to_le16(vcc->vpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) header->vci = cpu_to_le16(vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) header->type = cpu_to_le16(PKT_POPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) set_bit(ATM_VF_ADDR, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) set_bit(ATM_VF_READY, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static void pclose(struct atm_vcc *vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct solos_card *card = vcc->dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned char port = SOLOS_CHAN(vcc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct sk_buff *skb, *tmpskb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct pkt_hdr *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Remove any yet-to-be-transmitted packets from the pending queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) spin_lock(&card->tx_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) skb_queue_walk_safe(&card->tx_queue[port], skb, tmpskb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (SKB_CB(skb)->vcc == vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) skb_unlink(skb, &card->tx_queue[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) solos_pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) spin_unlock(&card->tx_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) skb = alloc_skb(sizeof(*header), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) header = skb_put(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) header->size = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) header->vpi = cpu_to_le16(vcc->vpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) header->vci = cpu_to_le16(vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) header->type = cpu_to_le16(PKT_PCLOSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) skb_get(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) fpga_queue(card, port, skb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (!wait_event_timeout(card->param_wq, !skb_shared(skb), 5 * HZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_warn(&card->dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "Timeout waiting for VCC close on port %d\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* Hold up vcc_destroy_socket() (our caller) until solos_bh() in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) tasklet has finished processing any incoming packets (and, more to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) the point, using the vcc pointer). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) tasklet_unlock_wait(&card->tlet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) clear_bit(ATM_VF_ADDR, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int print_buffer(struct sk_buff *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int len,i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) char msg[500];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) char item[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) len = buf->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) for (i = 0; i < len; i++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if(i % 8 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) sprintf(msg, "%02X: ", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) sprintf(item,"%02X ",*(buf->data + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) strcat(msg, item);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if(i % 8 == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) sprintf(item, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) strcat(msg, item);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) printk(KERN_DEBUG "%s", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (i % 8 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) sprintf(item, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) strcat(msg, item);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) printk(KERN_DEBUG "%s", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) printk(KERN_DEBUG "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct atm_vcc *vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) int old_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) SKB_CB(skb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spin_lock_irqsave(&card->tx_queue_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) old_len = skb_queue_len(&card->tx_queue[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) skb_queue_tail(&card->tx_queue[port], skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (!old_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) card->tx_mask |= (1 << port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) spin_unlock_irqrestore(&card->tx_queue_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Theoretically we could just schedule the tasklet here, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) that introduces latency we don't want -- it's noticeable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (!old_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) fpga_tx(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static uint32_t fpga_tx(struct solos_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) uint32_t tx_pending, card_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) uint32_t tx_started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) unsigned char port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) spin_lock_irqsave(&card->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) card_flags = ioread32(card->config_regs + FLAGS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * The queue lock is required for _writing_ to tx_mask, but we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * OK to read it here without locking. The only potential update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * that we could race with is in fpga_queue() where it sets a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * for a new port... but it's going to call this function again if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * it's doing that, anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) tx_pending = card->tx_mask & ~card_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) for (port = 0; tx_pending; tx_pending >>= 1, port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (tx_pending & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct sk_buff *oldskb = card->tx_skb[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (oldskb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dma_unmap_single(&card->dev->dev, SKB_CB(oldskb)->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) oldskb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) card->tx_skb[port] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) spin_lock(&card->tx_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) skb = skb_dequeue(&card->tx_queue[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) card->tx_mask &= ~(1 << port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) spin_unlock(&card->tx_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (skb && !card->using_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) tx_started |= 1 << port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) oldskb = skb; /* We're done with this skb already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) } else if (skb && card->using_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) unsigned char *data = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if ((unsigned long)data & card->dma_alignment) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) data = card->dma_bounce + (BUF_SIZE * port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) memcpy(data, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SKB_CB(skb)->dma_addr = dma_map_single(&card->dev->dev, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) card->tx_skb[port] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) iowrite32(SKB_CB(skb)->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) card->config_regs + TX_DMA_ADDR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!oldskb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Clean up and free oldskb now it's gone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (atmdebug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct pkt_hdr *header = (void *)oldskb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int size = le16_to_cpu(header->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) skb_pull(oldskb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dev_info(&card->dev->dev, "Transmitted: port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) size, le16_to_cpu(header->vpi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) le16_to_cpu(header->vci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) print_buffer(oldskb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) vcc = SKB_CB(oldskb)->vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (vcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) atomic_inc(&vcc->stats->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) solos_pop(vcc, oldskb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dev_kfree_skb_irq(oldskb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) wake_up(&card->param_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (tx_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) spin_unlock_irqrestore(&card->tx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return card_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct solos_card *card = vcc->dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct pkt_hdr *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int pktlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pktlen = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (pktlen > (BUF_SIZE - sizeof(*header))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) solos_pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!skb_clone_writable(skb, sizeof(*header))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int expand_by = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (skb_headroom(skb) < sizeof(*header))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) expand_by = sizeof(*header) - skb_headroom(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) solos_pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) header = skb_push(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* This does _not_ include the size of the header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) header->size = cpu_to_le16(pktlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) header->vpi = cpu_to_le16(vcc->vpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) header->vci = cpu_to_le16(vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) header->type = cpu_to_le16(PKT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static const struct atmdev_ops fpga_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .open = popen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .close = pclose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .ioctl = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .send = psend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .send_oam = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .phy_put = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .phy_get = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .change_qos = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .proc_read = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .owner = THIS_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) uint16_t fpga_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) uint8_t major_ver, minor_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) uint32_t data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct solos_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) card = kzalloc(sizeof(*card), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) card->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) init_waitqueue_head(&card->fw_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) init_waitqueue_head(&card->param_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) err = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dev_warn(&dev->dev, "Failed to enable PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) err = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) err = pci_request_regions(dev, "solos");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_warn(&dev->dev, "Failed to request regions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (!card->config_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) dev_warn(&dev->dev, "Failed to ioremap config registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) goto out_release_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!card->buffers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) goto out_unmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) iowrite32(1, card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ioread32(card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) iowrite32(0, card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ioread32(card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) data32 = ioread32(card->config_regs + FPGA_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) fpga_ver = (data32 & 0x0000FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) major_ver = ((data32 & 0xFF000000) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) minor_ver = ((data32 & 0x00FF0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (card->fpga_version > LEGACY_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) card->buffer_size = BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) card->buffer_size = OLD_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) major_ver, minor_ver, fpga_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (fpga_ver < 37 && (fpga_upgrade || firmware_upgrade ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) db_fpga_upgrade || db_firmware_upgrade)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_warn(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) "FPGA too old; cannot upgrade flash. Use JTAG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) fpga_upgrade = firmware_upgrade = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) db_fpga_upgrade = db_firmware_upgrade = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Stopped using Atmel flash after 0.03-38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (fpga_ver < 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) card->atmel_flash = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) card->atmel_flash = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) data32 = ioread32(card->config_regs + PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) card->nr_ports = (data32 & 0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (card->fpga_version >= DMA_SUPPORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) card->using_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (1) { /* All known FPGA versions so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) card->dma_alignment = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) card->dma_bounce = kmalloc_array(card->nr_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) BUF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!card->dma_bounce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_warn(&card->dev->dev, "Failed to allocate DMA bounce buffers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Fallback to MMIO doesn't work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) goto out_unmap_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) card->using_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* Set RX empty flag for all ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) pci_set_drvdata(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) spin_lock_init(&card->tx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) spin_lock_init(&card->tx_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) spin_lock_init(&card->cli_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) spin_lock_init(&card->param_queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) INIT_LIST_HEAD(&card->param_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "solos-pci", card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) goto out_unmap_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) iowrite32(1, card->config_regs + IRQ_EN_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (fpga_upgrade)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) flash_upgrade(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (firmware_upgrade)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) flash_upgrade(card, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (db_fpga_upgrade)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) flash_upgrade(card, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (db_firmware_upgrade)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) flash_upgrade(card, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) err = atm_init(card, &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) goto out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (card->fpga_version >= DMA_SUPPORTED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) sysfs_create_group(&card->dev->dev.kobj, &gpio_attr_group))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_err(&card->dev->dev, "Could not register parameter group for GPIOs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) iowrite32(0, card->config_regs + IRQ_EN_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) free_irq(dev->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) tasklet_kill(&card->tlet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) out_unmap_both:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) kfree(card->dma_bounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) pci_iounmap(dev, card->buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) out_unmap_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) pci_iounmap(dev, card->config_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) out_release_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static int atm_init(struct solos_card *card, struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) for (i = 0; i < card->nr_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct pkt_hdr *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) skb_queue_head_init(&card->tx_queue[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) skb_queue_head_init(&card->cli_queue[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) card->atmdev[i] = atm_dev_register("solos-pci", parent, &fpga_ops, -1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (!card->atmdev[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) atm_remove(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) card->atmdev[i]->ci_range.vpi_bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) card->atmdev[i]->ci_range.vci_bits = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) card->atmdev[i]->dev_data = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) card->atmdev[i]->phy_data = (void *)(unsigned long)i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) atm_dev_signal_change(card->atmdev[i], ATM_PHY_SIG_FOUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) skb = alloc_skb(sizeof(*header), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) header = skb_put(skb, sizeof(*header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) header->size = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) header->vpi = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) header->vci = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) header->type = cpu_to_le16(PKT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) fpga_queue(card, i, skb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static void atm_remove(struct solos_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) for (i = 0; i < card->nr_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (card->atmdev[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) atm_dev_deregister(card->atmdev[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) skb = card->rx_skb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) RX_DMA_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) skb = card->tx_skb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dma_unmap_single(&card->dev->dev, SKB_CB(skb)->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) while ((skb = skb_dequeue(&card->tx_queue[i])))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static void fpga_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct solos_card *card = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* Disable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) iowrite32(0, card->config_regs + IRQ_EN_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* Reset FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) iowrite32(1, card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) (void)ioread32(card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (card->fpga_version >= DMA_SUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) sysfs_remove_group(&card->dev->dev.kobj, &gpio_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) atm_remove(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) free_irq(dev->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) tasklet_kill(&card->tlet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) kfree(card->dma_bounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Release device from reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) iowrite32(0, card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) (void)ioread32(card->config_regs + FPGA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pci_iounmap(dev, card->buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) pci_iounmap(dev, card->config_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const struct pci_device_id fpga_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static struct pci_driver fpga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .name = "solos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .id_table = fpga_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .probe = fpga_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .remove = fpga_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static int __init solos_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) BUILD_BUG_ON(sizeof(struct solos_skb_cb) > sizeof(((struct sk_buff *)0)->cb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return pci_register_driver(&fpga_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static void __exit solos_pci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) pci_unregister_driver(&fpga_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) module_init(solos_pci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) module_exit(solos_pci_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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