^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * nicstar.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Header file for the nicstar device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Rui Prior (rprior@inescn.pt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (C) INESC 1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _LINUX_NICSTAR_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _LINUX_NICSTAR_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Includes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/uio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/atm_nicstar.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) controlled by the device driver. Must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) be <= 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #undef RCQ_SUPPORT /* Do not define this for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Define 4096 only if (all) your card(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) have 32K x 32bit SRAM, in which case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) setting this to 16384 will just waste a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) lot of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Setting this to 4096 for a card with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 128K x 32bit SRAM will limit the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) VCI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*#define NS_PCI_LATENCY 64*//* Must be a multiple of 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Number of buffers initially allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NUM_SB 32 /* Must be even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NUM_LB 24 /* Must be even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NUM_HB 8 /* Pre-allocated huge buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NUM_IOVB 48 /* Iovec buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Lower level for count of buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MIN_SB 8 /* Must be even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MIN_LB 8 /* Must be even */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MIN_HB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MIN_IOVB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Upper level for count of buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAX_SB 64 /* Must be even, <= 508 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX_LB 48 /* Must be even, <= 508 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX_HB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAX_IOVB 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* These are the absolute maximum allowed for the ioctl() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TOP_SB 256 /* Must be even, <= 508 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TOP_LB 128 /* Must be even, <= 508 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TOP_HB 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TOP_IOVB 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #undef ENABLE_TSQFIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SCQFULL_TIMEOUT (5 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NS_POLL_PERIOD (HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCR_TOLERANCE (1.0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* ESI stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* #defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NS_IOREMAP_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * BUF_XX distinguish the Rx buffers depending on their (small/large) size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * BUG_SM and BUG_LG are both used by the driver and the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * BUF_NONE is only used by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BUF_NONE 0xffffffff /* Software only: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* NICStAR structures located in host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * RSQ - Receive Status Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Written by the NICStAR, read by the device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) typedef struct ns_rsqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 buffer_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 final_aal5_crc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 word_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } ns_rsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ns_rsqe_vpi(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ns_rsqe_vci(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define NS_RSQE_VALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define NS_RSQE_NZGFC 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NS_RSQE_EOPDU 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define NS_RSQE_BUFSIZE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NS_RSQE_CONGESTION 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define NS_RSQE_CLP 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NS_RSQE_CRCERR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define NS_RSQE_BUFSIZE_SM 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define NS_RSQE_BUFSIZE_LG 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ns_rsqe_valid(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ns_rsqe_nzgfc(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ns_rsqe_eopdu(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ns_rsqe_bufsize(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ns_rsqe_congestion(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ns_rsqe_clp(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ns_rsqe_crcerr(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ns_rsqe_cellcount(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ns_rsqe_init(ns_rsqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define NS_RSQ_ALIGNMENT NS_RSQSIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * RCQ - Raw Cell Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Written by the NICStAR, read by the device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) typedef struct cell_payload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 word[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } cell_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) typedef struct ns_rcqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 word_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 word_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 word_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cell_payload payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } ns_rcqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define NS_RCQE_SIZE 64 /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ns_rcqe_islast(ns_rcqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ns_rcqe_cellheader(ns_rcqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) (le32_to_cpu((ns_rcqep)->word_1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ns_rcqe_nextbufhandle(ns_rcqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (le32_to_cpu((ns_rcqep)->word_2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * SCQ - Segmentation Channel Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Written by the device driver, read by the NICStAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) typedef struct ns_scqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 word_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 word_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 word_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } ns_scqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) or TSR (Transmit Status Requests) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define NS_SCQE_TYPE_TBD 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define NS_SCQE_TYPE_TSR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define NS_TBD_EOPDU 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NS_TBD_AAL0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define NS_TBD_AAL34 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define NS_TBD_AAL5 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define NS_TBD_VPI_MASK 0x0FF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define NS_TBD_VCI_MASK 0x000FFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define NS_TBD_VPI_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define NS_TBD_VCI_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ns_tbd_mkword_1(flags, m, n, buflen) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ns_tbd_mkword_1_novbr(flags, buflen) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (cpu_to_le32((flags) | (buflen) | 0x00810000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ns_tbd_mkword_3(control, pdulen) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (cpu_to_le32((control) << 16 | (pdulen)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define NS_TSR_INTENABLE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ns_tsr_mkword_1(flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ns_tsr_mkword_2(scdi, scqi) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ns_scqe_is_tsr(ns_scqep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VBR_SCQ_NUM_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VBR_SCQSIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CBR_SCQ_NUM_ENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CBR_SCQSIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define NS_SCQE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * TSQ - Transmit Status Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Written by the NICStAR, read by the device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) typedef struct ns_tsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 word_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } ns_tsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* NOTE: The first word can be a status word copied from the TSR which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) originated the TSI, or a timer overflow indicator. In this last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case, the value of the first word is all zeroes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define NS_TSI_EMPTY 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ns_tsi_isempty(ns_tsip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ns_tsi_gettimestamp(ns_tsip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ns_tsi_init(ns_tsip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define NS_TSQSIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define NS_TSQ_NUM_ENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define NS_TSQ_ALIGNMENT 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ns_tsi_tmrof(ns_tsip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (le32_to_cpu((ns_tsip)->word_1) == 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ns_tsi_getscdindex(ns_tsip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ns_tsi_getscqpos(ns_tsip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* NICStAR structures located in local SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * RCT - Receive Connection Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Written by both the NICStAR and the device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) typedef struct ns_rcte {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 buffer_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 aal5_crc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } ns_rcte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define NS_RCTE_NZGFC 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define NS_RCTE_CONNECTOPEN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define NS_RCTE_AALMASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define NS_RCTE_AAL0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define NS_RCTE_AAL34 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define NS_RCTE_AAL5 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define NS_RCTE_RCQ 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define NS_RCTE_RAWCELLINTEN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define NS_RCTE_RXCONSTCELLADDR 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define NS_RCTE_BUFFVALID 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define NS_RCTE_FBDSIZE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define NS_RCTE_EFCI 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define NS_RCTE_CLP 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define NS_RCTE_CRCERROR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define NS_RCTE_CELLCOUNT_MASK 0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define NS_RCTE_FBDSIZE_SM 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define NS_RCTE_FBDSIZE_LG 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* NOTE: We could make macros to contruct the first word of the RCTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) but that doesn't seem to make much sense... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * FBD - Free Buffer Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Written by the device driver using via the command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) typedef struct ns_fbd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 buffer_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } ns_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * TST - Transmit Schedule Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Written by the device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) typedef u32 ns_tste;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define NS_TST_OPCODE_MASK 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define NS_TST_OPCODE_VARIABLE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define NS_TST_OPCODE_END 0x60000000 /* Jump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ns_tste_make(opcode, sramad) (opcode | sramad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) - When the opcode is FIXED, sramad specifies the SRAM address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SCD for that fixed rate channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) - When the opcode is END, sramad specifies the SRAM address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) location of the next TST entry to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * SCD - Segmentation Channel Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Written by both the device driver and the NICStAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) typedef struct ns_scd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 word_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 partial_aal5_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ns_scqe cache_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ns_scqe cache_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } ns_scd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define NS_SCD_TAIL_MASK_VAR 0x00001FF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define NS_SCD_TAIL_MASK_FIX 0x000003F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define NS_SCD_HEAD_MASK_VAR 0x00001FF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define NS_SCD_HEAD_MASK_FIX 0x000003F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define NS_SCD_XMITFOREVER 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* NOTE: There are other fields in word 2 of the SCD, but as they should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) not be needed in the device driver they are not defined here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* NICStAR local SRAM memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define NS_RCT 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define NS_RCT_32_END 0x03FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define NS_RCT_128_END 0x0FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define NS_UNUSED_32 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define NS_UNUSED_128 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define NS_UNUSED_END 0x1BFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define NS_TST_FRSCD 0x1C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define NS_TST_FRSCD_END 0x1E7DB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define NS_VRSCD2 0x1E7DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define NS_VRSCD2_END 0x1E7E7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define NS_VRSCD1 0x1E7E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define NS_VRSCD1_END 0x1E7F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define NS_VRSCD0 0x1E7F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define NS_VRSCD0_END 0x1E7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define NS_RXFIFO 0x1E800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define NS_RXFIFO_END 0x1F7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define NS_SMFBQ 0x1F800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define NS_SMFBQ_END 0x1FBFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define NS_LGFBQ 0x1FC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define NS_LGFBQ_END 0x1FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* NISCtAR operation registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) enum ns_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DR0 = 0x00, /* Data Register 0 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DR1 = 0x04, /* Data Register 1 W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DR2 = 0x08, /* Data Register 2 W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DR3 = 0x0C, /* Data Register 3 W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CMD = 0x10, /* Command W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CFG = 0x14, /* Configuration R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) STAT = 0x18, /* Status R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) RSQB = 0x1C, /* Receive Status Queue Base W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) RSQT = 0x20, /* Receive Status Queue Tail R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RSQH = 0x24, /* Receive Status Queue Head W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CDC = 0x28, /* Cell Drop Counter R/clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ICC = 0x30, /* Invalid Cell Count R/clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) RAWCT = 0x34, /* Raw Cell Tail R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) TMR = 0x38, /* Timer R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) TSTB = 0x3C, /* Transmit Schedule Table Base R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) TSQB = 0x40, /* Transmit Status Queue Base W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) TSQT = 0x44, /* Transmit Status Queue Tail R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) TSQH = 0x48, /* Transmit Status Queue Head W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) GP = 0x4C, /* General Purpose R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) VPM = 0x50 /* VPI/VCI Mask W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* NICStAR commands issued to the CMD register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Top 4 bits are command opcode, lower 28 are parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define NS_CMD_NO_OPERATION 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* params always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* b19{1=open,0=close} b18-2{SRAM addr} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define NS_CMD_WRITE_SRAM 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* b18-2{SRAM addr} b1-0{burst size} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define NS_CMD_READ_SRAM 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* b18-2{SRAM addr} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define NS_CMD_WRITE_FREEBUFQ 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* b0{large buf indicator} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define NS_CMD_READ_UTILITY 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define NS_CMD_WRITE_UTILITY 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* NICStAR configuration bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define NS_CFG_SWRST 0x80000000 /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define NS_CFG_SMBUFSIZE_48 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define NS_CFG_SMBUFSIZE_96 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define NS_CFG_SMBUFSIZE_240 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define NS_CFG_SMBUFSIZE_2048 0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define NS_CFG_LGBUFSIZE_2048 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define NS_CFG_LGBUFSIZE_4096 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define NS_CFG_LGBUFSIZE_8192 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define NS_CFG_LGBUFSIZE_16384 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define NS_CFG_RSQSIZE_2048 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define NS_CFG_RSQSIZE_4096 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define NS_CFG_RSQSIZE_8192 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define NS_CFG_VPIBITS_0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define NS_CFG_VPIBITS_1 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define NS_CFG_VPIBITS_2 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define NS_CFG_VPIBITS_8 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define NS_CFG_RXINT_NOINT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define NS_CFG_RXINT_NODELAY 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define NS_CFG_RXINT_314US 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define NS_CFG_RXINT_624US 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define NS_CFG_RXINT_899US 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* NICStAR STATus bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define NS_STAT_EOPDU 0x00000020 /* End of PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* #defines which depend on other #defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define NS_TST0 NS_TST_FRSCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define NS_FRSCD_SIZE 12 /* 12 dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #if (NS_SMBUFSIZE == 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #elif (NS_SMBUFSIZE == 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #elif (NS_SMBUFSIZE == 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #elif (NS_SMBUFSIZE == 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #error NS_SMBUFSIZE is incorrect in nicstar.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #endif /* NS_SMBUFSIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #if (NS_LGBUFSIZE == 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #elif (NS_LGBUFSIZE == 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #elif (NS_LGBUFSIZE == 8192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #elif (NS_LGBUFSIZE == 16384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #error NS_LGBUFSIZE is incorrect in nicstar.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #endif /* NS_LGBUFSIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #if (NS_RSQSIZE == 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #elif (NS_RSQSIZE == 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #elif (NS_RSQSIZE == 8192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #error NS_RSQSIZE is incorrect in nicstar.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #endif /* NS_RSQSIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #if (NS_VPIBITS == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #elif (NS_VPIBITS == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #elif (NS_VPIBITS == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #elif (NS_VPIBITS == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #error NS_VPIBITS is incorrect in nicstar.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #endif /* NS_VPIBITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #ifdef RCQ_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define NS_CFG_RAWIE_OPT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #endif /* RCQ_SUPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #ifdef ENABLE_TSQFIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define NS_CFG_TSQFIE_OPT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #endif /* ENABLE_TSQFIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* PCI stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #ifndef PCI_VENDOR_ID_IDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define PCI_VENDOR_ID_IDT 0x111D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif /* PCI_VENDOR_ID_IDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #ifndef PCI_DEVICE_ID_IDT_IDT77201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define PCI_DEVICE_ID_IDT_IDT77201 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #endif /* PCI_DEVICE_ID_IDT_IDT77201 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Device driver structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct ns_skb_prv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int iovcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define NS_PRV_BUFTYPE(skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->buf_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define NS_PRV_DMA(skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define NS_PRV_IOVCNT(skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) (((struct ns_skb_prv *)(ATM_SKB(skb)+1))->iovcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) typedef struct tsq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) void *org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ns_tsi *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ns_tsi *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ns_tsi *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } tsq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) typedef struct scq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) void *org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ns_scqe *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ns_scqe *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ns_scqe *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) volatile ns_scqe *tail; /* Not related to the nicstar register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) unsigned num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct sk_buff **skb; /* Pointer to an array of pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) to the sk_buffs used for tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 scd; /* SRAM address of the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int tbd_count; /* Only meaningful on variable rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) wait_queue_head_t scqfull_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) volatile char full; /* SCQ full indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spinlock_t lock; /* SCQ spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } scq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) typedef struct rsq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) void *org;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ns_rsqe *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ns_rsqe *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ns_rsqe *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } rsq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) typedef struct skb_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) volatile int count; /* number of buffers in the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct sk_buff_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) } skb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* NOTE: for small and large buffer pools, the count is not used, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) actual value used for buffer management is the one read from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) card. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) typedef struct vc_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) volatile unsigned int tx:1; /* TX vc? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) volatile unsigned int rx:1; /* RX vc? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct atm_vcc *tx_vcc, *rx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct sk_buff *rx_iov; /* RX iovector skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) scq_info *scq; /* To keep track of the SCQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 cbr_scd; /* SRAM address of the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) SCD. 0x00000000 for UBR/VBR/ABR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int tbd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) } vc_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) typedef struct ns_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int index; /* Card ID to the device driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int sram_size; /* In k x 32bit words. 32 or 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) void __iomem *membase; /* Card's memory base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned long max_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int rct_size; /* Number of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int vpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int vcibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct pci_dev *pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct idr idr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct atm_dev *atmdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) tsq_info tsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) rsq_info rsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) scq_info *scq0, *scq1, *scq2; /* VBR SCQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) skb_pool sbpool; /* Small buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) skb_pool lbpool; /* Large buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) skb_pool hbpool; /* Pre-allocated huge buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) skb_pool iovpool; /* iovector buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) volatile int efbie; /* Empty free buf. queue int. enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) volatile u32 tst_addr; /* SRAM address of the TST in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) volatile int tst_free_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) vc_map vcmap[NS_MAX_RCTSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) vc_map *tste2vc[NS_TST_NUM_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) vc_map *scd2vc[NS_FRSCD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) buf_nr sbnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) buf_nr lbnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) buf_nr hbnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) buf_nr iovnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int sbfqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int lbfqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct sk_buff *sm_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u32 sm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct sk_buff *lg_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 lg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct sk_buff *rcbuf; /* Current raw cell buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct ns_rcqe *rawcell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u32 rawch; /* Raw cell queue head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) unsigned intcnt; /* Interrupt counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) spinlock_t int_lock; /* Interrupt lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) spinlock_t res_lock; /* Card resource lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) } ns_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) CBR vc. If the entry is not allocated, it must be NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) There are two TSTs so the driver can modify them on the fly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) without stopping the transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) scd2vc allows us to find out unused fixed rate SCDs, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) they must have a NULL pointer here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #endif /* _LINUX_NICSTAR_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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