^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/atm/midway.h - Efficient Networks Midway (SAR) description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DRIVERS_ATM_MIDWAY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRIVERS_ATM_MIDWAY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define NR_VCI 1024 /* number of VCIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define NR_VCI_LD 10 /* log2(NR_VCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NR_DMA_RX 512 /* RX DMA queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NR_DMA_TX 512 /* TX DMA queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NR_SERVICE NR_VCI /* service list size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NR_CHAN 8 /* number of TX channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TS_CLOCK 25000000 /* traffic shaper clock (cell/sec) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAP_MAX_SIZE 0x00400000 /* memory window for max config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EPROM_SIZE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MEM_VALID 0xffc00000 /* mask base address with this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHY_BASE 0x00020000 /* offset of PHY register are */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_BASE 0x00040000 /* offset of Midway register area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RAM_BASE 0x00200000 /* offset of RAM area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RAM_INCREMENT 0x00020000 /* probe for RAM every 128kB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MID_VCI_BASE RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MID_DMA_RX_BASE (MID_VCI_BASE+NR_VCI*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MID_DMA_TX_BASE (MID_DMA_RX_BASE+NR_DMA_RX*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MID_SERVICE_BASE (MID_DMA_TX_BASE+NR_DMA_TX*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MID_FREE_BASE (MID_SERVICE_BASE+NR_SERVICE*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAC_LEN 6 /* atm.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MID_MIN_BUF_SIZE (1024) /* 1 kB is minimum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MID_MAX_BUF_SIZE (128*1024) /* 128 kB is maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RX_DESCR_SIZE 1 /* RX PDU descr is 1 longword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TX_DESCR_SIZE 2 /* TX PDU descr is 2 longwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AAL5_TRAILER (ATM_AAL5_TRAILER/4) /* AAL5 trailer is 2 longwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TX_GAP 8 /* TX buffer gap (words) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Midway Reset/ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * All values read-only. Writing to this register resets Midway chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MID_RES_ID_MCON 0x00 /* Midway Reset/ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MID_ID 0xf0000000 /* Midway version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MID_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MID_MOTHER_ID 0x00000700 /* mother board id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MID_MOTHER_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MID_CON_TI 0x00000080 /* 0: normal ctrl; 1: SABRE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MID_CON_SUNI 0x00000040 /* 0: UTOPIA; 1: SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MID_CON_V6 0x00000020 /* 0: non-pipel UTOPIA (required iff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) !CON_SUNI; 1: UTOPIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAUGHTER_ID 0x0000001f /* daughter board id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Interrupt Status Acknowledge, Interrupt Status & Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MID_ISA 0x01 /* Interrupt Status Acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MID_IS 0x02 /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MID_IE 0x03 /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MID_TX_COMPLETE_7 0x00010000 /* channel N completed a PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MID_TX_COMPLETE_6 0x00008000 /* transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MID_TX_COMPLETE_5 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MID_TX_COMPLETE_4 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MID_TX_COMPLETE_3 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MID_TX_COMPLETE_2 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MID_TX_COMPLETE_1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MID_TX_COMPLETE_0 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MID_TX_COMPLETE 0x0001fe00 /* any TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MID_TX_DMA_OVFL 0x00000100 /* DMA to adapter overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MID_TX_IDENT_MISM 0x00000080 /* TX: ident mismatch => halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MID_DMA_LERR_ACK 0x00000040 /* LERR - SBus ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MID_DMA_ERR_ACK 0x00000020 /* DMA error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MID_RX_DMA_COMPLETE 0x00000010 /* DMA to host done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MID_TX_DMA_COMPLETE 0x00000008 /* DMA from host done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MID_SERVICE 0x00000004 /* something in service list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MID_SUNI_INT 0x00000002 /* interrupt from SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MID_STAT_OVFL 0x00000001 /* statistics overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Master Control/Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MID_MC_S 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MID_INT_SELECT 0x000001C0 /* Interrupt level (000: off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MID_INT_SEL_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MID_TX_LOCK_MODE 0x00000020 /* 0: streaming; 1: TX ovfl->lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MID_DMA_ENABLE 0x00000010 /* R: 0: disable; 1: enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) W: 0: no change; 1: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MID_TX_ENABLE 0x00000008 /* R: 0: TX disabled; 1: enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) W: 0: no change; 1: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MID_RX_ENABLE 0x00000004 /* like TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MID_WAIT_1MS 0x00000002 /* R: 0: timer not running; 1: running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) W: 0: no change; 1: no interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) for 1 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MID_WAIT_500US 0x00000001 /* like WAIT_1MS, but 0.5 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Cleared when reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MID_STAT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MID_VCI_TRASH 0xFFFF0000 /* trashed cells because of VCI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MID_VCI_TRASH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MID_OVFL_TRASH 0x0000FFFF /* trashed cells because of overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Address registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MID_SERV_WRITE 0x06 /* free pos in service area (R, 10 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MID_DMA_ADDR 0x07 /* virtual DMA address (R, 32 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MID_DMA_WR_RX 0x08 /* (RW, 9 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MID_DMA_RD_RX 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MID_DMA_WR_TX 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MID_DMA_RD_TX 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Transmit Place Registers (0x10+4*channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MID_TX_PLACE(c) (0x10+4*(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MID_SIZE 0x00003800 /* size, N*256 x 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MID_SIZE_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MID_LOCATION 0x000007FF /* location in adapter memory (word) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MID_LOC_SKIP 8 /* 8 bits of location are always zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (applies to all uses of location) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Transmit ReadPtr Registers (0x11+4*channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MID_TX_RDPTR(c) (0x11+4*(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MID_READ_PTR 0x00007FFF /* next word for PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Transmit DescrStart Registers (0x12+4*channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MID_TX_DESCRSTART(c) (0x12+4*(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MID_DESCR_START 0x00007FFF /* seg buffer being DMAed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ENI155_MAGIC 0xa54b872d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct midway_eprom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned char mac[MAC_LEN],inv_mac[MAC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned char pad[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 serial,inv_serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 magic,inv_magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * VCI table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MID_VCI_IN_SERVICE 0x00000001 /* set if VCI is currently in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) service list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MID_VCI_SIZE 0x00038000 /* reassembly buffer size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 2*<size> kB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MID_VCI_SIZE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MID_VCI_LOCATION 0x1ffc0000 /* buffer location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MID_VCI_LOCATION_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MID_VCI_PTI_MODE 0x20000000 /* 0: trash, 1: preserve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MID_VCI_MODE 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MID_VCI_MODE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MID_VCI_READ 0x00007fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MID_VCI_READ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MID_VCI_DESCR 0x7fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MID_VCI_DESCR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MID_VCI_COUNT 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MID_VCI_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MID_VCI_STATE 0x0000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MID_VCI_STATE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MID_VCI_WRITE 0x7fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MID_VCI_WRITE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MID_MODE_TRASH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MID_MODE_RAW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MID_MODE_AAL5 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Reassembly buffer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MID_RED_COUNT 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MID_RED_CRC_ERR 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MID_RED_T 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MID_RED_CE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MID_RED_CLP 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MID_RED_IDEN 0xfe000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MID_RED_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MID_RED_RX_ID 0x1b /* constant identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Segmentation buffer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MID_SEG_COUNT MID_RED_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MID_SEG_RATE 0x01f80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MID_SEG_RATE_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MID_SEG_PR 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MID_SEG_PR_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MID_SEG_AAL5 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MID_SEG_ID 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MID_SEG_ID_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MID_SEG_MAX_RATE 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MID_SEG_CLP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MID_SEG_PTI 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MID_SEG_PTI_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MID_SEG_VCI 0x00003ff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MID_SEG_VCI_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MID_SEG_TX_ID 0xb /* constant identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * DMA entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MID_DMA_COUNT 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MID_DMA_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MID_DMA_END 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MID_DMA_TYPE 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MID_DT_JK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MID_DT_WORD 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MID_DT_2W 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MID_DT_4W 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MID_DT_8W 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MID_DT_16W 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MID_DT_2WM 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MID_DT_4WM 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MID_DT_8WM 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MID_DT_16WM 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* only for RX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MID_DMA_VCI 0x0000ffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MID_DMA_VCI_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* only for TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MID_DMA_CHAN 0x000001c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MID_DMA_CHAN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MID_DT_BYTE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MID_DT_HWORD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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