^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This driver supports ATM cards based on the Efficient "Lanai"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * chipset such as the Speedstream 3010 and the ENI-25p. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Speedstream 3060 is currently not supported since we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * have the code to drive the on-board Alcatel DSL chipset (yet).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Thanks to Efficient for supporting this project with hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * documentation, and by answering my questions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Things not working yet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * o We don't support the Speedstream 3060 yet - this card has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * an on-board DSL modem chip by Alcatel and the driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * need some extra code added to handle it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * o Note that due to limitations of the Lanai only one VCC can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * in CBR at once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * o We don't currently parse the EEPROM at all. The code is all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * there as per the spec, but it doesn't actually work. I think
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * there may be some issues with the docs. Anyway, do NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * enable it yet - bugs in that code may actually damage your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * hardware! Because of this you should hardware an ESI before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * trying to use this in a LANE or MPOA environment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * o AAL0 is stubbed in but the actual rx/tx path isn't written yet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * vcc_tx_aal0() needs to send or queue a SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * vcc_rx_aal0() needs to handle AAL0 interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This isn't too much work - I just wanted to get other things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * done first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * o lanai_change_qos() isn't written yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * o There aren't any ioctl's yet -- I'd like to eventually support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * setting loopback and LED modes that way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * o If the segmentation engine or DMA gets shut down we should restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * card as per section 17.0i. (see lanai_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * o setsockopt(SO_CIRANGE) isn't done (although despite what the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * API says it isn't exactly commonly implemented)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Version history:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * v.0.02 -- 11-JAN-2000 -- Endian fixes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * v.0.01 -- 30-NOV-1999 -- Initial release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* -------------------- TUNABLE PARAMATERS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Maximum number of VCIs per card. Setting it lower could theoretically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * save some memory, but since we allocate our vcc list with get_free_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * it's not really likely for most architectures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NUM_VCI (1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Enable extra debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Debug _all_ register operations with card, except the memory test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Also disables the timed poll to prevent extra chattiness. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * isn't for normal use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #undef DEBUG_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * The programming guide specifies a full test of the on-board SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * at initialization time. Undefine to remove this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FULL_MEMORY_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * This is the number of (4 byte) service entries that we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * try to allocate at startup. Note that we will end up with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * one PAGE_SIZE's worth regardless of what this is set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SERVICE_ENTRIES (1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* TODO: make above a module load-time option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * We normally read the onboard EEPROM in order to discover our MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * address. Undefine to _not_ do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* TODO: make above a module load-time option (also) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Depth of TX fifo (in 128 byte units; range 2-31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Smaller numbers are better for network latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Larger numbers are better for PCI latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * I'm really sure where the best tradeoff is, but the BSD driver uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 7 and it seems to work ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TX_FIFO_DEPTH (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* TODO: make above a module load-time option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * How often (in jiffies) we will try to unstick stuck connections -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * shouldn't need to happen much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LANAI_POLL_PERIOD (10*HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* TODO: make above a module load-time option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * When allocating an AAL5 receiving buffer, try to make it at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * large enough to hold this many max_sdu sized PDUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AAL5_RX_MULTIPLIER (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* TODO: make above a module load-time option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Same for transmitting buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AAL5_TX_MULTIPLIER (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* TODO: make above a module load-time option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * When allocating an AAL0 transmiting buffer, how many cells should fit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * really critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AAL0_TX_MULTIPLIER (40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* TODO: make above a module load-time option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * How large should we make the AAL0 receiving buffer. Remember that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * is shared between all AAL0 VC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AAL0_RX_BUFFER_SIZE (PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* TODO: make above a module load-time option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Should we use Lanai's "powerdown" feature when no vcc's are bound?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* #define USE_POWERDOWN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* TODO: make above a module load-time option (also) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* -------------------- DEBUGGING AIDS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DEV_LABEL "lanai"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DPRINTK(format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define APRINTK(truth, format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (unlikely(!(truth))) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) printk(KERN_ERR DEV_LABEL ": " format, ##args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #else /* !DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DPRINTK(format, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define APRINTK(truth, format, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef DEBUG_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RWDEBUG(format, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #else /* !DEBUG_RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RWDEBUG(format, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* -------------------- DATA DEFINITIONS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LANAI_MAPPING_SIZE (0x40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LANAI_EEPROM_SIZE (128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) typedef int vci_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) typedef void __iomem *bus_addr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* DMA buffer in host memory for TX, RX, or service list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct lanai_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 *start; /* From get_free_pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 *end; /* One past last byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 *ptr; /* Pointer to current host location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dma_addr_t dmaaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct lanai_vcc_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned rx_nomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned rx_badlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned service_trash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned service_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned service_rxcrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } aal5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } aal0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct lanai_dev; /* Forward declaration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * This is the card-specific per-vcc data. Note that unlike some other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * drivers there is NOT a 1-to-1 correspondance between these and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * atm_vcc's - each one of these represents an actual 2-way vcc, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * an atm_vcc can be 1-way and share with a 1-way vcc in the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * direction. To make it weirder, there can even be 0-way vccs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * bound to us, waiting to do a change_qos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct lanai_vcc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) bus_addr_t vbase; /* Base of VCC's registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct lanai_vcc_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int nref; /* # of atm_vcc's who reference us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vci_t vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct lanai_buffer buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct atm_vcc *atmvcc; /* atm_vcc who is receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct lanai_buffer buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int endptr; /* last endptr from service entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct sk_buff_head backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) enum lanai_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct lanai_dev_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned ovfl_trash; /* # of cells dropped - buffer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned vci_trash; /* # of cells dropped - closed vci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned hec_err; /* # of cells dropped - bad HEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned pcierr_parity_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned pcierr_serr_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned pcierr_master_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned pcierr_m_target_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned pcierr_s_target_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned pcierr_master_parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned service_notx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned service_norx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned service_rxnotaal5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned dma_reenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned card_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct lanai_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bus_addr_t base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct lanai_dev_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct lanai_buffer service;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct lanai_vcc **vccs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int nbound; /* number of bound vccs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) enum lanai_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) vci_t num_vci; /* Currently just NUM_VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 eeprom[LANAI_EEPROM_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 serialno, magicno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int naal0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct lanai_buffer aal0buf; /* AAL0 RX buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 conf1, conf2; /* CONFIG[12] registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 status; /* STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spinlock_t endtxlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spinlock_t servicelock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct atm_vcc *cbrvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int board_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* TODO - look at race conditions with maintence of conf1/conf2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* TODO - transmit locking: should we use _irq not _irqsave? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* TODO - organize above in some rational fashion (see <asm/cache.h>) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * This function iterates one of these, calling a given function for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * vci with their bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void vci_bitfield_iterate(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const unsigned long *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void (*func)(struct lanai_dev *,vci_t vci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) vci_t vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for_each_set_bit(vci, lp, NUM_VCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) func(lanai, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* -------------------- BUFFER UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * usually any page allocation will do. Just to be safe in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * PAGE_SIZE is insanely tiny, though...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Allocate a buffer in host RAM for service list, RX, or TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Returns buf->start==NULL if no memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Note that the size will be rounded up 2^n bytes, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * if we can't allocate that we'll settle for something smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * until minbytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void lanai_buf_allocate(struct lanai_buffer *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) size_t bytes, size_t minbytes, struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (bytes > (128 * 1024)) /* max lanai buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bytes = 128 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (minbytes < LANAI_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) minbytes = LANAI_PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Technically we could use non-consistent mappings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * everything, but the way the lanai uses DMA memory would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * make that a terrific pain. This is much simpler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) buf->start = dma_alloc_coherent(&pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) size, &buf->dmaaddr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (buf->start != NULL) { /* Success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Lanai requires 256-byte alignment of DMA bufs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "bad dmaaddr: 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (unsigned long) buf->dmaaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) buf->ptr = buf->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) buf->end = (u32 *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (&((unsigned char *) buf->start)[size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) memset(buf->start, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) size /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } while (size >= minbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* size of buffer in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static inline size_t lanai_buf_size(const struct lanai_buffer *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ((unsigned long) buf->end) - ((unsigned long) buf->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void lanai_buf_deallocate(struct lanai_buffer *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (buf->start != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dma_free_coherent(&pci->dev, lanai_buf_size(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) buf->start, buf->dmaaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) buf->start = buf->end = buf->ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* size of buffer as "card order" (0=1k .. 7=128k) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int lanai_buf_size_cardorder(const struct lanai_buffer *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* This can only happen if PAGE_SIZE is gigantic, but just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (order > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) order = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* -------------------- PORT I/O UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Registers (and their bit-fields) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) enum lanai_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) Reset_Reg = 0x00, /* Reset; read for chip type; bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define BOARD_ID_LANAI256 (0) /* 25.6M adapter card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) Endian_Reg = 0x04, /* Endian setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) IntStatus_Reg = 0x08, /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) IntAck_Reg = 0x10, /* Interrupt acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) IntStatusSet_Reg = 0x18, /* Get status + enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) IntControlEna_Reg = 0x20, /* Interrupt control enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) IntControlDis_Reg = 0x24, /* Interrupt control disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) Status_Reg = 0x28, /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define STATUS_WAITING (0x00000002) /* Interrupt being delayed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define STATUS_SOOL (0x00000004) /* SOOL alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define STATUS_LOCD (0x00000008) /* LOCD alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define STATUS_LED (0x00000010) /* LED (HAPPI) output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define STATUS_GPIN (0x00000020) /* GPIN pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) Config1_Reg = 0x2C, /* Config word 1; bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define READMODE_PLAIN (0) /* Plain memory read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define READMODE_LINE (2) /* Memory read line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define READMODE_MULTIPLE (3) /* Memory read multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define LOOPMODE_NORMAL (0) /* Normal - no loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define LOOPMODE_TIME (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define LOOPMODE_DIAG (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define LOOPMODE_LINE (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CONFIG1_MASK_LOOPMODE (0x00000180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define LEDMODE_NOT_SOOL (0) /* !SOOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define LEDMODE_OFF (1) /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define LEDMODE_ON (2) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define LEDMODE_NOT_LOCD (3) /* !LOCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define LEDMORE_GPIN (4) /* GPIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define LEDMODE_NOT_GPIN (7) /* !GPIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CONFIG1_MASK_LEDMODE (0x00000E00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) Config2_Reg = 0x30, /* Config word 2; bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) Statistics_Reg = 0x34, /* Statistics; bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ServiceStuff_Reg = 0x38, /* Service stuff; bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ServWrite_Reg = 0x3C, /* ServWrite Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ServRead_Reg = 0x40, /* ServRead Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) TxDepth_Reg = 0x44, /* FIFO Transmit Depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) Butt_Reg = 0x48, /* Butt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) CBR_ICG_Reg = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CBR_PTR_Reg = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PingCount_Reg = 0x58, /* Ping count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DMA_Addr_Reg = 0x5C /* DMA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) enum lanai_register reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return lanai->base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static inline u32 reg_read(const struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) enum lanai_register reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) t = readl(reg_addr(lanai, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (int) reg, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static inline void reg_write(const struct lanai_dev *lanai, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enum lanai_register reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (int) reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writel(val, reg_addr(lanai, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static inline void conf1_write(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) reg_write(lanai, lanai->conf1, Config1_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static inline void conf2_write(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reg_write(lanai, lanai->conf2, Config2_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Same as conf2_write(), but defers I/O if we're powered down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #endif /* USE_POWERDOWN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) conf2_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline void reset_board(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DPRINTK("about to reset board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) reg_write(lanai, 0, Reset_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * If we don't delay a little while here then we can end up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * leaving the card in a VERY weird state and lock up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * PCI bus. This isn't documented anywhere but I've convinced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * myself after a lot of painful experimentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* -------------------- CARD SRAM UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* The SRAM is mapped into normal PCI memory space - the only catch is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * that it is only 16-bits wide but must be accessed as 32-bit. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * 16 high bits will be zero. We don't hide this, since they get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * programmed mostly like discrete registers anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SRAM_START (0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SRAM_BYTES (0x20000) /* Again, half don't really exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return lanai->base + SRAM_START + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return readl(sram_addr(lanai, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static inline void sram_write(const struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 val, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writel(val, sram_addr(lanai, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int sram_test_word(const struct lanai_dev *lanai, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 readback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sram_write(lanai, pattern, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) readback = sram_read(lanai, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (likely(readback == pattern))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) printk(KERN_ERR DEV_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) lanai->number, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) (unsigned int) pattern, (unsigned int) readback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int offset, result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) result = sram_test_word(lanai, offset, pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int sram_test_and_clear(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #ifdef FULL_MEMORY_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DPRINTK("testing SRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if ((result = sram_test_pass(lanai, 0x5555)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) DPRINTK("clearing SRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return sram_test_pass(lanai, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* -------------------- CARD-BASED VCC TABLE UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* vcc table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) enum lanai_vcc_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) vcc_rxaddr1 = 0x00, /* Location1, plus bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define RMMODE_TRASH (0) /* discard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define RMMODE_PRESERVE (1) /* input as AAL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define RMMODE_PIPE (2) /* pipe to coscheduler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define RMMODE_PIPEALL (3) /* pipe non-RM too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define RXMODE_TRASH (0) /* discard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define RXMODE_AAL0 (1) /* non-AAL5 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vcc_rxaddr2 = 0x04, /* Location2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) vcc_rxcrc1 = 0x08, /* RX CRC claculation space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) vcc_rxcrc2 = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define RXBUFSTART_CLP (0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define RXBUFSTART_CI (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) vcc_rxreadptr = 0x18, /* RX readptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) vcc_txicg = 0x1C, /* TX ICG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) vcc_txaddr1 = 0x20, /* Location1, plus bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) vcc_txaddr2 = 0x24, /* Location2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) vcc_txcrc1 = 0x28, /* TX CRC claculation space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) vcc_txcrc2 = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define TXREADPTR_GET_PTR(x) ((x)&0x01FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) vcc_txendptr = 0x34, /* TX Endptr, plus bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define TXENDPTR_CLP (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define PDUMODE_AAL0 (0*0x04000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define PDUMODE_AAL5 (2*0x04000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define PDUMODE_AAL5STREAM (3*0x04000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) vcc_txwriteptr = 0x38, /* TX Writeptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define CARDVCC_SIZE (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) vci_t vci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return sram_addr(lanai, vci * CARDVCC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) enum lanai_vcc_offset offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) val= readl(lvcc->vbase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) lvcc->vci, (int) offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static inline void cardvcc_write(const struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 val, enum lanai_vcc_offset offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) APRINTK((val & ~0xFFFF) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) (unsigned int) val, lvcc->vci, (unsigned int) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) lvcc->vci, (unsigned int) offset, (unsigned int) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writel(val, lvcc->vbase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* How many bytes will an AAL5 PDU take to transmit - remember that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * o we need to add 8 bytes for length, CPI, UU, and CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * o we need to round up to 48 bytes for cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static inline int aal5_size(int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int cells = (size + 8 + 47) / 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return cells * 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* -------------------- FREE AN ATM SKB: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (atmvcc->pop != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) atmvcc->pop(atmvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* -------------------- TURN VCCS ON AND OFF: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static void host_vcc_start_rx(const struct lanai_vcc *lvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 addr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) cardvcc_write(lvcc, 0, vcc_rxwriteptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) cardvcc_write(lvcc, 0, vcc_rxbufstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) cardvcc_write(lvcc, 0, vcc_rxreadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) addr1 = ((dmaaddr >> 8) & 0xFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RXADDR1_SET_MODE(RXMODE_AAL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) RXADDR1_OAM_PRESERVE | /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RXADDR1_SET_MODE(RXMODE_AAL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* This one must be last! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cardvcc_write(lvcc, addr1, vcc_rxaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static void host_vcc_start_tx(const struct lanai_vcc *lvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) cardvcc_write(lvcc, 0, vcc_txicg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cardvcc_write(lvcc, 0, vcc_txreadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cardvcc_write(lvcc, 0, vcc_txendptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) cardvcc_write(lvcc, 0, vcc_txwriteptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) cardvcc_write(lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cardvcc_write(lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ((dmaaddr >> 8) & 0xFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) vcc_txaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Shutdown receiving on card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (lvcc->vbase == NULL) /* We were never bound to a VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* 15.1.1 - set to trashing, wait one cell time (15us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cardvcc_write(lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RXADDR1_SET_RMMODE(RMMODE_TRASH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) udelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* 15.1.2 - clear rest of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) cardvcc_write(lvcc, 0, vcc_rxaddr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cardvcc_write(lvcc, 0, vcc_rxcrc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) cardvcc_write(lvcc, 0, vcc_rxcrc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cardvcc_write(lvcc, 0, vcc_rxwriteptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) cardvcc_write(lvcc, 0, vcc_rxbufstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) cardvcc_write(lvcc, 0, vcc_rxreadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Shutdown transmitting on card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Unfortunately the lanai needs us to wait until all the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * drains out of the buffer before we can dealloc it, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * can take awhile -- up to 370ms for a full 128KB buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * assuming everone else is quiet. In theory the time is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * boundless if there's a CBR VCC holding things up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct lanai_vcc *lvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned long flags, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int read, write, lastread = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) APRINTK(!in_interrupt(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "lanai_shutdown_tx_vci called w/o process context!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (lvcc->vbase == NULL) /* We were never bound to a VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* 15.2.1 - wait for queue to drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) lanai_free_skb(lvcc->tx.atmvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) read_lock_irqsave(&vcc_sklist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) __clear_bit(lvcc->vci, lanai->backlog_vccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) read_unlock_irqrestore(&vcc_sklist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * We need to wait for the VCC to drain but don't wait forever. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * give each 1K of buffer size 1/128th of a second to clear out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * TODO: maybe disable CBR if we're about to timeout?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (read == write && /* Is TX buffer empty? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) (cardvcc_read(lvcc, vcc_txcbr_next) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TXCBR_NEXT_BOZO) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (read != lastread) { /* Has there been any progress? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) lastread = read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) timeout += HZ / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (unlikely(time_after(jiffies, timeout))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "backlog closing vci %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) lvcc->tx.atmvcc->dev->number, lvcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DPRINTK("read, write = %d, %d\n", read, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* 15.2.2 - clear out all tx registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cardvcc_write(lvcc, 0, vcc_txreadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) cardvcc_write(lvcc, 0, vcc_txwriteptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) cardvcc_write(lvcc, 0, vcc_txendptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cardvcc_write(lvcc, 0, vcc_txcrc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cardvcc_write(lvcc, 0, vcc_txcrc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) cardvcc_write(lvcc, 0, vcc_txaddr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) cardvcc_write(lvcc, 0, vcc_txaddr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* -------------------- MANAGING AAL0 RX BUFFER: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static inline void aal0_buffer_free(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* -------------------- EEPROM UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Offsets of data in the EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define EEPROM_COPYRIGHT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define EEPROM_COPYRIGHT_LEN (44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define EEPROM_CHECKSUM (62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define EEPROM_CHECKSUM_REV (63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define EEPROM_MAC (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define EEPROM_MAC_REV (70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define EEPROM_SERIAL (112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define EEPROM_SERIAL_REV (116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define EEPROM_MAGIC (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define EEPROM_MAGIC_REV (124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define EEPROM_MAGIC_VALUE (0x5AB478D2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #ifndef READ_EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Stub functions to use if EEPROM reading is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int eeprom_read(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int eeprom_validate(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) lanai->serialno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) lanai->magicno = EEPROM_MAGIC_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #else /* READ_EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int eeprom_read(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int i, address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define pre_read() do { data_h(); clock_h(); udelay(5); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) data_h(); udelay(5); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* start with both clock and data high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) data_h(); clock_h(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) for (address = 0; address < LANAI_EEPROM_SIZE; address++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) data = (address << 1) | 1; /* Command=read + address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* send start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) data_l(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) clock_l(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) for (i = 128; i != 0; i >>= 1) { /* write command out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ((data & i) ? CONFIG1_PROMDATA : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (lanai->conf1 != tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) set_config1(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) udelay(5); /* Let new data settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) clock_h(); udelay(5); clock_l(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* look for ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) data_h(); clock_h(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (read_pin() != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto error; /* No ack seen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) clock_l(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* read back result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) for (data = 0, i = 7; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) data_h(); clock_h(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) data = (data << 1) | !!read_pin();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) clock_l(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* look again for ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) data_h(); clock_h(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (read_pin() == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) goto error; /* Spurious ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) clock_l(); udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) send_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) lanai->eeprom[address] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) DPRINTK("EEPROM 0x%04X %02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) (unsigned int) address, (unsigned int) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) clock_l(); udelay(5); /* finish read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) send_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) lanai->number, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #undef set_config1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #undef clock_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #undef clock_l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #undef data_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #undef data_l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #undef pre_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #undef read_pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #undef send_stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* read a big-endian 4-byte value out of eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Checksum/validate EEPROM contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int eeprom_validate(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int i, s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) const u8 *e = lanai->eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* First, see if we can get an ASCIIZ string out of the copyright */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) for (i = EEPROM_COPYRIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (e[i] < 0x20 || e[i] > 0x7E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if ( i != EEPROM_COPYRIGHT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DPRINTK("eeprom: copyright = \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) (char *) &e[EEPROM_COPYRIGHT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) DPRINTK("eeprom: copyright not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Validate checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) for (i = s = 0; i < EEPROM_CHECKSUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) s += e[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) s &= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (s != e[EEPROM_CHECKSUM]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) s ^= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (s != e[EEPROM_CHECKSUM_REV]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Verify MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) printk(KERN_ERR DEV_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) "(itf %d) : EEPROM MAC addresses don't match "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "(0x%02X, inverse 0x%02X)\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) (unsigned int) e[EEPROM_MAC + i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) (unsigned int) e[EEPROM_MAC_REV + i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) DPRINTK("eeprom: MAC address = %pM\n", &e[EEPROM_MAC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Verify serial number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) (unsigned int) lanai->serialno, (unsigned int) v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Verify magic number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) lanai->magicno, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (lanai->magicno != EEPROM_MAGIC_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) "magic not what expected (got 0x%08X, not 0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) lanai->number, (unsigned int) lanai->magicno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) (unsigned int) EEPROM_MAGIC_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #endif /* READ_EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return &lanai->eeprom[EEPROM_MAC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* -------------------- INTERRUPT HANDLING UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Interrupt types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define INT_STATS (0x00000002) /* Statistics counter overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define INT_SOOL (0x00000004) /* SOOL changed state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define INT_LOCD (0x00000008) /* LOCD changed state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define INT_LED (0x00000010) /* LED (HAPPI) changed state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define INT_GPIN (0x00000020) /* GPIN changed state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define INT_PING (0x00000040) /* PING_COUNT fulfilled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define INT_WAKE (0x00000080) /* Lanai wants bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define INT_LOCK (0x00000200) /* Service list overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define INT_MISMATCH (0x00000400) /* TX magic list mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define INT_AAL0 (0x00001000) /* Non-AAL5 data available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define INT_SERVICE (0x00002000) /* Service list entries available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define INT_TIMEOUTBM (0x00010000) /* No response to bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define INT_PCIPARITY (0x00020000) /* Parity error on PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* Sets of the above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define INT_ALL (0x0003FFFE) /* All interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define INT_STATUS (0x0000003C) /* Some status pin changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define INT_DMASHUT (0x00038000) /* DMA engine got shut down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static inline u32 intr_pending(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return reg_read(lanai, IntStatusMasked_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) reg_write(lanai, i, IntControlEna_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) reg_write(lanai, i, IntControlDis_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* -------------------- CARD/PCI STATUS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static void status_message(int itf, const char *name, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const char *onoff[2] = { "off to on", "on to off" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) itf, name, onoff[!status]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static void lanai_check_status(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u32 new = reg_read(lanai, Status_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) u32 changes = new ^ lanai->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) lanai->status = new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define e(flag, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (changes & flag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) status_message(lanai->number, name, new & flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) e(STATUS_SOOL, "SOOL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) e(STATUS_LOCD, "LOCD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) e(STATUS_LED, "LED");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) e(STATUS_GPIN, "GPIN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #undef e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void pcistatus_got(int itf, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u16 s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (result != PCIBIOS_SUCCESSFUL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "%d\n", lanai->number, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (s == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (result != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "%d\n", lanai->number, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (clearonly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define e(flag, name, stat) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (s & flag) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pcistatus_got(lanai->number, name); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ++lanai->stats.pcierr_##stat; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) e(PCI_STATUS_PARITY, "master parity", master_parity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #undef e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* -------------------- VCC TX BUFFER UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* space left in tx buffer in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) r = endptr * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) r -= ((unsigned long) lvcc->tx.buf.ptr) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ((unsigned long) lvcc->tx.buf.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) r -= 16; /* Leave "bubble" - if start==end it looks empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) r += lanai_buf_size(&lvcc->tx.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* test if VCC is currently backlogged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return !skb_queue_empty(&lvcc->tx.backlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* Bit fields in the segmentation buffer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define DESCRIPTOR_MAGIC (0xD0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define DESCRIPTOR_AAL5 (0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define DESCRIPTOR_AAL5_STREAM (0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define DESCRIPTOR_CLP (0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Add 32-bit descriptor with its padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) u32 flags, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) pos = ((unsigned char *) lvcc->tx.buf.ptr) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) (unsigned char *) lvcc->tx.buf.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) APRINTK((pos & ~0x0001FFF0) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) APRINTK((pos & ~0x0001FFF0) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) lvcc->tx.buf.ptr[-1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) DESCRIPTOR_CLP : 0) | flags | pos >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) lvcc->tx.buf.ptr = lvcc->tx.buf.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Add 32-bit AAL5 trailer and leave room for its CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int len, int cpi, int uu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) lvcc->tx.buf.ptr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) lvcc->tx.buf.ptr = lvcc->tx.buf.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) const unsigned char *src, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) unsigned char *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) m = e - (unsigned char *) lvcc->tx.buf.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (m < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) memcpy(lvcc->tx.buf.ptr, src, n - m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (m != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) memcpy(lvcc->tx.buf.start, src + n - m, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) e = ((unsigned char *) lvcc->tx.buf.start) + m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) lvcc->tx.buf.ptr = (u32 *) e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) unsigned char *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) int m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (n == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) m = e - (unsigned char *) lvcc->tx.buf.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (m < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) memset(lvcc->tx.buf.ptr, 0, n - m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (m != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) memset(lvcc->tx.buf.start, 0, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) e = ((unsigned char *) lvcc->tx.buf.start) + m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) lvcc->tx.buf.ptr = (u32 *) e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* Update "butt" register to specify new WritePtr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static inline void lanai_endtx(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) const struct lanai_vcc *lvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) (unsigned char *) lvcc->tx.buf.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) APRINTK((ptr & ~0x0001FFF0) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) lvcc->tx.buf.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * Since the "butt register" is a shared resounce on the card we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * serialize all accesses to it through this spinlock. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * mostly just paranoia since the register is rarely "busy" anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * but is needed for correctness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) spin_lock(&lanai->endtxlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * We need to check if the "butt busy" bit is set before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * updating the butt register. In theory this should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * never happen because the ATM card is plenty fast at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * updating the register. Still, we should make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (unlikely(i > 50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) printk(KERN_ERR DEV_LABEL "(itf %d): butt register "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) "always busy!\n", lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * Before we tall the card to start work we need to be sure 100% of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * the info in the service buffer has been written before we tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * the card about it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) spin_unlock(&lanai->endtxlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * space available. "pdusize" is the number of bytes the PDU will take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static void lanai_send_one_aal5(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) APRINTK(pdusize == aal5_size(skb->len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) "lanai_send_one_aal5: wrong size packet (%d != %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) pdusize, aal5_size(skb->len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pad = pdusize - skb->len - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) APRINTK(pad >= 0, "pad is negative (%d)\n", pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) APRINTK(pad < 48, "pad is too big (%d)\n", pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) vcc_tx_memcpy(lvcc, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) vcc_tx_memzero(lvcc, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) lanai_endtx(lanai, lvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) lanai_free_skb(lvcc->tx.atmvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) atomic_inc(&lvcc->tx.atmvcc->stats->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Try to fill the buffer - don't call unless there is backlog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct lanai_vcc *lvcc, int endptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) int space = vcc_tx_space(lvcc, endptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) APRINTK(vcc_is_backlogged(lvcc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "vcc_tx_unqueue() called with empty backlog (vci=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) lvcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) while (space >= 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) skb = skb_dequeue(&lvcc->tx.backlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto no_backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) n = aal5_size(skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (n + 16 > space) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* No room for this packet - put it back on queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) skb_queue_head(&lvcc->tx.backlog, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) lanai_send_one_aal5(lanai, lvcc, skb, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) space -= n + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!vcc_is_backlogged(lvcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) no_backlog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) __clear_bit(lvcc->vci, lanai->backlog_vccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Given an skb that we want to transmit either send it now or queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) int space, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (vcc_is_backlogged(lvcc)) /* Already backlogged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) goto queue_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) space = vcc_tx_space(lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) n = aal5_size(skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (space < n + 16) { /* No space for this PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) __set_bit(lvcc->vci, lanai->backlog_vccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) queue_it:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) skb_queue_tail(&lvcc->tx.backlog, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) lanai_send_one_aal5(lanai, lvcc, skb, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct lanai_vcc *lvcc, int endptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) printk(KERN_INFO DEV_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ": vcc_tx_unqueue_aal0: not implemented\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* Remember to increment lvcc->tx.atmvcc->stats->tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) lanai_free_skb(lvcc->tx.atmvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* -------------------- VCC RX BUFFER UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* unlike the _tx_ cousins, this doesn't update ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static inline void vcc_rx_memcpy(unsigned char *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) const struct lanai_vcc *lvcc, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ((const unsigned char *) (lvcc->rx.buf.end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (m < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) memcpy(dest, lvcc->rx.buf.ptr, n - m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) memcpy(dest + n - m, lvcc->rx.buf.start, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* Make sure that these copies don't get reordered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* Receive AAL5 data on a VCC with a particular endptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) const u32 *x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) u32 *end = &lvcc->rx.buf.start[endptr * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (n < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) n += lanai_buf_size(&lvcc->rx.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) "vcc_rx_aal5: n out of range (%d/%zu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) n, lanai_buf_size(&lvcc->rx.buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* Recover the second-to-last word to get true pdu length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if ((x = &end[-2]) < lvcc->rx.buf.start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) x = &lvcc->rx.buf.end[-2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * Before we actually read from the buffer, make sure the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * changes have arrived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) size = be32_to_cpup(x) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (unlikely(n != aal5_size(size))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* Make sure size matches padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) "on vci=%d - size=%d n=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) lvcc->stats.x.aal5.rx_badlen++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (unlikely(skb == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) lvcc->stats.rx_nomem++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) skb_put(skb, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) vcc_rx_memcpy(skb->data, lvcc, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ATM_SKB(skb)->vcc = lvcc->rx.atmvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) __net_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) atomic_inc(&lvcc->rx.atmvcc->stats->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) lvcc->rx.buf.ptr = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) cardvcc_write(lvcc, endptr, vcc_rxreadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static void vcc_rx_aal0(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* Remember to increment lvcc->rx.atmvcc->stats->rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* -------------------- MANAGING HOST-BASED VCC TABLE: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* Decide whether to use vmalloc or get_zeroed_page for VCC table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define VCCTABLE_GETFREEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static int vcc_table_allocate(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #ifdef VCCTABLE_GETFREEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) "vcc table > PAGE_SIZE!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return (lanai->vccs == NULL) ? -ENOMEM : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) lanai->vccs = vzalloc(bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (unlikely(lanai->vccs == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #ifdef VCCTABLE_GETFREEPAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) free_page((unsigned long) lanai->vccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) vfree(lanai->vccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Allocate a fresh lanai_vcc, with the appropriate things cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static inline struct lanai_vcc *new_lanai_vcc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct lanai_vcc *lvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (likely(lvcc != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) skb_queue_head_init(&lvcc->tx.backlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) lvcc->vci = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return lvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static int lanai_get_sized_buffer(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct lanai_buffer *buf, int max_sdu, int multiplier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (unlikely(max_sdu < 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) max_sdu = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) max_sdu = aal5_size(max_sdu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) size = (max_sdu + 16) * multiplier + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (unlikely(buf->start == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (unlikely(lanai_buf_size(buf) < size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) "for %s buffer, got only %zu\n", lanai->number, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) name, lanai_buf_size(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) DPRINTK("Allocated %zu byte %s buffer\n", lanai_buf_size(buf), name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Setup a RX buffer for a currently unbound AAL5 vci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct lanai_vcc *lvcc, const struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* Setup a TX buffer for a currently unbound AAL5 vci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) const struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) int max_sdu, multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (qos->aal == ATM_AAL0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) lvcc->tx.unqueue = vcc_tx_unqueue_aal0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) max_sdu = ATM_CELL_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) multiplier = AAL0_TX_MULTIPLIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) lvcc->tx.unqueue = vcc_tx_unqueue_aal5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) max_sdu = qos->txtp.max_sdu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) multiplier = AAL5_TX_MULTIPLIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) multiplier, "TX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static inline void host_vcc_bind(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct lanai_vcc *lvcc, vci_t vci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (lvcc->vbase != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return; /* We already were bound in the other direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) DPRINTK("Binding vci %d\n", vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (lanai->nbound++ == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) DPRINTK("Coming out of powerdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) lanai->conf1 &= ~CONFIG1_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) conf2_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) lvcc->vbase = cardvcc_addr(lanai, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) lanai->vccs[lvcc->vci = vci] = lvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static inline void host_vcc_unbind(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct lanai_vcc *lvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (lvcc->vbase == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return; /* This vcc was never bound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) DPRINTK("Unbinding vci %d\n", lvcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) lvcc->vbase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) lanai->vccs[lvcc->vci] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (--lanai->nbound == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) DPRINTK("Going into powerdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) lanai->conf1 |= CONFIG1_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* -------------------- RESET CARD: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static void lanai_reset(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* resetting - not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) "implemented\n", lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* The following is just a hack until we write the real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * resetter - at least ack whatever interrupt sent us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) reg_write(lanai, INT_ALL, IntAck_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) lanai->stats.card_reset++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* -------------------- SERVICE LIST UTILITIES: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * Allocate service buffer and tell card about it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static int service_buffer_allocate(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (unlikely(lanai->service.start == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) DPRINTK("allocated service buffer at %p, size %zu(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) lanai->service.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) lanai_buf_size(&lanai->service),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) lanai_buf_size_cardorder(&lanai->service));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Clear ServWrite register to be safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) reg_write(lanai, 0, ServWrite_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* ServiceStuff register contains size and address of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) reg_write(lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) SSTUFF_SET_ADDR(lanai->service.dmaaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ServiceStuff_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static inline void service_buffer_deallocate(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) lanai_buf_deallocate(&lanai->service, lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* Bitfields in service list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define SERVICE_TX (0x80000000) /* Was from transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define SERVICE_CI (0x10000000) /* RXed PDU had CI set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define SERVICE_STREAM (0x04000000) /* RX Stream mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define SERVICE_GET_END(x) ((x)&0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* Handle one thing from the service list - returns true if it marked a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * VCC ready for xmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static int handle_service(struct lanai_dev *lanai, u32 s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) vci_t vci = SERVICE_GET_VCI(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct lanai_vcc *lvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) read_lock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) lvcc = lanai->vccs[vci];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (unlikely(lvcc == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) DPRINTK("(itf %d) got service entry 0x%X for nonexistent "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) "vcc %d\n", lanai->number, (unsigned int) s, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (s & SERVICE_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) lanai->stats.service_notx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) lanai->stats.service_norx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (s & SERVICE_TX) { /* segmentation interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (unlikely(lvcc->tx.atmvcc == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) DPRINTK("(itf %d) got service entry 0x%X for non-TX "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) "vcc %d\n", lanai->number, (unsigned int) s, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) lanai->stats.service_notx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) __set_bit(vci, lanai->transmit_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) lvcc->tx.endptr = SERVICE_GET_END(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (unlikely(lvcc->rx.atmvcc == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) DPRINTK("(itf %d) got service entry 0x%X for non-RX "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) "vcc %d\n", lanai->number, (unsigned int) s, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) lanai->stats.service_norx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) "vcc %d\n", lanai->number, (unsigned int) s, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) lanai->stats.service_rxnotaal5++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) vcc_rx_aal5(lvcc, SERVICE_GET_END(s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (s & SERVICE_TRASH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) int bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) DPRINTK("got trashed rx pdu on vci %d\n", vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) lvcc->stats.x.aal5.service_trash++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) bytes = (SERVICE_GET_END(s) * 16) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) (((unsigned long) lvcc->rx.buf.ptr) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ((unsigned long) lvcc->rx.buf.start)) + 47;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (bytes < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) bytes += lanai_buf_size(&lvcc->rx.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) lanai->stats.ovfl_trash += (bytes / 48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (s & SERVICE_STREAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) lvcc->stats.x.aal5.service_stream++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) "PDU on VCI %d!\n", lanai->number, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) lanai_reset(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) DPRINTK("got rx crc error on vci %d\n", vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) lvcc->stats.x.aal5.service_rxcrc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* Try transmitting on all VCIs that we marked ready to serve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct lanai_vcc *lvcc = lanai->vccs[vci];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (vcc_is_backlogged(lvcc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* Run service queue -- called from interrupt context or with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * interrupts otherwise disabled and with the lanai->servicelock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static void run_service(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) int ntx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) u32 wreg = reg_read(lanai, ServWrite_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) const u32 *end = lanai->service.start + wreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) while (lanai->service.ptr != end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ntx += handle_service(lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) le32_to_cpup(lanai->service.ptr++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (lanai->service.ptr >= lanai->service.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) lanai->service.ptr = lanai->service.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) reg_write(lanai, wreg, ServRead_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (ntx != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) read_lock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) vci_bitfield_iterate(lanai, lanai->transmit_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) iter_transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) bitmap_zero(lanai->transmit_ready, NUM_VCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* -------------------- GATHER STATISTICS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static void get_statistics(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) u32 statreg = reg_read(lanai, Statistics_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* -------------------- POLLING TIMER: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #ifndef DEBUG_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* Try to undequeue 1 backlogged vcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct lanai_vcc *lvcc = lanai->vccs[vci];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) int endptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (lvcc == NULL || lvcc->tx.atmvcc == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) !vcc_is_backlogged(lvcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) __clear_bit(vci, lanai->backlog_vccs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) lvcc->tx.unqueue(lanai, lvcc, endptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #endif /* !DEBUG_RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static void lanai_timed_poll(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct lanai_dev *lanai = from_timer(lanai, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #ifndef DEBUG_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (lanai->conf1 & CONFIG1_POWERDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #endif /* USE_POWERDOWN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* If we can grab the spinlock, check if any services need to be run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (spin_trylock(&lanai->servicelock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) run_service(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) spin_unlock(&lanai->servicelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /* ...and see if any backlogged VCs can make progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /* unfortunately linux has no read_trylock() currently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) read_lock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) get_statistics(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) #endif /* !DEBUG_RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) timer_setup(&lanai->timer, lanai_timed_poll, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) add_timer(&lanai->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) del_timer_sync(&lanai->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /* -------------------- INTERRUPT SERVICE: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) u32 ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (reason & INT_SERVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ack = INT_SERVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) spin_lock(&lanai->servicelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) run_service(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) spin_unlock(&lanai->servicelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (reason & (INT_AAL0_STR | INT_AAL0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ack |= reason & (INT_AAL0_STR | INT_AAL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) vcc_rx_aal0(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* The rest of the interrupts are pretty rare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (ack == reason)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (reason & INT_STATS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) reason &= ~INT_STATS; /* No need to ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) get_statistics(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (reason & INT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ack |= reason & INT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) lanai_check_status(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (unlikely(reason & INT_DMASHUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) "shutdown, reason=0x%08X, address=0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) lanai->number, (unsigned int) (reason & INT_DMASHUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) (unsigned int) reg_read(lanai, DMA_Addr_Reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (reason & INT_TABORTBM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) lanai_reset(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ack |= (reason & INT_DMASHUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) lanai->stats.dma_reenable++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) pcistatus_check(lanai, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (unlikely(reason & INT_TABORTSENT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ack |= (reason & INT_TABORTSENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) pcistatus_check(lanai, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (unlikely(reason & INT_SEGSHUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) "segmentation shutdown, reason=0x%08X\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) (unsigned int) (reason & INT_SEGSHUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) lanai_reset(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (unlikely(reason & (INT_PING | INT_WAKE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) "unexpected interrupt 0x%08X, resetting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) (unsigned int) (reason & (INT_PING | INT_WAKE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) lanai_reset(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (unlikely(ack != reason)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) DPRINTK("unacked ints: 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) (unsigned int) (reason & ~ack));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ack = reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (ack != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) reg_write(lanai, ack, IntAck_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) static irqreturn_t lanai_int(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) struct lanai_dev *lanai = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) u32 reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) * If we're powered down we shouldn't be generating any interrupts -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * so assume that this is a shared interrupt line and it's for someone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) reason = intr_pending(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (reason == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return IRQ_NONE; /* Must be for someone else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (unlikely(reason == 0xFFFFFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) break; /* Maybe we've been unplugged? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) lanai_int_1(lanai, reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) reason = intr_pending(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) } while (reason != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* TODO - it would be nice if we could use the "delayed interrupt" system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * to some advantage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* -------------------- CHECK BOARD ID/REV: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * The board id and revision are stored both in the reset register and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * in the PCI configuration space - the documentation says to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * each of them. If revp!=NULL we store the revision there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static int check_board_id_and_rev(const char *name, u32 val, int *revp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) DPRINTK("%s says board_id=%d, board_rev=%d\n", name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) (int) RESET_GET_BOARD_ID(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) (int) RESET_GET_BOARD_REV(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (revp != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) *revp = RESET_GET_BOARD_REV(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* -------------------- PCI INITIALIZATION/SHUTDOWN: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static int lanai_pci_start(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct pci_dev *pci = lanai->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (pci_enable_device(pci) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) printk(KERN_ERR DEV_LABEL "(itf %d): can't enable "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) "PCI device", lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) printk(KERN_WARNING DEV_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) "(itf %d): No suitable DMA available.\n", lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) result = check_board_id_and_rev("PCI", pci->subsystem_device, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* Set latency timer to zero as per lanai docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) if (result != PCIBIOS_SUCCESSFUL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) printk(KERN_ERR DEV_LABEL "(itf %d): can't write "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) pcistatus_check(lanai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) pcistatus_check(lanai, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* -------------------- VPI/VCI ALLOCATION: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * get a CBRZERO interrupt), and we can use it only if no one is receiving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * AAL0 traffic (since they will use the same queue) - according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * docs we shouldn't even use it for AAL0 traffic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static inline int vci0_is_ok(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) const struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (qos->rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (lanai->naal0 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) lanai->conf2 |= CONFIG2_VCI0_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) conf2_write_if_powerup(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* return true if vci is currently unused, or if requested qos is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) const struct atm_vcc *atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) const struct atm_qos *qos = &atmvcc->qos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) const struct lanai_vcc *lvcc = lanai->vccs[vci];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (vci == 0 && !vci0_is_ok(lanai, qos))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (unlikely(lvcc != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (qos->rxtp.traffic_class != ATM_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if (qos->txtp.traffic_class != ATM_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (qos->txtp.traffic_class == ATM_CBR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) qos->rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) const struct lanai_vcc *vci0 = lanai->vccs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (vci0 != NULL && vci0->rx.atmvcc != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) conf2_write_if_powerup(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static int lanai_normalize_ci(struct lanai_dev *lanai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) switch (*vpip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) case ATM_VPI_ANY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) *vpip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) return -EADDRINUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) switch (*vcip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) case ATM_VCI_ANY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) (*vcip)++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (vci_is_ok(lanai, *vcip, atmvcc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return -EADDRINUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (*vcip >= lanai->num_vci || *vcip < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) !vci_is_ok(lanai, *vcip, atmvcc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) return -EADDRINUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* -------------------- MANAGE CBR: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * CBR ICG is stored as a fixed-point number with 4 fractional bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * Note that storing a number greater than 2046.0 will result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * incorrect shaping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define CBRICG_FRAC_BITS (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define CBRICG_MAX (2046 << CBRICG_FRAC_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) * where MAXPCR is (according to the docs) 25600000/(54*8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) * which is equal to (3125<<9)/27.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) * Solving for ICG, we get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) * ICG = MAXPCR/PCR - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) * ICG = (3125<<9)/(27*PCR) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) * ICG = ((3125<<9) - (27*PCR)) / (27*PCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * The end result is supposed to be a fixed-point number with FRAC_BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * bits of a fractional part, so we keep everything in the numerator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * shifted by that much as we compute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static int pcr_to_cbricg(const struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) int x, icg, pcr = atm_pcr_goal(&qos->txtp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (pcr == 0) /* Use maximum bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (pcr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) rounddown = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) pcr = -pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) x = pcr * 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (rounddown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) icg += x - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) icg /= x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (icg > CBRICG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) icg = CBRICG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) pcr, rounddown ? 'Y' : 'N', icg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) return icg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) static inline void lanai_cbr_setup(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) lanai->conf2 |= CONFIG2_CBR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) conf2_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) conf2_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /* -------------------- OPERATIONS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) /* setup a newly detected device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static int lanai_dev_open(struct atm_dev *atmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) unsigned long raw_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) DPRINTK("In lanai_dev_open()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) /* Basic device fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) lanai->number = atmdev->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) lanai->num_vci = NUM_VCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) bitmap_zero(lanai->backlog_vccs, NUM_VCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) bitmap_zero(lanai->transmit_ready, NUM_VCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) lanai->naal0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) lanai->nbound = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) lanai->cbrvcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) memset(&lanai->stats, 0, sizeof lanai->stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) spin_lock_init(&lanai->endtxlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) spin_lock_init(&lanai->servicelock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) atmdev->ci_range.vpi_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) atmdev->ci_range.vci_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) atmdev->ci_range.vci_bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) atmdev->link_rate = ATM_25_PCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) /* 3.2: PCI initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if ((result = lanai_pci_start(lanai)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) raw_base = lanai->pci->resource[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (lanai->base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) result = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) goto error_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /* 3.3: Reset lanai and PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) reset_board(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) lanai->conf1 = reg_read(lanai, Config1_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) CONFIG1_MASK_LEDMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) * 3.4: Turn on endian mode for big-endian hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) * We don't actually want to do this - the actual bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) * in the endian register are not documented anywhere.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) * Instead we do the bit-flipping ourselves on big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) * 3.5: get the board ID/rev by reading the reset register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) result = check_board_id_and_rev("register",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) reg_read(lanai, Reset_Reg), &lanai->board_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) goto error_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) /* 3.6: read EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if ((result = eeprom_read(lanai)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) goto error_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if ((result = eeprom_validate(lanai)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) goto error_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /* 3.7: re-reset PHY, do loopback tests, setup PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* TODO - loopback tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* 3.8/3.9: test and initialize card SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if ((result = sram_test_and_clear(lanai)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) goto error_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* 3.10: initialize lanai registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) lanai->conf1 |= CONFIG1_DMA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if ((result = service_buffer_allocate(lanai)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) goto error_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if ((result = vcc_table_allocate(lanai)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) goto error_service;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) conf2_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) DEV_LABEL, lanai)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) goto error_vcctable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) mb(); /* Make sure that all that made it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /* 3.11: initialize loop mode (i.e. turn looping off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) CONFIG1_GPOUT2 | CONFIG1_GPOUT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) lanai->status = reg_read(lanai, Status_Reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /* We're now done initializing this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) lanai->conf1 |= CONFIG1_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) lanai_timed_poll_start(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=%p, irq=%u "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) "(%pMF)\n", lanai->number, (int) lanai->pci->revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) lanai->base, lanai->pci->irq, atmdev->esi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) "board_rev=%d\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) (unsigned int) lanai->serialno, lanai->board_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) error_vcctable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) vcc_table_deallocate(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) error_service:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) service_buffer_deallocate(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) error_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) reset_board(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) iounmap(lanai->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) lanai->base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) error_pci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) pci_disable_device(lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /* called when device is being shutdown, and all vcc's are gone - higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) * levels will deallocate the atm device for us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static void lanai_dev_close(struct atm_dev *atmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (lanai->base==NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) lanai->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) lanai_timed_poll_stop(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) intr_disable(lanai, INT_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) free_irq(lanai->pci->irq, lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) reset_board(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) #ifdef USE_POWERDOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) lanai->conf1 |= CONFIG1_POWERDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) conf1_write(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) pci_disable_device(lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) vcc_table_deallocate(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) service_buffer_deallocate(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) iounmap(lanai->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) kfree(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /* close a vcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static void lanai_close(struct atm_vcc *atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (lvcc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) clear_bit(ATM_VF_READY, &atmvcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) clear_bit(ATM_VF_PARTIAL, &atmvcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (lvcc->rx.atmvcc == atmvcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) lanai_shutdown_rx_vci(lvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) if (atmvcc->qos.aal == ATM_AAL0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (--lanai->naal0 <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) aal0_buffer_free(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) lvcc->rx.atmvcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (lvcc->tx.atmvcc == atmvcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (atmvcc == lanai->cbrvcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) if (lvcc->vbase != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) lanai_cbr_shutdown(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) lanai->cbrvcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) lanai_shutdown_tx_vci(lanai, lvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) lvcc->tx.atmvcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (--lvcc->nref == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) host_vcc_unbind(lanai, lvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) kfree(lvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) atmvcc->dev_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) clear_bit(ATM_VF_ADDR, &atmvcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /* open a vcc on the card to vpi/vci */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static int lanai_open(struct atm_vcc *atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) struct lanai_dev *lanai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) struct lanai_vcc *lvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) int vci = atmvcc->vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) short vpi = atmvcc->vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) /* we don't support partial open - it's not really useful anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) if (unlikely(result != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) set_bit(ATM_VF_ADDR, &atmvcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) (int) vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) lvcc = lanai->vccs[vci];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) if (lvcc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) lvcc = new_lanai_vcc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) if (unlikely(lvcc == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) atmvcc->dev_data = lvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) lvcc->nref++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (atmvcc->qos.aal == ATM_AAL0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) if (lanai->naal0 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) result = aal0_buffer_allocate(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) result = lanai_setup_rx_vci_aal5(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) lanai, lvcc, &atmvcc->qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (unlikely(result != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) lvcc->rx.atmvcc = atmvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) lvcc->stats.rx_nomem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) lvcc->stats.x.aal5.rx_badlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) lvcc->stats.x.aal5.service_trash = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) lvcc->stats.x.aal5.service_stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) lvcc->stats.x.aal5.service_rxcrc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (atmvcc->qos.aal == ATM_AAL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) lanai->naal0++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (atmvcc->qos.txtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) if (unlikely(result != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) lvcc->tx.atmvcc = atmvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (atmvcc->qos.txtp.traffic_class == ATM_CBR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) APRINTK(lanai->cbrvcc == NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) "cbrvcc!=NULL, vci=%d\n", vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) lanai->cbrvcc = atmvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) host_vcc_bind(lanai, lvcc, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) * Make sure everything made it to RAM before we tell the card about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) * the VCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (atmvcc == lvcc->rx.atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) host_vcc_start_rx(lvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) if (atmvcc == lvcc->tx.atmvcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) host_vcc_start_tx(lvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (lanai->cbrvcc == atmvcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) lanai_cbr_setup(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) set_bit(ATM_VF_READY, &atmvcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) lanai_close(atmvcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (unlikely(lvcc == NULL || lvcc->vbase == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) lvcc->tx.atmvcc != atmvcc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) goto einval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (unlikely(skb == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) goto einval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) if (unlikely(lanai == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) goto einval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ATM_SKB(skb)->vcc = atmvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) switch (atmvcc->qos.aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) read_lock_irqsave(&vcc_sklist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) vcc_tx_aal5(lanai, lvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) read_unlock_irqrestore(&vcc_sklist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (unlikely(skb->len != ATM_CELL_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) goto einval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) /* NOTE - this next line is technically invalid - we haven't unshared skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) cpu_to_be32s((u32 *) skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) read_lock_irqsave(&vcc_sklist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) vcc_tx_aal0(lanai, lvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) read_unlock_irqrestore(&vcc_sklist_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) atmvcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) einval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) lanai_free_skb(atmvcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) static int lanai_change_qos(struct atm_vcc *atmvcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /*const*/ struct atm_qos *qos, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) return -EBUSY; /* TODO: need to write this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #ifndef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #define lanai_proc_read NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) loff_t left = *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) struct lanai_vcc *lvcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) "serial=%u, magic=0x%08X, num_vci=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) atmdev->number, lanai->type==lanai2 ? "2" : "HB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) (unsigned int) lanai->serialno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) (unsigned int) lanai->magicno, lanai->num_vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return sprintf(page, "revision: board=%d, pci_if=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) lanai->board_rev, (int) lanai->pci->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) return sprintf(page, "EEPROM ESI: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) &lanai->eeprom[EEPROM_MAC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) (lanai->status & STATUS_LOCD) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) (lanai->status & STATUS_LED) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) (lanai->status & STATUS_GPIN) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) return sprintf(page, "global buffer sizes: service=%zu, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) "aal0_rx=%zu\n", lanai_buf_size(&lanai->service),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) if (left-- == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) get_statistics(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) return sprintf(page, "cells in error: overflow=%u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) lanai->stats.ovfl_trash, lanai->stats.vci_trash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) lanai->stats.hec_err, lanai->stats.atm_ovfl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) return sprintf(page, "PCI errors: parity_detect=%u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) "master_abort=%u, master_target_abort=%u,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) lanai->stats.pcierr_parity_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) lanai->stats.pcierr_serr_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) lanai->stats.pcierr_m_target_abort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) return sprintf(page, " slave_target_abort=%u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) lanai->stats.pcierr_master_parity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) return sprintf(page, " no_tx=%u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) lanai->stats.service_notx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) lanai->stats.service_rxnotaal5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (left-- == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) return sprintf(page, "resets: dma=%u, card=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) lanai->stats.dma_reenable, lanai->stats.card_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /* At this point, "left" should be the VCI we're looking for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) read_lock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) for (; ; left++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (left >= NUM_VCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if ((lvcc = lanai->vccs[left]) != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) (*pos)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) /* Note that we re-use "left" here since we're done with it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u", (vci_t) left,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) lvcc->nref, lvcc->stats.rx_nomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) if (lvcc->rx.atmvcc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) left += sprintf(&page[left], ",\n rx_AAL=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) left += sprintf(&page[left], ", rx_buf_size=%zu, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) "rx_bad_len=%u,\n rx_service_trash=%u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) "rx_service_stream=%u, rx_bad_crc=%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) lanai_buf_size(&lvcc->rx.buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) lvcc->stats.x.aal5.rx_badlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) lvcc->stats.x.aal5.service_trash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) lvcc->stats.x.aal5.service_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) lvcc->stats.x.aal5.service_rxcrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) if (lvcc->tx.atmvcc != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) left += sprintf(&page[left], ",\n tx_AAL=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) "tx_buf_size=%zu, tx_qos=%cBR, tx_backlogged=%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) lanai_buf_size(&lvcc->tx.buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) vcc_is_backlogged(lvcc) ? 'Y' : 'N');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) page[left++] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) page[left] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) return left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #endif /* CONFIG_PROC_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* -------------------- HOOKS: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static const struct atmdev_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .dev_close = lanai_dev_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .open = lanai_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .close = lanai_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .send = lanai_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .phy_put = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .phy_get = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .change_qos = lanai_change_qos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .proc_read = lanai_proc_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .owner = THIS_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) /* initialize one probed card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) static int lanai_init_one(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) const struct pci_device_id *ident)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) struct lanai_dev *lanai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) struct atm_dev *atmdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) lanai = kzalloc(sizeof(*lanai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) if (lanai == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) printk(KERN_ERR DEV_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) ": couldn't allocate dev_data structure!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) atmdev = atm_dev_register(DEV_LABEL, &pci->dev, &ops, -1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) if (atmdev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) printk(KERN_ERR DEV_LABEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) ": couldn't register atm device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) kfree(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) atmdev->dev_data = lanai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) lanai->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) lanai->type = (enum lanai_type) ident->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) result = lanai_dev_open(atmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) DPRINTK("lanai_start() failed, err=%d\n", -result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) atm_dev_deregister(atmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) kfree(lanai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static const struct pci_device_id lanai_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) { 0, } /* terminal entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) static struct pci_driver lanai_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .name = DEV_LABEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .id_table = lanai_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) .probe = lanai_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) module_pci_driver(lanai_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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