^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Device driver for Interphase ATM PCI adapter cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Author: Peter Wang <pwang@iphase.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Interphase Corporation <www.iphase.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Version: 1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) iphase.h: This is the header file for iphase.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) This software may be used and distributed according to the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) of the GNU General Public License (GPL), incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Drivers based on this skeleton fall under the GPL and must retain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) the authorship (implicit copyright) notice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) was originally written by Monalisa Agrawal at UNH. Now this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) supports a variety of varients of Interphase ATM PCI (i)Chip adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) in terms of PHY type, the size of control memory and the size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) packet memory. The following are the change log and history:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Bugfix the Mona's UBR driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Modify the basic memory allocation and dma logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Port the driver to the latest kernel from 2.0.46.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Complete the ABR logic of the driver, and added the ABR work-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) around for the hardware anormalies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Add the CBR support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Add the flow control logic to the driver to allow rate-limit VC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Add 4K VC support to the board with 512K control memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Add the support of all the variants of the Interphase ATM PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (25M UTP25) and x531 (DS3 and E3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Add SMP support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Support and updates available at: ftp://ftp.iphase.com/pub/atm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifndef IPHASE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IPHASE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /************************ IADBG DEFINE *********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* IADebugFlag Bit Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IF_IADBG_INIT_ADAPTER 0x00000001 // init adapter info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IF_IADBG_TX 0x00000002 // debug TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IF_IADBG_RX 0x00000004 // debug RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IF_IADBG_QUERY_INFO 0x00000008 // debug Request call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IF_IADBG_SHUTDOWN 0x00000010 // debug shutdown event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IF_IADBG_INTR 0x00000020 // debug interrupt DPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IF_IADBG_TXPKT 0x00000040 // debug TX PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IF_IADBG_RXPKT 0x00000080 // debug RX PKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IF_IADBG_ERR 0x00000100 // debug system error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IF_IADBG_EVENT 0x00000200 // debug event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IF_IADBG_DIS_INTR 0x00001000 // debug disable interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IF_IADBG_EN_INTR 0x00002000 // debug enable interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IF_IADBG_LOUD 0x00004000 // debugging info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IF_IADBG_VERY_LOUD 0x00008000 // excessive debugging info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IF_IADBG_CBR 0x00100000 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IF_IADBG_UBR 0x00200000 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IF_IADBG_ABR 0x00400000 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IF_IADBG_DESC 0x01000000 //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IF_IADBG_SUNI_STAT 0x02000000 // suni statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IF_IADBG_RESET 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IF_IADBG(f) if (IADebugFlag & (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_ATM_IA_DEBUG /* Debug build */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #else /* free build */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IF_LOUD(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IF_VERY_LOUD(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IF_INIT_ADAPTER(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IF_INIT(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IF_SUNI_STAT(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IF_PVC_CHKPKT(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IF_QUERY_INFO(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IF_COPY_OVER(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IF_HANG(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IF_INTR(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IF_DIS_INTR(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IF_EN_INTR(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IF_TX(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IF_RX(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IF_TXDEBUG(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IF_VC(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IF_ERR(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IF_CBR(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IF_UBR(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IF_ABR(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IF_SHUTDOWN(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DbgPrint(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IF_EVENT(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IF_TXPKT(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IF_RXPKT(A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif /* CONFIG_ATM_IA_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define isprint(a) ((a >=' ')&&(a <= '~'))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ATM_DESC(skb) (skb->protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IA_SKB_STATE(skb) (skb->protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IA_DLED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IA_TX_DONE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* iadbg defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IA_CMD 0x7749
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int sub_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 maddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __user *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } IA_CMDBUF, *PIA_CMDBUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MEMDUMP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* sub_cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MEMDUMP_SEGREG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MEMDUMP_DEV 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MEMDUMP_REASSREG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MEMDUMP_FFL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define READ_REG 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define WAKE_DBG_WAIT 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /************************ IADBG DEFINE END ***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define Boolean(x) ((x) ? 1 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define NR_VCI 1024 /* number of VCIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define NR_VCI_LD 10 /* log2(NR_VCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NR_VCI_4K 4096 /* number of VCIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NR_VCI_4K_LD 12 /* log2(NR_VCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MEM_VALID 0xfffffff0 /* mask base address with this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #ifndef PCI_VENDOR_ID_IPHASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCI_VENDOR_ID_IPHASE 0x107e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifndef PCI_DEVICE_ID_IPHASE_5575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PCI_DEVICE_ID_IPHASE_5575 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DEV_LABEL "ia"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCR 207692
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ICR 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TBE 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FRTT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RIF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RDF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define NRMCODE 5 /* 0 - 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TRMCODE 3 /* 0 - 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CDFCODE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ATDFCODE 2 /* 0 - 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*---------------------- Packet/Cell Memory ------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DFL_TX_BUF_SZ 10240 /* 10 K buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DFL_TX_BUFFERS 50 /* number of packet buffers for Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) - descriptor 0 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DFL_RX_BUF_SZ 10240 /* 10k buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DFL_RX_BUFFERS 50 /* number of packet buffers for Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) - descriptor 0 unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct cpcs_trailer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u_short control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u_short length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u_int crc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct cpcs_trailer_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct cpcs_trailer *cpcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct ia_vcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int rxing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int txing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int NumCbrEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 saved_tx_quota;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int flow_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct sk_buff_head txing_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ltimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 vc_desc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct abr_vc_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u_char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u_char rdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u_short air;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u_int res[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u_int req_rm_cell_data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u_int req_rm_cell_data2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u_int add_rm_cell_data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u_int add_rm_cell_data2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* 32 byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct main_vc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u_short type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ABR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define UBR 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CBR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* ABR fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u_short nrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u_short trm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u_short rm_timestamp_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u_short rm_timestamp_lo:8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) crm:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u_short remainder; /* ABR and UBR fields - last 10 bits*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u_short next_vc_sched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u_short present_desc; /* all classes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u_short last_cell_slot; /* ABR and UBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u_short pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u_short fraction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u_short icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u_short atdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u_short mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u_short acr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u_short unack:8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) status:8; /* all classes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define UIOLI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CRC_APPEND 0x40 /* for status field - CRC-32 append */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ABR_STATE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* 8 byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct ext_vc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u_short atm_hdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u_short atm_hdr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u_short last_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u_short out_of_rate_link; /* reserved for UBR and CBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DLE_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TX_DLE_PSI 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Descriptor List Entries (DLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct dle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 sys_pkt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 local_pkt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u16 prq_wr_ptr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct dle_q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct dle *start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct dle *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct dle *read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct dle *write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct free_desc_q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int desc; /* Descriptor number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct free_desc_q *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct tx_buf_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned short desc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned short vc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned short res1; /* reserved field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned short bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned short buf_start_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned short buf_start_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned short res2[10]; /* reserved field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct rx_buf_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned short desc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned short vc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned short vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned short bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned short buf_start_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned short buf_start_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned short dma_start_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned short dma_start_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned short crc_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned short crc_lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned short res:8, timeout:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned short res2[5]; /* reserved field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*--------SAR stuff ---------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define EPROM_SIZE 0x40000 /* says 64K in the docs ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MAC1_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MAC2_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*------------ PCI Memory Space Map, 128K SAR memory ----------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*------------ Bus interface control registers -----------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IPHASE5575_BUS_CONTROL_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IPHASE5575_MAC1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IPHASE5575_REV 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IPHASE5575_EXT_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Bus Interface Control Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CTRL_FE_RST 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CTRL_LED 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CTRL_25MBPHY 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CTRL_ENCMBMEM 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CTRL_ENOFFSEG 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CTRL_ERRMASK 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CTRL_DLETMASK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CTRL_DLERMASK 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CTRL_FEMASK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CTRL_SEGMASK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CTRL_REASSMASK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CTRL_CSPREEMPT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CTRL_B128 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CTRL_B64 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CTRL_B48 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CTRL_B32 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CTRL_B16 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CTRL_B8 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Bus Interface Status Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define STAT_CMEMSIZ 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define STAT_ADPARCK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define STAT_RESVD 0x1fffff80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define STAT_ERRINT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define STAT_MARKINT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define STAT_DLETINT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define STAT_DLERINT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define STAT_FEINT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define STAT_SEGINT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define STAT_REASSINT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*--------------- Segmentation control registers -----------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* The segmentation registers are 16 bits access and the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) are defined as such so the addresses are the actual "offsets" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IDLEHEADHI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IDLEHEADLO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MAXRATE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define RATE155 0x64b1 // 16 bits float format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MAX_ATM_155 352768 // Cells/second p.118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define RATE25 0x5f9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define STPARMS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define STPARMS_1K 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define STPARMS_2K 0x0049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define STPARMS_4K 0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define COMP_EN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CBR_EN 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define ABR_EN 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define UBR_EN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define ABRUBR_ARB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define RM_TYPE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define RM_TYPE_4_0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SEG_COMMAND_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Values for the command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define RESET_SEG 0x0055
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define RESET_SEG_STATE 0x00aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define RESET_TX_CELL_CTR 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CBR_PTR_BASE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define ABR_SBPTR_BASE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define UBR_SBPTR_BASE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define ABRWQ_BASE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define UBRWQ_BASE 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define VCT_BASE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define VCTE_BASE 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CBR_TAB_BEG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CBR_TAB_END 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PRQ_ST_ADR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PRQ_ED_ADR 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PRQ_RD_PTR 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PRQ_WR_PTR 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define TCQ_ST_ADR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define TCQ_ED_ADR 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define TCQ_RD_PTR 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TCQ_WR_PTR 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SEG_QUEUE_BASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SEG_DESC_BASE 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MODE_REG_0 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define T_ONLINE 0x0002 /* (i)chipSAR is online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MODE_REG_1 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MODE_REG_1_VAL 0x0400 /*for propoer device operation*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SEG_INTR_STATUS_REG 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SEG_MASK_REG 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TRANSMIT_DONE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TCQ_NOT_EMPTY 0x1000 /* this can be used for both the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) status registers as well as the mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define CELL_CTR_HIGH_AUTO 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define CELL_CTR_HIGH_NOAUTO 0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CELL_CTR_LO_AUTO 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CELL_CTR_LO_NOAUTO 0xca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Diagnostic registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define NEXTDESC 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define NEXTVC 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PSLOTCNT 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define NEWDN 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define NEWVC 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SBPTR 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define ABRWQ_WRPTR 0x6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define ABRWQ_RDPTR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define UBRWQ_WRPTR 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define UBRWQ_RDPTR 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define CBR_VC 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define ABR_SBVC 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define UBR_SBVC 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define ABRNEXTLINK 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define UBRNEXTLINK 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*----------------- Reassembly control registers ---------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* The reassembly registers are 16 bits access and the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) are defined as such so the addresses are the actual "offsets" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MODE_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define R_ONLINE 0x0002 /* (i)chip is online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define IGN_RAW_FL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PROTOCOL_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define REASS_MASK_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define REASS_INTR_STATUS_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Interrupt Status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define RX_PKT_CTR_OF 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define RX_ERR_CTR_OF 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define RX_CELL_CTR_OF 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define RX_FREEQ_EMPT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define RX_EXCPQ_FL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define RX_RAWQ_FL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define RX_EXCP_RCVD 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define RX_PKT_RCVD 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define RX_RAW_RCVD 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DRP_PKT_CNTR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define ERR_CNTR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define RAW_BASE_ADR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define CELL_CTR0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define CELL_CTR1 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define REASS_COMMAND_REG 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Values for command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define RESET_REASS 0x0055
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define RESET_REASS_STATE 0x00aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define RESET_DRP_PKT_CNTR 0x00f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define RESET_ERR_CNTR 0x00f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define RESET_CELL_CNTR 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define RESET_REASS_ALL_REGS 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define REASS_DESC_BASE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define VC_LKUP_BASE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define REASS_TABLE_BASE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define REASS_QUEUE_BASE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define PKT_TM_CNT 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define TMOUT_RANGE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define INTRVL_CNTR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define TMOUT_INDX 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define VP_LKUP_BASE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define VP_FILTER 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define ABR_LKUP_BASE 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define FREEQ_ST_ADR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define FREEQ_ED_ADR 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define FREEQ_RD_PTR 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define FREEQ_WR_PTR 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define PCQ_ST_ADR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define PCQ_ED_ADR 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define PCQ_RD_PTR 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define PCQ_WR_PTR 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define EXCP_Q_ST_ADR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define EXCP_Q_ED_ADR 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define EXCP_Q_RD_PTR 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define EXCP_Q_WR_PTR 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define CC_FIFO_ST_ADR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define CC_FIFO_ED_ADR 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define CC_FIFO_RD_PTR 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define CC_FIFO_WR_PTR 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define STATE_REG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define BUF_SIZE 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define XTRA_RM_OFFSET 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define DRP_PKT_CNTR_NC 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define ERR_CNTR_NC 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define CELL_CNTR0_NC 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define CELL_CNTR1_NC 0x8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* State Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define EXCPQ_EMPTY 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define PCQ_EMPTY 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define FREEQ_EMPTY 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*----------------- Front End registers/ DMA control --------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* There is a lot of documentation error regarding these offsets ???
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) eg:- 2 offsets given 800, a00 for rx counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) similarly many others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) Remember again that the offsets are to be 4*register number, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) correct the #defines here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*--------------------------- RAM ---------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* These memory maps are actually offsets from the segmentation and reassembly RAM base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Segmentation Control Memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define TX_COMP_Q 0x1000 /* Transmit Complete Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define PKT_RDY_Q 0x1400 /* Packet Ready Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define CBR_SCHED_TABLE 0x1800 /* CBR Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define UBR_SCHED_TABLE 0x3000 /* UBR Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define UBR_WAIT_Q 0x4000 /* UBR Wait Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define ABR_SCHED_TABLE 0x5000 /* ABR Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define ABR_WAIT_Q 0x5800 /* ABR Wait Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define EXT_VC_TABLE 0x6000 /* Extended VC Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define MAIN_VC_TABLE 0x8000 /* Main VC Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SCHEDSZ 1024 /* ABR and UBR Scheduling Table size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define TX_DESC_TABLE_SZ 128 /* Number of entries in the Transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) Buffer Descriptor Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* These are used as table offsets in Descriptor Table address generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define DESC_MODE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define VC_INDEX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define BYTE_CNT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define PKT_START_HI 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define PKT_START_LO 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Descriptor Mode Word Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define EOM_EN 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define AAL5 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define APP_CRC32 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define CMPL_INT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define TABLE_ADDRESS(db, dn, to) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Reassembly Control Memory Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define VP_TABLE 0x5c00 /* VP Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define EXCEPTION_Q 0x5e00 /* Exception Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define PKT_COMP_Q 0x6800 /* Packet Complete Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define REASS_TABLE 0x7000 /* Reassembly Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define RX_VC_TABLE 0x7800 /* VC Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define ABR_VC_TABLE 0x8000 /* ABR VC Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define RX_DESC_TABLE_SZ 736 /* Number of entries in the Receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) Buffer Descriptor Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define VP_TABLE_SZ 256 /* Number of entries in VPTable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Buffer Descriptor Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define RX_ACT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define RX_VPVC 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define RX_CNG 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define RX_CER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define RX_PTE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define RX_OFL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define NUM_RX_EXCP 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Reassembly Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define NO_AAL5_PKT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define AAL5_PKT_REASSEMBLED 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define AAL5_PKT_TERMINATED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define RAW_PKT 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define REASS_ABR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*-------------------- Base Registers --------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PHY_BASE IPHASE5575_FRONT_END_REG_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) typedef volatile u_int ffreg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) typedef u_int rreg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) typedef struct _ffredn_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ffreg_t idlehead_high; /* Idle cell header (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ffreg_t idlehead_low; /* Idle cell header (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ffreg_t maxrate; /* Maximum rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ffreg_t stparms; /* Traffic Management Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ffreg_t rm_type; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u_int filler5[0x17 - 0x06];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ffreg_t cmd_reg; /* Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u_int filler18[0x20 - 0x18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ffreg_t cbr_base; /* CBR Pointer Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ffreg_t vbr_base; /* VBR Pointer Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ffreg_t abr_base; /* ABR Pointer Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ffreg_t ubr_base; /* UBR Pointer Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u_int filler24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ffreg_t vbrwq_base; /* VBR Wait Queue Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ffreg_t abrwq_base; /* ABR Wait Queue Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ffreg_t ubrwq_base; /* UBR Wait Queue Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ffreg_t vct_base; /* Main VC Table Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ffreg_t vcte_base; /* Extended Main VC Table Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u_int filler2a[0x2C - 0x2A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ffreg_t cbr_tab_beg; /* CBR Table Begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ffreg_t cbr_tab_end; /* CBR Table End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ffreg_t cbr_pointer; /* CBR Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u_int filler2f[0x30 - 0x2F];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u_int filler38[0x40 - 0x38];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ffreg_t queue_base; /* Base address for PRQ and TCQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ffreg_t desc_base; /* Base address of descriptor table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u_int filler42[0x45 - 0x42];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ffreg_t mode_reg_0; /* Mode register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ffreg_t mode_reg_1; /* Mode register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ffreg_t intr_status_reg;/* Interrupt Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ffreg_t mask_reg; /* Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ffreg_t state_reg; /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u_int filler4c[0x58 - 0x4c];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ffreg_t curr_desc_num; /* Contains the current descriptor num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ffreg_t next_desc; /* Next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ffreg_t next_vc; /* Next VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u_int filler5b[0x5d - 0x5b];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ffreg_t present_slot_cnt;/* Present slot count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u_int filler5e[0x6a - 0x5e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ffreg_t new_desc_num; /* New descriptor number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ffreg_t new_vc; /* New VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ffreg_t sched_tbl_ptr; /* Schedule table pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ffreg_t abrwq_wptr; /* ABR wait queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ffreg_t cbr_vc; /* CBR VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ffreg_t vbr_sb_vc; /* VBR SB VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ffreg_t abr_sb_vc; /* ABR SB VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ffreg_t ubr_sb_vc; /* UBR SB VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ffreg_t vbr_next_link; /* VBR next link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ffreg_t abr_next_link; /* ABR next link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ffreg_t ubr_next_link; /* UBR next link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u_int filler7a[0x7c-0x7a];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ffreg_t out_rate_head; /* Out of rate head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u_int filler7d[0xca-0x7d]; /* pad out to full address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u_int fillercc[0x100-0xcc]; /* pad out to full address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } ffredn_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) typedef struct _rfredn_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rreg_t mode_reg_0; /* Mode register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) rreg_t protocol_id; /* Protocol ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) rreg_t mask_reg; /* Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) rreg_t intr_status_reg;/* Interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) rreg_t err_cntr; /* Error Counter (cleared on read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u_int filler6[0x08 - 0x06];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rreg_t raw_base_adr; /* Base addr for raw cell Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u_int filler2[0x0c - 0x09];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u_int filler3[0x0f - 0x0e];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) rreg_t cmd_reg; /* Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) rreg_t desc_base; /* Base address for description table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) rreg_t vc_lkup_base; /* Base address for VC lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) rreg_t reass_base; /* Base address for reassembler table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) rreg_t queue_base; /* Base address for Communication queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u_int filler14[0x16 - 0x14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) rreg_t pkt_tm_cnt; /* Packet Timeout and count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rreg_t tmout_range; /* Range of reassembley IDs for timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) rreg_t intrvl_cntr; /* Packet aging interval counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) rreg_t tmout_indx; /* index of pkt being tested for aging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u_int filler1a[0x1c - 0x1a];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rreg_t vp_lkup_base; /* Base address for VP lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) rreg_t vp_filter; /* VP filter register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) rreg_t abr_lkup_base; /* Base address of ABR VC Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u_int filler1f[0x24 - 0x1f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) rreg_t fdq_st_adr; /* Free desc queue start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rreg_t fdq_ed_adr; /* Free desc queue end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) rreg_t fdq_rd_ptr; /* Free desc queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) rreg_t fdq_wr_ptr; /* Free desc queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rreg_t pcq_st_adr; /* Packet Complete queue start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) rreg_t pcq_ed_adr; /* Packet Complete queue end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) rreg_t excp_st_adr; /* Exception queue start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) rreg_t excp_ed_adr; /* Exception queue end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) rreg_t excp_rd_ptr; /* Exception queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rreg_t excp_wr_ptr; /* Exception queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u_int filler30[0x34 - 0x30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rreg_t raw_st_adr; /* Raw Cell start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rreg_t raw_ed_adr; /* Raw Cell end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) rreg_t raw_rd_ptr; /* Raw Cell read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rreg_t raw_wr_ptr; /* Raw Cell write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) rreg_t state_reg; /* State Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u_int filler39[0x42 - 0x39];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rreg_t buf_size; /* Buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u_int filler43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u_int filler45[0x84 - 0x45];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) rreg_t err_cntr_nc; /* Error Counter, Not clear on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u_int filler86[0x8c - 0x86];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u_int filler8e[0x100-0x8e]; /* pad out to full address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) } rfredn_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Atlantic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ffredn_t ffredn; /* F FRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rfredn_t rfredn; /* R FRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) } ia_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u_short f_vc_type; /* VC type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u_short f_nrm; /* Nrm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u_short f_nrmexp; /* Nrm Exp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u_short reserved6; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u_short f_crm; /* Crm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u_short reserved10; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u_short reserved12; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u_short reserved14; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u_short last_cell_slot; /* last_cell_slot_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u_short f_pcr; /* Peak Cell Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u_short fraction; /* fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u_short f_icr; /* Initial Cell Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u_short f_cdf; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u_short f_mcr; /* Minimum Cell Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u_short f_acr; /* Allowed Cell Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u_short f_status; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } f_vc_abr_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u_short r_status_rdf; /* status + RDF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u_short r_air; /* AIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u_short reserved4[14]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } r_vc_abr_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MRM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) typedef struct srv_cls_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 pcr; /* Peak Cell Rate (24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* VBR parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 scr; /* sustainable cell rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 max_burst_size; /* ?? cell rate or data rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* ABR only UNI 4.0 Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 mcr; /* Min Cell Rate (24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 icr; /* Initial Cell Rate (24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 tbe; /* Transient Buffer Exposure (24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 frtt; /* Fixed Round Trip Time (24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #if 0 /* Additional Parameters of TM 4.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) bits 31 30 29 28 27-25 24-22 21-19 18-9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) | NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #endif /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u8 nrm; /* Max # of Cells for each forward RM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) cell (3-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u8 trm; /* Time between forward RM cells (3-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u16 adtf; /* ACR Decrease Time Factor (10-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 cdf; /* Cutoff Decrease Factor (3-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 rif; /* Rate Increment Factor (4-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 rdf; /* Rate Decrease Factor (4-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u8 reserved; /* 8 bits to keep structure word aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) } srv_cls_param_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct testTable_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u16 lastTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u16 fract;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u8 vc_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u16 vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u16 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) } RX_ERROR_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 active: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 abr: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 ubr: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 cnt: 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define VC_ACTIVE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define VC_ABR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define VC_UBR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } vcstatus_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct ia_rfL_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 fdq_st; /* Free desc queue start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u32 fdq_ed; /* Free desc queue end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 fdq_rd; /* Free desc queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 fdq_wr; /* Free desc queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 pcq_st; /* Packet Complete queue start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 pcq_ed; /* Packet Complete queue end address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 pcq_rd; /* Packet Complete queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 pcq_wr; /* Packet Complete queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct ia_ffL_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 prq_st; /* Packet Ready Queue Start Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u32 prq_ed; /* Packet Ready Queue End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 prq_wr; /* Packet Ready Queue write pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 tcq_st; /* Transmit Complete Queue Start Address*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 tcq_ed; /* Transmit Complete Queue End Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 tcq_rd; /* Transmit Complete Queue read pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct desc_tbl_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct ia_vcc *iavcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct sk_buff *txskb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) typedef struct ia_rtn_q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct desc_tbl_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct ia_rtn_q *next, *tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } IARTN_Q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define SUNI_LOSV 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) enum ia_suni {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) SUNI_MASTER_RESET = 0x000, /* SUNI Master Reset and Identity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) SUNI_MASTER_CONFIG = 0x004, /* SUNI Master Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) SUNI_MASTER_INTR_STAT = 0x008, /* SUNI Master Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SUNI_RESERVED1 = 0x00c, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SUNI_MASTER_CLK_MONITOR = 0x010, /* SUNI Master Clock Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) SUNI_MASTER_CONTROL = 0x014, /* SUNI Master Clock Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Reserved (10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) SUNI_RSOP_CONTROL = 0x040, /* RSOP Control/Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) SUNI_RSOP_STATUS = 0x044, /* RSOP Status/Interrupt States */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) SUNI_TSOP_CONTROL = 0x050, /* TSOP Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) SUNI_TSOP_DIAG = 0x054, /* TSOP Disgnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Reserved (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) SUNI_RLOP_CS = 0x060, /* RLOP Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SUNI_RLOP_INTR = 0x064, /* RLOP Interrupt Enable/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SUNI_RLOP_LINE_FEBEL = 0x074, /* RLOP Line FEBE LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) SUNI_RLOP_LINE_FEBE = 0x078, /* RLOP Line FEBE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SUNI_RLOP_LINE_FEBEM = 0x07c, /* RLOP Line FEBE MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) SUNI_TLOP_CONTROL = 0x080, /* TLOP Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SUNI_TLOP_DISG = 0x084, /* TLOP Disgnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Reserved (14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SUNI_RPOP_CS = 0x0c0, /* RPOP Status/Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) SUNI_RPOP_INTR = 0x0c4, /* RPOP Interrupt/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SUNI_RPOP_RESERVED = 0x0c8, /* RPOP Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) SUNI_RPOP_INTR_ENA = 0x0cc, /* RPOP Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Reserved (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SUNI_RPOP_PATH_SIG = 0x0dc, /* RPOP Path Signal Label */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SUNI_RPOP_FEBEL = 0x0e8, /* RPOP Path FEBE LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) SUNI_RPOP_FEBEM = 0x0ec, /* RPOP Path FEBE MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Reserved (4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SUNI_TPOP_CNTRL_DAIG = 0x100, /* TPOP Control/Disgnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SUNI_TPOP_POINTER_CTRL = 0x104, /* TPOP Pointer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SUNI_TPOP_SOURCER_CTRL = 0x108, /* TPOP Source Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Reserved (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SUNI_TPOP_ARB_PRTL = 0x114, /* TPOP Arbitrary Pointer LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) SUNI_TPOP_ARB_PRTM = 0x118, /* TPOP Arbitrary Pointer MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) SUNI_TPOP_RESERVED2 = 0x11c, /* TPOP Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SUNI_TPOP_PATH_SIG = 0x120, /* TPOP Path Signal Lable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) SUNI_TPOP_PATH_STATUS = 0x124, /* TPOP Path Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Reserved (6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) SUNI_RACP_CS = 0x140, /* RACP Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) SUNI_RACP_INTR = 0x144, /* RACP Interrupt Enable/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SUNI_RACP_HDR_PATTERN = 0x148, /* RACP Match Header Pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) SUNI_RACP_HDR_MASK = 0x14c, /* RACP Match Header Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SUNI_RACP_CORR_HCS = 0x150, /* RACP Correctable HCS Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) SUNI_RACP_UNCORR_HCS = 0x154, /* RACP Uncorrectable HCS Err Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Reserved (10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) SUNI_TACP_CONTROL = 0x180, /* TACP Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SUNI_TACP_IDLE_HDR_PAT = 0x184, /* TACP Idle Cell Header Pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SUNI_TACP_IDLE_PAY_PAY = 0x188, /* TACP Idle Cell Payld Octet Patrn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Reserved (5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Reserved (24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* FIXME: unused but name conflicts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * SUNI_MASTER_TEST = 0x200, SUNI Master Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) SUNI_RESERVED_TEST = 0x204 /* SUNI Reserved for Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) typedef struct _SUNI_STATS_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 valid; // 1 = oc3 PHY card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 carrier_detect; // GPIN input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) // RSOP: receive section overhead processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u16 rsop_oof_state; // 1 = out of frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u16 rsop_lof_state; // 1 = loss of frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u16 rsop_los_state; // 1 = loss of signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 rsop_los_count; // loss of signal count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u32 rsop_bse_count; // section BIP-8 error count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) // RLOP: receive line overhead processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u16 rlop_ferf_state; // 1 = far end receive failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u16 rlop_lais_state; // 1 = line AIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 rlop_lbe_count; // BIP-24 count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u32 rlop_febe_count; // FEBE count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) // RPOP: receive path overhead processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u16 rpop_lop_state; // 1 = LOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u16 rpop_pais_state; // 1 = path AIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u16 rpop_pyel_state; // 1 = path yellow alert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) u32 rpop_bip_count; // path BIP-8 error count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 rpop_febe_count; // path FEBE error count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u16 rpop_psig; // path signal label value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) // RACP: receive ATM cell processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u16 racp_hp_state; // hunt/presync state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 racp_fu_count; // FIFO underrun count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 racp_fo_count; // FIFO overrun count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u32 racp_chcs_count; // correctable HCS error count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u32 racp_uchcs_count; // uncorrectable HCS error count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } IA_SUNI_STATS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) typedef struct iadev_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /*-----base pointers into (i)chipSAR+ address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u32 __iomem *phy; /* Base pointer into phy (SUNI). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 __iomem *dma; /* Base pointer into DMA control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 __iomem *reg; /* Base pointer to SAR registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u32 __iomem *seg_reg; /* base pointer to segmentation engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) internal registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u32 __iomem *reass_reg; /* base pointer to reassemble engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) internal registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 __iomem *ram; /* base pointer to SAR RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) void __iomem *seg_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) void __iomem *reass_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct dle_q tx_dle_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct free_desc_q *tx_free_desc_qhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct sk_buff_head tx_dma_q, tx_backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) spinlock_t tx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) IARTN_Q tx_return_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 close_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) wait_queue_head_t close_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) wait_queue_head_t timeout_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct cpcs_trailer_desc *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u16 num_tx_desc, tx_buf_sz, rate_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 tx_cell_cnt, tx_pkt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct dle_q rx_dle_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct free_desc_q *rx_free_desc_qhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct sk_buff_head rx_dma_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) spinlock_t rx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct atm_vcc **rx_open; /* list of all open VCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u16 num_rx_desc, rx_buf_sz, rxing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 rx_pkt_ram, rx_tmp_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) unsigned long rx_tmp_jif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) void __iomem *RX_DESC_BASE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct atm_dev *next_board; /* other iphase devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) unsigned int real_base; /* real and virtual base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) unsigned int pci_map_size; /*pci map size of board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) unsigned char irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) unsigned char bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) unsigned char dev_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) u_short phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u_short num_vc, memSize, memType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct ia_ffL_t ffL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct ia_rfL_t rfL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* Suni stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) // IA_SUNI_STATS suni_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) unsigned char carrier_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* CBR related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) // transmit DMA & Receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unsigned int tx_dma_cnt; // number of elements on dma queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) unsigned int rx_dma_cnt; // number of elements on rx dma queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) // receive MARK for Cell FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned int rx_mark_cnt; // number of elements on mark queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) unsigned int CbrTotEntries; // Total CBR Entries in Scheduling Table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) unsigned int CbrRemEntries; // Remaining CBR Entries in Scheduling Table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) unsigned int CbrEntryPt; // CBR Sched Table Entry Point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) unsigned int Granularity; // CBR Granularity given Table Size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* ABR related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) unsigned int sum_mcr, sum_cbr, LineRate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) unsigned int n_abr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct desc_tbl_t *desc_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) u_short host_tcq_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct testTable_t **testTable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dma_addr_t tx_dle_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dma_addr_t rx_dle_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } IADEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /******************* IDT77105 25MB/s PHY DEFINE *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) enum ia_mb25 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) MB25_MASTER_CTRL = 0x00, /* Master control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) MB25_INTR_STATUS = 0x04, /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) MB25_DIAG_CONTROL = 0x08, /* Diagnostic control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) MB25_LED_HEC = 0x0c, /* LED driver and HEC status/control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) MB25_LOW_BYTE_COUNTER = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) MB25_HIGH_BYTE_COUNTER = 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * Master Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define MB25_MC_UPLO 0x80 /* UPLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define MB25_MC_DREC 0x40 /* Discard receive cell errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define MB25_MC_TDPC 0x10 /* Transmit data parity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define MB25_MC_DRIC 0x08 /* Discard receive idle cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define MB25_MC_HALTTX 0x04 /* Halt Tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define MB25_MC_UMS 0x02 /* UTOPIA mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define MB25_MC_ENABLED 0x01 /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * Interrupt Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define MB25_IS_HECECR 0x20 /* HEC error cell received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define MB25_IS_SCR 0x10 /* "Short Cell" Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * Diagnostic Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define MB25_DC_FTXCD 0x80 /* Force TxClav deassert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define MB25_DC_RXCOS 0x40 /* RxClav operation select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define MB25_DC_IXPE 0x08 /* Insert xmit payload error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define MB25_DC_LB_MASK 0x03 /* Loopback control mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define MB25_DC_LL 0x03 /* Line Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define MB25_DC_PL 0x02 /* PHY Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define MB25_DC_NM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define FE_MASK 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define FE_MULTI_MODE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define FE_SINGLE_MODE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define FE_UTP_OPTION 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define FE_25MBIT_PHY 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define FE_DS3_PHY 0x0080 /* DS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define FE_E3_PHY 0x0090 /* E3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) enum suni_pm7345 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) SUNI_CONFIG = 0x000, /* SUNI Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) SUNI_INTR_ENBL = 0x004, /* SUNI Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SUNI_INTR_STAT = 0x008, /* SUNI Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) SUNI_CONTROL = 0x00c, /* SUNI Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) SUNI_ID_RESET = 0x010, /* SUNI Reset and Identity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) SUNI_DATA_LINK_CTRL = 0x014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) SUNI_RBOC_CONF_INTR_ENBL = 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) SUNI_RBOC_STAT = 0x01c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SUNI_DS3_FRM_CFG = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SUNI_DS3_FRM_INTR_ENBL = 0x024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) SUNI_DS3_FRM_INTR_STAT = 0x028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) SUNI_DS3_FRM_STAT = 0x02c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) SUNI_RFDL_CFG = 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) SUNI_RFDL_ENBL_STAT = 0x034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) SUNI_RFDL_STAT = 0x038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SUNI_RFDL_DATA = 0x03c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) SUNI_PMON_CHNG = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) SUNI_PMON_INTR_ENBL_STAT = 0x044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* SUNI_RESERVED1 (0x13 - 0x11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) SUNI_PMON_LCV_EVT_CNT_LSB = 0x050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) SUNI_PMON_LCV_EVT_CNT_MSB = 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SUNI_PMON_FBE_EVT_CNT_LSB = 0x058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) SUNI_PMON_SEZ_DET_CNT_LSB = 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) SUNI_PMON_SEZ_DET_CNT_MSB = 0x064,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) SUNI_PMON_PE_EVT_CNT_LSB = 0x068,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) SUNI_PMON_PE_EVT_CNT_MSB = 0x06c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) SUNI_PMON_PPE_EVT_CNT_LSB = 0x070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SUNI_PMON_PPE_EVT_CNT_MSB = 0x074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) SUNI_DS3_TRAN_CFG = 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) SUNI_DS3_TRAN_DIAG = 0x084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* SUNI_RESERVED2 (0x23 - 0x21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) SUNI_XFDL_CFG = 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) SUNI_XFDL_INTR_ST = 0x094,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) SUNI_XFDL_XMIT_DATA = 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) SUNI_XBOC_CODE = 0x09c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) SUNI_SPLR_CFG = 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) SUNI_SPLR_INTR_EN = 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) SUNI_SPLR_INTR_ST = 0x0a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) SUNI_SPLR_STATUS = 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) SUNI_SPLT_CFG = 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SUNI_SPLT_CNTL = 0x0b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) SUNI_SPLT_DIAG_G1 = 0x0b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SUNI_SPLT_F1 = 0x0bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) SUNI_CPPM_LOC_METERS = 0x0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) SUNI_CPPM_FEBE_CNT_LSB = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) SUNI_CPPM_FEBE_CNT_MSB = 0x0dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SUNI_RXCP_CTRL = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SUNI_RXCP_FCTRL = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) SUNI_RXCP_INTR_EN_STS = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) SUNI_RXCP_IDLE_PAT_H1 = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) SUNI_RXCP_IDLE_PAT_H2 = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SUNI_RXCP_IDLE_PAT_H3 = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) SUNI_RXCP_IDLE_PAT_H4 = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SUNI_RXCP_IDLE_MASK_H1 = 0x11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SUNI_RXCP_IDLE_MASK_H2 = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SUNI_RXCP_IDLE_MASK_H3 = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) SUNI_RXCP_IDLE_MASK_H4 = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) SUNI_RXCP_CELL_PAT_H1 = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) SUNI_RXCP_CELL_PAT_H2 = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) SUNI_RXCP_CELL_PAT_H3 = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) SUNI_RXCP_CELL_PAT_H4 = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SUNI_RXCP_CELL_MASK_H1 = 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SUNI_RXCP_CELL_MASK_H2 = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SUNI_RXCP_CELL_MASK_H3 = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) SUNI_RXCP_CELL_MASK_H4 = 0x148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) SUNI_RXCP_HCS_CS = 0x14c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* SUNI_RESERVED3 (0x57 - 0x54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) SUNI_TXCP_CTRL = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SUNI_TXCP_INTR_EN_STS = 0x164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) SUNI_TXCP_IDLE_PAT_H1 = 0x168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) SUNI_TXCP_IDLE_PAT_H2 = 0x16c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) SUNI_TXCP_IDLE_PAT_H3 = 0x170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) SUNI_TXCP_IDLE_PAT_H4 = 0x174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) SUNI_TXCP_IDLE_PAT_H5 = 0x178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SUNI_TXCP_IDLE_PAYLOAD = 0x17c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SUNI_E3_FRM_FRAM_OPTIONS = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) SUNI_E3_FRM_MAINT_OPTIONS = 0x184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) SUNI_E3_FRM_MAINT_INTR_IND = 0x194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) SUNI_E3_FRM_MAINT_STAT = 0x198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) SUNI_RESERVED4 = 0x19c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) SUNI_TTB_CTRL = 0x1b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) SUNI_TTB_IND_ADDR = 0x1b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) SUNI_TTB_IND_DATA = 0x1bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* SUNI_PAD5 (0x7f - 0x71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) SUNI_MASTER_TEST = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* SUNI_PAD6 (0xff - 0x80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define SUNI_PM7345_T suni_pm7345_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define SUNI_PM7345 0x20 /* Suni chip type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define SUNI_PM5346 0x30 /* Suni chip type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * SUNI_PM7345 Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define SUNI_PM7345_CLB 0x01 /* Cell loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define SUNI_PM7345_PLB 0x02 /* Payload loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define SUNI_PM7345_LLB 0x80 /* Line loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * DS3 FRMR Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * DS3 FRMR Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define SUNI_DS3_REDV 0x40 /* DS3 RED state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define SUNI_DS3_CBITV 0x20 /* Application ID channel state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define SUNI_DS3_IDLV 0x08 /* Idle signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define SUNI_DS3_OOFV 0x02 /* Out of frame state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define SUNI_DS3_LOSV 0x01 /* Loss of signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * E3 FRMR Interrupt/Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define SUNI_E3_LCVI 0x10 /* Line code violation intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define SUNI_E3_COFAI 0x08 /* Change of frame align intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define SUNI_E3_OOFI 0x04 /* Out of frame intr status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define SUNI_E3_LOS 0x02 /* Loss of signal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define SUNI_E3_OOF 0x01 /* Out of frame state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * E3 FRMR Maintenance Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * RXCP Control/Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define SUNI_DS3_HCSADD 0x20 /* Add coset poly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * RXCP Interrupt Enable/Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define SUNI_DS3_OOCDI 0x10 /* SYNC state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /* ia_eeprom define*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define MEM_SIZE_128K 0x0000 /* board has 128k buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* 0x3 to 0xF are reserved for future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define NOVRAM_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define CMD_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /***********
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * Switches and defines for header files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * The following defines are used to turn on and off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * various options in the header files. Primarily useful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * for debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ***********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * a list of the commands that can be sent to the NOVRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define EXTEND 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define IAWRITE 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define IAREAD 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define ERASE 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define EWDS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define WRAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define ERAL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define EWEN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * these bits duplicate the hw_flip.h register settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * note: how the data in / out bits are defined in the flipper specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define NVCE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define NVSK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define NVDO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define NVDI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /***********************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * This define ands the value and the current config register and puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * the result in the config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define CFG_AND(val) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) u32 t; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) t &= (val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /***********************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * This define ors the value and the current config register and puts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * the result in the config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define CFG_OR(val) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) u32 t; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) t |= (val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /***********************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * Send a command to the NOVRAM, the command is in cmd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * clear CE and SK. Then assert CE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * Clock each of the command bits out in the correct order with SK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * exit with CE still asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define NVRAM_CMD(cmd) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u_short c = cmd; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) CFG_AND(~(NVCE|NVSK)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) CFG_OR(NVCE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) for (i=0; i<CMD_LEN; i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) c <<= 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /***********************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * clear the CE, this must be used after each command is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define NVRAM_CLR_CE {CFG_AND(~NVCE)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /***********************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * clock the data bit in bitval out to the NOVRAM. The bitval must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * a 1 or 0, or the clockout operation is undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define NVRAM_CLKOUT(bitval) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) CFG_AND(~NVDI); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) CFG_OR((bitval) ? NVDI : 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) CFG_OR(NVSK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) CFG_AND( ~NVSK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /***********************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * clock the data bit in and return a 1 or 0, depending on the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * that was received from the NOVRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ***********************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define NVRAM_CLKIN(value) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) u32 _t; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) CFG_OR(NVSK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) CFG_AND(~NVSK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) value = (_t & NVDO) ? 1 : 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #endif /* IPHASE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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