^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2000 ATecoM GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The author may be reached at ecd@atecom.com.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifndef _IDT77252_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define _IDT77252_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Makros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VPCI2VC(card, vpi, vci) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (((vpi) << card->vcibits) | ((vci) & card->vcimask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* DEBUGGING definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DBG_RAW_CELL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DBG_TINY 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DBG_GENERAL 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DBG_XGENERAL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DBG_INIT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DBG_DEINIT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DBG_INTERRUPT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DBG_OPEN_CONN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DBG_CLOSE_CONN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DBG_RX_DATA 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DBG_TX_DATA 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifdef CONFIG_ATM_IDT77252_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CPRINTK(args...) do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OPRINTK(args...) do { if (debug & DBG_OPEN_CONN) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IPRINTK(args...) do { if (debug & DBG_INIT) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DIPRINTK(args...) do { if (debug & DBG_DEINIT) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TXPRINTK(args...) do { if (debug & DBG_TX_DATA) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RXPRINTK(args...) do { if (debug & DBG_RX_DATA) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XPRINTK(args...) do { if (debug & DBG_XGENERAL) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DPRINTK(args...) do { if (debug & DBG_GENERAL) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NPRINTK(args...) do { if (debug & DBG_TINY) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RPRINTK(args...) do { if (debug & DBG_RAW_CELL) printk(args); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define INTPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DIPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TXPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RXPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RPRINTK(args...) do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SCHED_UBR0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCHED_UBR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCHED_VBR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SCHED_ABR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCHED_CBR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SCQFULL_TIMEOUT HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Free Buffer Queue Layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SAR_FB_SIZE_0 (2048 - 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SAR_FB_SIZE_1 (4096 - 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SAR_FB_SIZE_2 (8192 - 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SAR_FB_SIZE_3 (16384 - 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SAR_FBQ0_LOW 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SAR_FBQ0_HIGH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SAR_FBQ1_LOW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SAR_FBQ1_HIGH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SAR_FBQ2_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SAR_FBQ2_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SAR_FBQ3_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SAR_FBQ3_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SAR_TST_RESERVED 44 /* Num TST reserved for UBR/ABR/VBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SAR_TST_RESERVED 0 /* Num TST reserved for UBR/ABR/VBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TCT_CBR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TCT_UBR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TCT_VBR 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TCT_ABR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TCT_TYPE 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TCT_RR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TCT_LMCR 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TCT_SCD_MASK 0x0007ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TCT_TSIF 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TCT_HALT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TCT_IDLE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TCT_FLAG_UBR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Structure describing an IDT77252 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct scqe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 word_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 word_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 word_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SCQ_ENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SCQ_SIZE (SCQ_ENTRIES * sizeof(struct scqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SCQ_MASK (SCQ_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct scq_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct scqe *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct scqe *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct scqe *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) atomic_t used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long trans_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long scd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spinlock_t skblock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct sk_buff_head transmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct sk_buff_head pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct rx_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct sk_buff_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct aal1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct sk_buff *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned char sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct vc_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct rate_estimator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int ewma_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u64 cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u64 last_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) long avcps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 maxcps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct vc_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define VCF_TX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define VCF_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define VCF_IDLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define VCF_RSV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 init_er;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 lacr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 max_er;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int ntste;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct atm_vcc *tx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct atm_vcc *rx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct idt77252_dev *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct scq_info *scq; /* To keep track of the SCQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct rate_estimator *estimator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int scd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct rx_pool rx_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct aal1 aal1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } rcv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* RCTE - Receive Connection Table Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct rct_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 buffer_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 aal5_crc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* RSQ - Receive Status Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SAR_RSQE_VALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SAR_RSQE_IDLE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SAR_RSQE_BUF_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SAR_RSQE_BUF_ASGN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SAR_RSQE_NZGFC 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SAR_RSQE_EPDU 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SAR_RSQE_BUF_CONT 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SAR_RSQE_EFCIE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SAR_RSQE_CLP 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SAR_RSQE_CRC 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SAR_RSQE_CELLCNT 0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define RSQSIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define RSQ_NUM_ENTRIES (RSQSIZE / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define RSQ_ALIGNMENT 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct rsq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 word_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 word_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 word_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct rsq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct rsq_entry *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct rsq_entry *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct rsq_entry *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* TSQ - Transmit Status Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SAR_TSQE_INVALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SAR_TSQE_TIMESTAMP 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SAR_TSQE_TYPE 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SAR_TSQE_TYPE_TIMER 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SAR_TSQE_TYPE_TSR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SAR_TSQE_TYPE_IDLE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SAR_TSQE_TYPE_TBD_COMP 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SAR_TSQE_TAG(stat) (((stat) >> 24) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TSQSIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TSQ_NUM_ENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TSQ_ALIGNMENT 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct tsq_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 word_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 word_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct tsq_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct tsq_entry *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct tsq_entry *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct tsq_entry *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct tst_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 tste;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TSTE_MASK 0x601fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TSTE_OPC_MASK 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TSTE_OPC_NULL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TSTE_OPC_CBR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TSTE_OPC_VAR 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TSTE_OPC_JMP 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TSTE_PUSH_IDLE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TSTE_PUSH_ACTIVE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TST_SWITCH_DONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TST_SWITCH_PENDING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TST_SWITCH_WAIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define FBQ_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define FBQ_SIZE (1 << FBQ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define FBQ_MASK (FBQ_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct sb_pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct sk_buff *skb[FBQ_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define POOL_HANDLE(queue, index) (((queue + 1) << 16) | (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define POOL_QUEUE(handle) (((handle) >> 16) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define POOL_INDEX(handle) ((handle) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct idt77252_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct tsq_info tsq; /* Transmit Status Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct rsq_info rsq; /* Receive Status Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct pci_dev *pcidev; /* PCI handle (desriptor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct atm_dev *atmdev; /* ATM device desriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) void __iomem *membase; /* SAR's memory base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long srambase; /* SAR's sram base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void __iomem *fbq[4]; /* FBQ fill addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) spinlock_t cmd_lock; /* for r/w utility/sram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned long softstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags; /* see blow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct work_struct tqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned long tct_base; /* TCT base address in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long rct_base; /* RCT base address in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned long rt_base; /* Rate Table base in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned long scd_base; /* SCD base address in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned long tst[2]; /* TST base address in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long abrst_base; /* ABRST base address in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long fifo_base; /* RX FIFO base in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long irqstat[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int sramsize; /* SAR's sram size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int tct_size; /* total TCT entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int rct_size; /* total RCT entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int scd_size; /* length of SCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int tst_size; /* total TST entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int tst_free; /* free TSTEs in TST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int abrst_size; /* size of ABRST in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int fifo_size; /* size of RX FIFO in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int vpibits; /* Bits used for VPI index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int vcibits; /* Bits used for VCI index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int vcimask; /* Mask for VCI index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int utopia_pcr; /* Utopia Itf's Cell Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int link_pcr; /* PHY's Peek Cell Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct vc_map **vcs; /* Open Connections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct vc_map **scd2vc; /* SCD to Connection map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct tst_info *soft_tst; /* TST to Connection map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int tst_index; /* Current TST in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct timer_list tst_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) spinlock_t tst_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long tst_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct sb_pool sbpool[4]; /* Pool of RX skbuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct sk_buff *raw_cell_head; /* Pointer to raw cell queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 *raw_cell_hnd; /* Pointer to RCQ handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dma_addr_t raw_cell_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int index; /* SAR's ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int revision; /* chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) char name[16]; /* Device name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct idt77252_dev *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* definition for flag field above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define IDT77252_BIT_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define IDT77252_BIT_INTERRUPT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define ATM_CELL_PAYLOAD 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define FREEBUF_ALIGNMENT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Makros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define ALIGN_ADDRESS(addr, alignment) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* ABR SAR Network operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SAR_REG_DR0 (card->membase + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SAR_REG_DR1 (card->membase + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SAR_REG_DR2 (card->membase + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SAR_REG_DR3 (card->membase + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SAR_REG_CMD (card->membase + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SAR_REG_CFG (card->membase + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SAR_REG_STAT (card->membase + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SAR_REG_RSQB (card->membase + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SAR_REG_RSQT (card->membase + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SAR_REG_RSQH (card->membase + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SAR_REG_CDC (card->membase + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SAR_REG_VPEC (card->membase + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SAR_REG_ICC (card->membase + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SAR_REG_RAWCT (card->membase + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SAR_REG_TMR (card->membase + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SAR_REG_TSTB (card->membase + 0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SAR_REG_TSQB (card->membase + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SAR_REG_TSQT (card->membase + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SAR_REG_TSQH (card->membase + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SAR_REG_GP (card->membase + 0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SAR_REG_VPM (card->membase + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SAR_REG_RXFD (card->membase + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SAR_REG_RXFT (card->membase + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SAR_REG_RXFH (card->membase + 0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SAR_REG_RAWHND (card->membase + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SAR_REG_RXSTAT (card->membase + 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SAR_REG_ABRSTD (card->membase + 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SAR_REG_ABRRQ (card->membase + 0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SAR_REG_VBRRQ (card->membase + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SAR_REG_RTBL (card->membase + 0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SAR_REG_MDFCT (card->membase + 0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SAR_REG_TXSTAT (card->membase + 0x7C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SAR_REG_TCMDQ (card->membase + 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SAR_REG_IRCP (card->membase + 0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SAR_REG_FBQP0 (card->membase + 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SAR_REG_FBQP1 (card->membase + 0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SAR_REG_FBQP2 (card->membase + 0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SAR_REG_FBQP3 (card->membase + 0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SAR_REG_FBQS0 (card->membase + 0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SAR_REG_FBQS1 (card->membase + 0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SAR_REG_FBQS2 (card->membase + 0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SAR_REG_FBQS3 (card->membase + 0xA4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SAR_REG_FBQWP0 (card->membase + 0xA8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SAR_REG_FBQWP1 (card->membase + 0xAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SAR_REG_FBQWP2 (card->membase + 0xB0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SAR_REG_FBQWP3 (card->membase + 0xB4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SAR_REG_NOW (card->membase + 0xB8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SAR_CMD_NO_OPERATION 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SAR_CMD_WRITE_SRAM 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SAR_CMD_READ_SRAM 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SAR_CMD_READ_UTILITY 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SAR_CMD_WRITE_UTILITY 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SAR_CMD_OPEN_CONNECTION (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SAR_CMD_CLOSE_CONNECTION SAR_CMD_OPENCLOSE_CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Configuration Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SAR_CFG_SWRST 0x80000000 /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SAR_CFG_LOOP 0x40000000 /* Internal Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SAR_CFG_RXPTH 0x20000000 /* Receive Path Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SAR_CFG_IDLE_CLP 0x10000000 /* SAR set CLP Bits of Null Cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SAR_CFG_TX_FIFO_SIZE_1 0x04000000 /* TX FIFO Size = 1 cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SAR_CFG_TX_FIFO_SIZE_2 0x08000000 /* TX FIFO Size = 2 cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000 /* TX FIFO Size = 4 cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SAR_CFG_TX_FIFO_SIZE_9 0x00000000 /* TX FIFO Size = 9 cells (full) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SAR_CFG_NO_IDLE 0x02000000 /* SAR sends no Null Cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SAR_CFG_RSVD1 0x01000000 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SAR_CFG_RXSTQ_SIZE_2k 0x00000000 /* RX Stat Queue Size = 2048 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SAR_CFG_RXSTQ_SIZE_4k 0x00400000 /* RX Stat Queue Size = 4096 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SAR_CFG_RXSTQ_SIZE_8k 0x00800000 /* RX Stat Queue Size = 8192 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SAR_CFG_RXSTQ_SIZE_R 0x00C00000 /* RX Stat Queue Size = reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SAR_CFG_ICAPT 0x00200000 /* accept Invalid Cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SAR_CFG_IGGFC 0x00100000 /* Ignore GFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SAR_CFG_VPVCS_0 0x00000000 /* VPI/VCI Select bit range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SAR_CFG_VPVCS_1 0x00040000 /* VPI/VCI Select bit range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SAR_CFG_VPVCS_2 0x00080000 /* VPI/VCI Select bit range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SAR_CFG_VPVCS_8 0x000C0000 /* VPI/VCI Select bit range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SAR_CFG_CNTBL_1k 0x00000000 /* Connection Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SAR_CFG_CNTBL_4k 0x00010000 /* Connection Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SAR_CFG_CNTBL_16k 0x00020000 /* Connection Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SAR_CFG_CNTBL_512 0x00030000 /* Connection Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SAR_CFG_VPECA 0x00008000 /* VPI/VCI Error Cell Accept */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SAR_CFG_RXINT_NOINT 0x00000000 /* No Interrupt on PDU received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SAR_CFG_RXINT_NODELAY 0x00001000 /* Interrupt without delay to host*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SAR_CFG_RXINT_256US 0x00002000 /* Interrupt with delay 256 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SAR_CFG_RXINT_505US 0x00003000 /* Interrupt with delay 505 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SAR_CFG_RXINT_742US 0x00004000 /* Interrupt with delay 742 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SAR_CFG_RAWIE 0x00000800 /* Raw Cell Queue Interrupt Enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SAR_CFG_RQFIE 0x00000400 /* RSQ Almost Full Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SAR_CFG_RSVD2 0x00000200 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SAR_CFG_CACHE 0x00000100 /* DMA on Cache Line Boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SAR_CFG_TMOIE 0x00000080 /* Timer Roll Over Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SAR_CFG_FBIE 0x00000040 /* Free Buffer Queue Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SAR_CFG_TXEN 0x00000020 /* Transmit Operation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SAR_CFG_TXINT 0x00000010 /* Transmit status Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SAR_CFG_TXUIE 0x00000008 /* Transmit underrun Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SAR_CFG_UMODE 0x00000004 /* Utopia Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SAR_CFG_TXSFI 0x00000002 /* Transmit status Full Int Enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SAR_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000 /* TX FIFO Size Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SAR_CFG_RXSTQSIZE_MASK 0x00C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SAR_CFG_CNTBL_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SAR_CFG_RXINT_MASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Status Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SAR_STAT_FRAC_3 0xF0000000 /* Fraction of Free Buffer Queue 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SAR_STAT_FRAC_2 0x0F000000 /* Fraction of Free Buffer Queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SAR_STAT_FRAC_1 0x00F00000 /* Fraction of Free Buffer Queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SAR_STAT_FRAC_0 0x000F0000 /* Fraction of Free Buffer Queue 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define SAR_STAT_TSIF 0x00008000 /* Transmit Status Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SAR_STAT_TXICP 0x00004000 /* Transmit Status Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SAR_STAT_RSVD1 0x00002000 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SAR_STAT_TSQF 0x00001000 /* Transmit Status Queue full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SAR_STAT_TMROF 0x00000800 /* Timer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SAR_STAT_PHYI 0x00000400 /* PHY device Interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Command Busy Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SAR_STAT_FBQ3A 0x00000100 /* Free Buffer Queue 3 Attention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SAR_STAT_FBQ2A 0x00000080 /* Free Buffer Queue 2 Attention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SAR_STAT_RSQF 0x00000040 /* Receive Status Queue full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SAR_STAT_EPDU 0x00000020 /* End Of PDU Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SAR_STAT_RAWCF 0x00000010 /* Raw Cell Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SAR_STAT_FBQ1A 0x00000008 /* Free Buffer Queue 1 Attention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SAR_STAT_FBQ0A 0x00000004 /* Free Buffer Queue 0 Attention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SAR_STAT_RSQAF 0x00000002 /* Receive Status Queue almost full*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define SAR_STAT_RSVD2 0x00000001 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* General Purpose Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SAR_GP_TXNCC_MASK 0xff000000 /* Transmit Negative Credit Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SAR_GP_EEDI 0x00010000 /* EEPROM Data In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SAR_GP_BIGE 0x00008000 /* Big Endian Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SAR_GP_RM_NORMAL 0x00000000 /* Normal handling of RM cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SAR_GP_RM_TO_RCQ 0x00002000 /* put RM cells into Raw Cell Queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SAR_GP_RM_RSVD 0x00004000 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SAR_GP_RM_INHIBIT 0x00006000 /* Inhibit update of Connection tab */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SAR_GP_PHY_RESET 0x00000008 /* PHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SAR_GP_EESCLK 0x00000004 /* EEPROM SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SAR_GP_EECS 0x00000002 /* EEPROM Chip Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SAR_GP_EEDO 0x00000001 /* EEPROM Data Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* SAR local SRAM layout for 128k work SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SAR_SRAM_SCD_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SAR_SRAM_TCT_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SAR_SRAM_RCT_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SAR_SRAM_TCT_128_BASE 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define SAR_SRAM_TCT_128_TOP 0x01fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define SAR_SRAM_RCT_128_BASE 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define SAR_SRAM_RCT_128_TOP 0x02fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define SAR_SRAM_FB0_128_BASE 0x03000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define SAR_SRAM_FB0_128_TOP 0x033ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SAR_SRAM_FB1_128_BASE 0x03400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SAR_SRAM_FB1_128_TOP 0x037ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define SAR_SRAM_FB2_128_BASE 0x03800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define SAR_SRAM_FB2_128_TOP 0x03bff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SAR_SRAM_FB3_128_BASE 0x03c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define SAR_SRAM_FB3_128_TOP 0x03fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define SAR_SRAM_SCD_128_BASE 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define SAR_SRAM_SCD_128_TOP 0x07fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define SAR_SRAM_TST1_128_BASE 0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define SAR_SRAM_TST1_128_TOP 0x0bfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define SAR_SRAM_TST2_128_BASE 0x0c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define SAR_SRAM_TST2_128_TOP 0x0ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define SAR_SRAM_ABRSTD_128_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define SAR_SRAM_ABRSTD_128_TOP 0x13fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define SAR_SRAM_RT_128_BASE 0x14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define SAR_SRAM_RT_128_TOP 0x15fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define SAR_SRAM_FIFO_128_BASE 0x18000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define SAR_SRAM_FIFO_128_TOP 0x1ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* SAR local SRAM layout for 32k work SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define SAR_SRAM_TCT_32_BASE 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define SAR_SRAM_TCT_32_TOP 0x00fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define SAR_SRAM_RCT_32_BASE 0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define SAR_SRAM_RCT_32_TOP 0x017ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define SAR_SRAM_FB0_32_BASE 0x01800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define SAR_SRAM_FB0_32_TOP 0x01bff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define SAR_SRAM_FB1_32_BASE 0x01c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define SAR_SRAM_FB1_32_TOP 0x01fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define SAR_SRAM_FB2_32_BASE 0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SAR_SRAM_FB2_32_TOP 0x023ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define SAR_SRAM_FB3_32_BASE 0x02400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SAR_SRAM_FB3_32_TOP 0x027ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define SAR_SRAM_SCD_32_BASE 0x02800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SAR_SRAM_SCD_32_TOP 0x03fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SAR_SRAM_TST1_32_BASE 0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define SAR_SRAM_TST1_32_TOP 0x04fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SAR_SRAM_TST2_32_BASE 0x05000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SAR_SRAM_TST2_32_TOP 0x05fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SAR_SRAM_ABRSTD_32_BASE 0x06000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SAR_SRAM_ABRSTD_32_TOP 0x067ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define SAR_SRAM_RT_32_BASE 0x06800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define SAR_SRAM_RT_32_TOP 0x06fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SAR_SRAM_FIFO_32_BASE 0x07000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define SAR_SRAM_FIFO_32_TOP 0x07fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* TSR - Transmit Status Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define SAR_TSR_TYPE_TSR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define SAR_TSR_TYPE_TBD 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define SAR_TSR_TSIF 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SAR_TSR_TAG_MASK 0x01F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* TBD - Transmit Buffer Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define SAR_TBD_EPDU 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define SAR_TBD_TSIF 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define SAR_TBD_OAM 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define SAR_TBD_AAL0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define SAR_TBD_AAL34 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define SAR_TBD_AAL5 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define SAR_TBD_GTSI 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define SAR_TBD_TAG_MASK 0x01F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define SAR_TBD_VPI_MASK 0x0FF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define SAR_TBD_VCI_MASK 0x000FFFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define SAR_TBD_VC_MASK (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define SAR_TBD_VPI_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define SAR_TBD_VCI_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* RXFD - Receive FIFO Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define SAR_RXFD_SIZE_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define SAR_RXFD_SIZE_512 0x00000000 /* 512 words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define SAR_RXFD_SIZE_1K 0x01000000 /* 1k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define SAR_RXFD_SIZE_2K 0x02000000 /* 2k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define SAR_RXFD_SIZE_4K 0x03000000 /* 4k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define SAR_RXFD_SIZE_8K 0x04000000 /* 8k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define SAR_RXFD_SIZE_16K 0x05000000 /* 16k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define SAR_RXFD_SIZE_32K 0x06000000 /* 32k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define SAR_RXFD_SIZE_64K 0x07000000 /* 64k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define SAR_RXFD_SIZE_128K 0x08000000 /* 128k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define SAR_RXFD_SIZE_256K 0x09000000 /* 256k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define SAR_RXFD_ADDR_MASK 0x001ffc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* ABRSTD - ABR + VBR Schedule Tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define SAR_ABRSTD_SIZE_MASK 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SAR_ABRSTD_SIZE_512 0x00000000 /* 512 words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SAR_ABRSTD_SIZE_1K 0x01000000 /* 1k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SAR_ABRSTD_SIZE_2K 0x02000000 /* 2k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define SAR_ABRSTD_SIZE_4K 0x03000000 /* 4k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define SAR_ABRSTD_SIZE_8K 0x04000000 /* 8k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SAR_ABRSTD_SIZE_16K 0x05000000 /* 16k words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define SAR_ABRSTD_ADDR_MASK 0x001ffc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* RCTE - Receive Connection Table Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define SAR_RCTE_IL_MASK 0xE0000000 /* inactivity limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SAR_RCTE_IC_MASK 0x1C000000 /* inactivity count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SAR_RCTE_RSVD 0x02000000 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define SAR_RCTE_LCD 0x01000000 /* last cell data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SAR_RCTE_CI_VC 0x00800000 /* EFCI in previous cell of VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SAR_RCTE_FBP_01 0x00000000 /* 1. cell->FBQ0, others->FBQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define SAR_RCTE_FBP_1 0x00200000 /* use FBQ 1 for all cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define SAR_RCTE_FBP_2 0x00400000 /* use FBQ 2 for all cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define SAR_RCTE_FBP_3 0x00600000 /* use FBQ 3 for all cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define SAR_RCTE_NZ_GFC 0x00100000 /* non zero GFC in all cell of VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define SAR_RCTE_CONNECTOPEN 0x00080000 /* VC is open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define SAR_RCTE_AAL_MASK 0x00070000 /* mask for AAL type field s.b. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define SAR_RCTE_RAWCELLINTEN 0x00008000 /* raw cell interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define SAR_RCTE_RXCONCELLADDR 0x00004000 /* RX constant cell address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define SAR_RCTE_BUFFSTAT_MASK 0x00003000 /* buffer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define SAR_RCTE_EFCI 0x00000800 /* EFCI Congestion flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define SAR_RCTE_CLP 0x00000400 /* Cell Loss Priority flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define SAR_RCTE_CRC 0x00000200 /* Received CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define SAR_RCTE_CELLCNT_MASK 0x000001FF /* cell Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SAR_RCTE_AAL0 0x00000000 /* AAL types for ALL field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define SAR_RCTE_AAL34 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define SAR_RCTE_AAL5 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define SAR_RCTE_RCQ 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define SAR_RCTE_OAM 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define TCMDQ_START 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define TCMDQ_LACR 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define TCMDQ_START_LACR 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define TCMDQ_INIT_ER 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define TCMDQ_HALT 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct idt77252_skb_prv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct scqe tbd; /* Transmit Buffer Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dma_addr_t paddr; /* DMA handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 pool; /* sb_pool handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define IDT77252_PRV_TBD(skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define IDT77252_PRV_PADDR(skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define IDT77252_PRV_POOL(skb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* PCI related items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #ifndef PCI_VENDOR_ID_IDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define PCI_VENDOR_ID_IDT 0x111D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #endif /* PCI_VENDOR_ID_IDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #ifndef PCI_DEVICE_ID_IDT_IDT77252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define PCI_DEVICE_ID_IDT_IDT77252 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #endif /* PCI_DEVICE_ID_IDT_IDT772052 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #endif /* !(_IDT77252_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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