^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*******************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2000 ATecoM GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The author may be reached at ecd@atecom.com.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/poison.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/atm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_ATM_IDT77252_USE_SUNI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "suni.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "idt77252.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "idt77252_tables.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static unsigned int vpibits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATM_IDT77252_SEND_IDLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Debug HACKs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DEBUG_MODULE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #undef HAVE_EEPROM /* does not work, yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_ATM_IDT77252_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static unsigned long debug = DBG_GENERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * SCQ Handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct scq_info *alloc_scq(struct idt77252_dev *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void free_scq(struct idt77252_dev *, struct scq_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int queue_skb(struct idt77252_dev *, struct vc_map *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct sk_buff *, int oam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void drain_scq(struct idt77252_dev *, struct vc_map *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * FBQ Handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int push_rx_skb(struct idt77252_dev *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct sk_buff *, int queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void recycle_rx_pool_skb(struct idt77252_dev *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct rx_pool *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void add_rx_skb(struct idt77252_dev *, int queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int size, unsigned int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * RSQ Handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int init_rsq(struct idt77252_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void deinit_rsq(struct idt77252_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void idt77252_rx(struct idt77252_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * TSQ handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int init_tsq(struct idt77252_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void deinit_tsq(struct idt77252_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void idt77252_tx(struct idt77252_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * ATM Interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void idt77252_dev_close(struct atm_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int idt77252_open(struct atm_vcc *vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void idt77252_close(struct atm_vcc *vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) char *page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void idt77252_softint(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct atmdev_ops idt77252_ops =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .dev_close = idt77252_dev_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .open = idt77252_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .close = idt77252_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .send = idt77252_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .send_oam = idt77252_send_oam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .phy_put = idt77252_phy_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .phy_get = idt77252_phy_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .change_qos = idt77252_change_qos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .proc_read = idt77252_proc_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .owner = THIS_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct idt77252_dev *idt77252_chain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static unsigned int idt77252_sram_write_errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* I/O and Utility Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) waitfor_idle(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) stat = readl(SAR_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) while (stat & SAR_STAT_CMDBZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) stat = readl(SAR_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) read_sram(struct idt77252_dev *card, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) value = readl(SAR_REG_DR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((idt77252_sram_write_errors == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (((addr > card->tst[0] + card->tst_size - 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (addr < card->tst[0] + card->tst_size)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ((addr > card->tst[1] + card->tst_size - 2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (addr < card->tst[1] + card->tst_size)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) card->name, addr, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(value, SAR_REG_DR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) read_utility(void *dev, unsigned long ubus_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct idt77252_dev *card = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) printk("Error: No such device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) value = readl(SAR_REG_DR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) write_utility(void *dev, unsigned long ubus_addr, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct idt77252_dev *card = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) printk("Error: No such device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel((u32) value, SAR_REG_DR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifdef HAVE_EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static u32 rdsrtab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SAR_GP_EECS | SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SAR_GP_EEDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SAR_GP_EEDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static u32 wrentab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SAR_GP_EECS | SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SAR_GP_EEDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SAR_GP_EEDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SAR_GP_EESCLK /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static u32 rdtab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SAR_GP_EECS | SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SAR_GP_EEDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SAR_GP_EEDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static u32 wrtab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SAR_GP_EECS | SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SAR_GP_EESCLK, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SAR_GP_EEDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SAR_GP_EESCLK /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static u32 clktab[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SAR_GP_EESCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) idt77252_read_gp(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) gp = readl(SAR_REG_GP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) idt77252_write_gp(struct idt77252_dev *card, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) value & SAR_GP_EEDO ? "1" : "0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel(value, SAR_REG_GP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) idt77252_eeprom_read_status(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) idt77252_write_gp(card, gp | rdsrtab[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (i = 0, j = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) byte <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) idt77252_write_gp(card, gp | clktab[j++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) idt77252_write_gp(card, gp | clktab[j++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) idt77252_write_gp(card, gp | rdtab[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) for (i = 0, j = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) idt77252_write_gp(card, gp | clktab[j++] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (offset & 1 ? SAR_GP_EEDO : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) idt77252_write_gp(card, gp | clktab[j++] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) (offset & 1 ? SAR_GP_EEDO : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) offset >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) for (i = 0, j = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) byte <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) idt77252_write_gp(card, gp | clktab[j++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) idt77252_write_gp(card, gp | clktab[j++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) idt77252_write_gp(card, gp | wrentab[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) idt77252_write_gp(card, gp | wrtab[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) for (i = 0, j = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) idt77252_write_gp(card, gp | clktab[j++] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (offset & 1 ? SAR_GP_EEDO : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) idt77252_write_gp(card, gp | clktab[j++] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (offset & 1 ? SAR_GP_EEDO : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) offset >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for (i = 0, j = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) idt77252_write_gp(card, gp | clktab[j++] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) (data & 1 ? SAR_GP_EEDO : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) idt77252_write_gp(card, gp | clktab[j++] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (data & 1 ? SAR_GP_EEDO : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) data >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) idt77252_eeprom_init(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) idt77252_write_gp(card, gp | SAR_GP_EECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #endif /* HAVE_EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #ifdef CONFIG_ATM_IDT77252_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dump_tct(struct idt77252_dev *card, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned long tct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) printk("%s: TCT %x:", card->name, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) printk(" %08x", read_sram(card, tct + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) idt77252_tx_dump(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) printk("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (i = 0; i < card->tct_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) vc = card->vcs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) vcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (vc->rx_vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) vcc = vc->rx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) else if (vc->tx_vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) vcc = vc->tx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) printk("%s: Connection %d:\n", card->name, vc->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dump_tct(card, vc->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* SCQ Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct sb_pool *pool = &card->sbpool[queue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) index = pool->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) while (pool->skb[index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) index = (index + 1) & FBQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (index == pool->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pool->skb[index] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pool->index = (index + 1) & FBQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int queue, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) handle = IDT77252_PRV_POOL(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) queue = POOL_QUEUE(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (queue > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) index = POOL_INDEX(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (index > FBQ_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) card->sbpool[queue].skb[index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct sk_buff *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) sb_pool_skb(struct idt77252_dev *card, u32 handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned int queue, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) queue = POOL_QUEUE(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (queue > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) index = POOL_INDEX(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (index > FBQ_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return card->sbpool[queue].skb[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct scq_info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) alloc_scq(struct idt77252_dev *card, int class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct scq_info *scq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!scq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) &scq->paddr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (scq->base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) kfree(scq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) scq->next = scq->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) scq->last = scq->base + (SCQ_ENTRIES - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) atomic_set(&scq->used, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) spin_lock_init(&scq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) spin_lock_init(&scq->skblock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) skb_queue_head_init(&scq->transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) skb_queue_head_init(&scq->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return scq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) free_scq(struct idt77252_dev *card, struct scq_info *scq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dma_free_coherent(&card->pcidev->dev, SCQ_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) scq->base, scq->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) while ((skb = skb_dequeue(&scq->transmit))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) vcc = ATM_SKB(skb)->vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) while ((skb = skb_dequeue(&scq->pending))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) vcc = ATM_SKB(skb)->vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) kfree(scq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct scq_info *scq = vc->scq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct scqe *tbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) atomic_inc(&scq->used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) entries = atomic_read(&scq->used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (entries > (SCQ_ENTRIES - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) atomic_dec(&scq->used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) skb_queue_tail(&scq->transmit, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) spin_lock_irqsave(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (vc->estimator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct atm_vcc *vcc = vc->tx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct sock *sk = sk_atm(vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) vc->estimator->cells += (skb->len + 47) / 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (refcount_read(&sk->sk_wmem_alloc) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (sk->sk_sndbuf >> 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 cps = vc->estimator->maxcps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) vc->estimator->cps = cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) vc->estimator->avcps = cps << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (vc->lacr < vc->init_er) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) vc->lacr = vc->init_er;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel(TCMDQ_LACR | (vc->lacr << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) vc->index, SAR_REG_TCMDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) spin_unlock_irqrestore(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tbd = &IDT77252_PRV_TBD(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) spin_lock_irqsave(&scq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) scq->next->word_1 = cpu_to_le32(tbd->word_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) SAR_TBD_TSIF | SAR_TBD_GTSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) scq->next->word_2 = cpu_to_le32(tbd->word_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) scq->next->word_3 = cpu_to_le32(tbd->word_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) scq->next->word_4 = cpu_to_le32(tbd->word_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (scq->next == scq->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) scq->next = scq->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) scq->next++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) write_sram(card, scq->scd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) scq->paddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) (u32)((unsigned long)scq->next - (unsigned long)scq->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) spin_unlock_irqrestore(&scq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) scq->trans_start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) SAR_REG_TCMDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) card->name, atomic_read(&scq->used),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) read_sram(card, scq->scd + 1), scq->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (time_after(jiffies, scq->trans_start + HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) printk("%s: Error pushing TBD for %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #ifdef CONFIG_ATM_IDT77252_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) idt77252_tx_dump(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) scq->trans_start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) drain_scq(struct idt77252_dev *card, struct vc_map *vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct scq_info *scq = vc->scq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) card->name, atomic_read(&scq->used), scq->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) skb = skb_dequeue(&scq->transmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) vcc = ATM_SKB(skb)->vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) atomic_inc(&vcc->stats->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) atomic_dec(&scq->used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) spin_lock(&scq->skblock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) while ((skb = skb_dequeue(&scq->pending))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (push_on_scq(card, vc, skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) skb_queue_head(&vc->scq->pending, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) spin_unlock(&scq->skblock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) queue_skb(struct idt77252_dev *card, struct vc_map *vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct sk_buff *skb, int oam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct scqe *tbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) int aal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 word4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (skb->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TXPRINTK("%s: Sending %d bytes of data.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) card->name, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) tbd = &IDT77252_PRV_TBD(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) vcc = ATM_SKB(skb)->vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) word4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) (skb->data[2] << 8) | (skb->data[3] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (oam) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (skb->len != 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) tbd->word_3 = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) tbd->word_4 = word4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (test_bit(VCF_RSV, &vc->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) vc = card->vcs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (test_bit(VCF_RSV, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) printk("%s: Trying to transmit on reserved VC\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) aal = vcc->qos.aal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) switch (aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case ATM_AAL34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (skb->len > 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (aal == ATM_AAL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ATM_CELL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ATM_CELL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) tbd->word_3 = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) tbd->word_4 = word4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) tbd->word_2 = IDT77252_PRV_PADDR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) tbd->word_3 = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) (vcc->vci << SAR_TBD_VCI_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case ATM_AAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case ATM_AAL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) printk("%s: Traffic type not supported.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) error = -EPROTONOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) spin_lock_irqsave(&vc->scq->skblock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) skb_queue_tail(&vc->scq->pending, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) while ((skb = skb_dequeue(&vc->scq->pending))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (push_on_scq(card, vc, skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) skb_queue_head(&vc->scq->pending, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) spin_unlock_irqrestore(&vc->scq->skblock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) errout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) for (i = 0; i < card->scd_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!card->scd2vc[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) card->scd2vc[i] = vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) vc->scd_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return card->scd_base + i * SAR_SRAM_SCD_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) write_sram(card, scq->scd, scq->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) write_sram(card, scq->scd + 1, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) write_sram(card, scq->scd + 2, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) write_sram(card, scq->scd + 3, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* RSQ Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) init_rsq(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct rsq_entry *rsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) &card->rsq.paddr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (card->rsq.base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) printk("%s: can't allocate RSQ.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) card->rsq.next = card->rsq.last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) rsqe->word_4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) SAR_REG_RSQH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) writel(card->rsq.paddr, SAR_REG_RSQB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) (unsigned long) card->rsq.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) readl(SAR_REG_RSQB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) readl(SAR_REG_RSQH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) readl(SAR_REG_RSQB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) readl(SAR_REG_RSQT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) deinit_rsq(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dma_free_coherent(&card->pcidev->dev, RSQSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) card->rsq.base, card->rsq.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct rx_pool *rpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 header, vpi, vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) stat = le32_to_cpu(rsqe->word_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (stat & SAR_RSQE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) RXPRINTK("%s: message about inactive connection.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) card->name, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) header = le32_to_cpu(rsqe->word_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) vpi = (header >> 16) & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) vci = (header >> 0) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) card->name, vpi, vci, skb, skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) printk("%s: SDU received for out-of-range vc %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) recycle_rx_skb(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) vc = card->vcs[VPCI2VC(card, vpi, vci)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!vc || !test_bit(VCF_RX, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) printk("%s: SDU received on non RX vc %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) recycle_rx_skb(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) vcc = vc->rx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) skb_end_pointer(skb) - skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if ((vcc->qos.aal == ATM_AAL0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) (vcc->qos.aal == ATM_AAL34)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct sk_buff *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) unsigned char *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 aal0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) cell = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if ((sb = dev_alloc_skb(64)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) printk("%s: Can't allocate buffers for aal0.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) atomic_add(i, &vcc->stats->rx_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!atm_charge(vcc, sb->truesize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) atomic_add(i - 1, &vcc->stats->rx_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dev_kfree_skb(sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) (vci << ATM_HDR_VCI_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) *((u32 *) sb->data) = aal0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) skb_put(sb, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) skb_put_data(sb, cell, ATM_CELL_PAYLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ATM_SKB(sb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) __net_timestamp(sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) vcc->push(vcc, sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) atomic_inc(&vcc->stats->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) cell += ATM_CELL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) recycle_rx_skb(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (vcc->qos.aal != ATM_AAL5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) card->name, vcc->qos.aal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) recycle_rx_skb(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) rpp = &vc->rcv.rx_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) __skb_queue_tail(&rpp->queue, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) rpp->len += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (stat & SAR_RSQE_EPDU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) unsigned char *l1l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) len = (l1l2[0] << 8) | l1l2[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) len = len ? len : 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) "(CDC: %08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) card->name, len, rpp->len, readl(SAR_REG_CDC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) recycle_rx_pool_skb(card, rpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) atomic_inc(&vcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (stat & SAR_RSQE_CRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) RXPRINTK("%s: AAL5 CRC error.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) recycle_rx_pool_skb(card, rpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) atomic_inc(&vcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (skb_queue_len(&rpp->queue) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct sk_buff *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) skb = dev_alloc_skb(rpp->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) RXPRINTK("%s: Can't alloc RX skb.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) recycle_rx_pool_skb(card, rpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) atomic_inc(&vcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (!atm_charge(vcc, skb->truesize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) recycle_rx_pool_skb(card, rpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) skb_queue_walk(&rpp->queue, sb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) skb_put_data(skb, sb->data, sb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) recycle_rx_pool_skb(card, rpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) skb_trim(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ATM_SKB(skb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) __net_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) vcc->push(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) atomic_inc(&vcc->stats->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) flush_rx_pool(card, rpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!atm_charge(vcc, skb->truesize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) recycle_rx_skb(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) skb_end_pointer(skb) - skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) sb_pool_remove(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) skb_trim(skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ATM_SKB(skb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) __net_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) vcc->push(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) atomic_inc(&vcc->stats->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (skb->truesize > SAR_FB_SIZE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) else if (skb->truesize > SAR_FB_SIZE_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) else if (skb->truesize > SAR_FB_SIZE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) idt77252_rx(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct rsq_entry *rsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (card->rsq.next == card->rsq.last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) rsqe = card->rsq.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) rsqe = card->rsq.next + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) RXPRINTK("%s: no entry in RSQ.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dequeue_rx(card, rsqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) rsqe->word_4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) card->rsq.next = rsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (card->rsq.next == card->rsq.last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) rsqe = card->rsq.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) rsqe = card->rsq.next + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) SAR_REG_RSQH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) idt77252_rx_raw(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct sk_buff *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) u32 head, tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct sk_buff *sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (card->raw_cell_head == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) card->raw_cell_head = sb_pool_skb(card, handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) queue = card->raw_cell_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (!queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) tail = readl(SAR_REG_RAWCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) skb_end_offset(queue) - 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) while (head != tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) unsigned int vpi, vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) u32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) header = le32_to_cpu(*(u32 *) &queue->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #ifdef CONFIG_ATM_IDT77252_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (debug & DBG_RAW_CELL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) card->name, (header >> 28) & 0x000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) (header >> 20) & 0x00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) (header >> 4) & 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) (header >> 1) & 0x0007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) (header >> 0) & 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) for (i = 16; i < 64; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) printk(" %02x", queue->data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) vc = card->vcs[VPCI2VC(card, vpi, vci)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!vc || !test_bit(VCF_RX, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) RPRINTK("%s: SDU received on non RX vc %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) vcc = vc->rx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (vcc->qos.aal != ATM_AAL0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) atomic_inc(&vcc->stats->rx_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if ((sb = dev_alloc_skb(64)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) printk("%s: Can't allocate buffers for AAL0.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) atomic_inc(&vcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!atm_charge(vcc, sb->truesize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev_kfree_skb(sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) goto drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) *((u32 *) sb->data) = header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) skb_put(sb, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) skb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ATM_SKB(sb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) __net_timestamp(sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) vcc->push(vcc, sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) atomic_inc(&vcc->stats->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) drop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) skb_pull(queue, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) head = IDT77252_PRV_PADDR(queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) + (queue->data - queue->head - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (queue->len < 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct sk_buff *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) head = le32_to_cpu(*(u32 *) &queue->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) handle = le32_to_cpu(*(u32 *) &queue->data[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) next = sb_pool_skb(card, handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) recycle_rx_skb(card, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) card->raw_cell_head = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) queue = card->raw_cell_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dma_sync_single_for_cpu(&card->pcidev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) IDT77252_PRV_PADDR(queue),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) (skb_end_pointer(queue) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) queue->data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) card->raw_cell_head = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) printk("%s: raw cell queue overrun\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* TSQ Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) init_tsq(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct tsq_entry *tsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) &card->tsq.paddr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (card->tsq.base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) printk("%s: can't allocate TSQ.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) card->tsq.next = card->tsq.last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) writel(card->tsq.paddr, SAR_REG_TSQB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) SAR_REG_TSQH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) deinit_tsq(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dma_free_coherent(&card->pcidev->dev, TSQSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) card->tsq.base, card->tsq.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) idt77252_tx(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct tsq_entry *tsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) unsigned int vpi, vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u32 conn, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (card->tsq.next == card->tsq.last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) tsqe = card->tsq.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) tsqe = card->tsq.next + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) card->tsq.base, card->tsq.next, card->tsq.last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) readl(SAR_REG_TSQB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) readl(SAR_REG_TSQT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) readl(SAR_REG_TSQH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) stat = le32_to_cpu(tsqe->word_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (stat & SAR_TSQE_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) le32_to_cpu(tsqe->word_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) le32_to_cpu(tsqe->word_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) switch (stat & SAR_TSQE_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case SAR_TSQE_TYPE_TIMER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) TXPRINTK("%s: Timer RollOver detected.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) case SAR_TSQE_TYPE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) conn = le32_to_cpu(tsqe->word_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (SAR_TSQE_TAG(stat) == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #ifdef NOTDEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) printk("%s: Connection %d halted.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) le32_to_cpu(tsqe->word_1) & 0x1fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) vc = card->vcs[conn & 0x1fff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (!vc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) printk("%s: could not find VC from conn %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) card->name, conn & 0x1fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) printk("%s: Connection %d IDLE.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) card->name, vc->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) set_bit(VCF_IDLE, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case SAR_TSQE_TYPE_TSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) conn = le32_to_cpu(tsqe->word_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) vc = card->vcs[conn & 0x1fff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (!vc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) printk("%s: no VC at index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) le32_to_cpu(tsqe->word_1) & 0x1fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) drain_scq(card, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) case SAR_TSQE_TYPE_TBD_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) conn = le32_to_cpu(tsqe->word_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (vpi >= (1 << card->vpibits) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) vci >= (1 << card->vcibits)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) printk("%s: TBD complete: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) "out of range VPI.VCI %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) vc = card->vcs[VPCI2VC(card, vpi, vci)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (!vc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) printk("%s: TBD complete: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) "no VC at VPI.VCI %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) drain_scq(card, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) card->tsq.next = tsqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (card->tsq.next == card->tsq.last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) tsqe = card->tsq.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) tsqe = card->tsq.next + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) card->tsq.base, card->tsq.next, card->tsq.last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) stat = le32_to_cpu(tsqe->word_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) } while (!(stat & SAR_TSQE_INVALID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) SAR_REG_TSQH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) card->index, readl(SAR_REG_TSQH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) readl(SAR_REG_TSQT), card->tsq.next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) tst_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) struct idt77252_dev *card = from_timer(card, t, tst_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) unsigned long base, idle, jump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) u32 pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) int e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) spin_lock_irqsave(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) base = card->tst[card->tst_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) idle = card->tst[card->tst_index ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) jump = base + card->tst_size - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) pc = readl(SAR_REG_NOW) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if ((pc ^ idle) & ~(card->tst_size - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) mod_timer(&card->tst_timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) clear_bit(TST_SWITCH_WAIT, &card->tst_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) card->tst_index ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) base = card->tst[card->tst_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) idle = card->tst[card->tst_index ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) for (e = 0; e < card->tst_size - 2; e++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) write_sram(card, idle + e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) card->soft_tst[e].tste & TSTE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) for (e = 0; e < card->tst_size - 2; e++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) write_sram(card, idle + e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) card->soft_tst[e].tste & TSTE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) jump = base + card->tst_size - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) write_sram(card, jump, TSTE_OPC_NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) set_bit(TST_SWITCH_WAIT, &card->tst_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) mod_timer(&card->tst_timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) spin_unlock_irqrestore(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) int n, unsigned int opc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) unsigned long cl, avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) unsigned long idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int e, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) avail = card->tst_size - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) for (e = 0; e < avail; e++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (card->soft_tst[e].vc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (e >= avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) printk("%s: No free TST entries found\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) NPRINTK("%s: conn %d: first TST entry at %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) card->name, vc ? vc->index : -1, e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) r = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) cl = avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) data = opc & TSTE_OPC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (vc && (opc != TSTE_OPC_NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) data = opc | vc->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) idle = card->tst[card->tst_index ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * Fill Soft TST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) while (r > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) card->soft_tst[e].vc = vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) card->soft_tst[e].vc = (void *)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) card->soft_tst[e].tste = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (timer_pending(&card->tst_timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) write_sram(card, idle + e, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) cl -= card->tst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) r--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (++e == avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) e = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) cl += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) spin_lock_irqsave(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) res = __fill_tst(card, vc, n, opc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) set_bit(TST_SWITCH_PENDING, &card->tst_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (!timer_pending(&card->tst_timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) mod_timer(&card->tst_timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) spin_unlock_irqrestore(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) unsigned long idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) int e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) idle = card->tst[card->tst_index ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) for (e = 0; e < card->tst_size - 2; e++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (card->soft_tst[e].vc == vc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) card->soft_tst[e].vc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) card->soft_tst[e].tste = TSTE_OPC_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (timer_pending(&card->tst_timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) write_sram(card, idle + e, TSTE_OPC_VAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) clear_tst(struct idt77252_dev *card, struct vc_map *vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) spin_lock_irqsave(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) res = __clear_tst(card, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) set_bit(TST_SWITCH_PENDING, &card->tst_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (!timer_pending(&card->tst_timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) mod_timer(&card->tst_timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) spin_unlock_irqrestore(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) change_tst(struct idt77252_dev *card, struct vc_map *vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) int n, unsigned int opc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) spin_lock_irqsave(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) __clear_tst(card, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) res = __fill_tst(card, vc, n, opc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) set_bit(TST_SWITCH_PENDING, &card->tst_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (!timer_pending(&card->tst_timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) mod_timer(&card->tst_timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) spin_unlock_irqrestore(&card->tst_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) set_tct(struct idt77252_dev *card, struct vc_map *vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) unsigned long tct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) switch (vc->class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) case SCHED_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) card->name, tct, vc->scq->scd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) write_sram(card, tct + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) write_sram(card, tct + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) write_sram(card, tct + 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) write_sram(card, tct + 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) write_sram(card, tct + 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) write_sram(card, tct + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) write_sram(card, tct + 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) case SCHED_UBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) card->name, tct, vc->scq->scd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) write_sram(card, tct + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) write_sram(card, tct + 2, TCT_TSIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) write_sram(card, tct + 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) write_sram(card, tct + 5, vc->init_er);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) write_sram(card, tct + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) write_sram(card, tct + 7, TCT_FLAG_UBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case SCHED_VBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) case SCHED_ABR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* FBQ Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) idt77252_fbq_level(struct idt77252_dev *card, int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) idt77252_fbq_full(struct idt77252_dev *card, int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) skb->data = skb->head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) skb_reset_tail_pointer(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) skb->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) skb_reserve(skb, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) switch (queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) skb_put(skb, SAR_FB_SIZE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) skb_put(skb, SAR_FB_SIZE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) skb_put(skb, SAR_FB_SIZE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) skb_put(skb, SAR_FB_SIZE_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (idt77252_fbq_full(card, queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) handle = IDT77252_PRV_POOL(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) addr = IDT77252_PRV_PADDR(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) writel(handle, card->fbq[queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) writel(addr, card->fbq[queue]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) add_rx_skb(struct idt77252_dev *card, int queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) unsigned int size, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) skb = dev_alloc_skb(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (sb_pool_add(card, skb, queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) printk("%s: SB POOL full\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) goto outfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) paddr = dma_map_single(&card->pcidev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) skb_end_pointer(skb) - skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) IDT77252_PRV_PADDR(skb) = paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (push_rx_skb(card, skb, queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) printk("%s: FB QUEUE full\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) goto outunmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) outunmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) handle = IDT77252_PRV_POOL(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) outfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) u32 handle = IDT77252_PRV_POOL(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) skb_end_pointer(skb) - skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) err = push_rx_skb(card, skb, POOL_QUEUE(handle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) skb_end_pointer(skb) - skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) sb_pool_remove(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) skb_queue_head_init(&rpp->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) rpp->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct sk_buff *skb, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) skb_queue_walk_safe(&rpp->queue, skb, tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) recycle_rx_skb(card, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) flush_rx_pool(card, rpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* ATM Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct atm_dev *dev = vcc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct vc_map *vc = vcc->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (vc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) printk("%s: NULL connection in send().\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (!test_bit(VCF_TX, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) switch (vcc->qos.aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) case ATM_AAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (skb_shinfo(skb)->nr_frags != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) printk("%s: No scatter-gather yet.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) ATM_SKB(skb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) err = queue_skb(card, vc, skb, oam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return idt77252_send_skb(vcc, skb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct atm_dev *dev = vcc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) skb = dev_alloc_skb(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) printk("%s: Out of memory in send_oam().\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) skb_put_data(skb, cell, 52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) return idt77252_send_skb(vcc, skb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static __inline__ unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) idt77252_fls(unsigned int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) int r = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (x == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (x & 0xffff0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) x >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) r += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (x & 0xff00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) x >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) r += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (x & 0xf0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) x >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) r += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (x & 0xc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) x >>= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) r += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (x & 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) r += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) idt77252_int_to_atmfp(unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) u16 m, e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) e = idt77252_fls(rate) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (e < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) m = (rate - (1 << e)) << (9 - e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) else if (e == 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) m = (rate - (1 << e));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) else /* e > 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) m = (rate - (1 << e)) >> (e - 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return 0x4000 | (e << 9) | m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) u16 afp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (pcr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return rate_to_log[(afp >> 5) & 0x1ff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return rate_to_log[((afp >> 5) + 1) & 0x1ff];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) idt77252_est_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) struct rate_estimator *est = from_timer(est, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) struct vc_map *vc = est->vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) struct idt77252_dev *card = vc->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) u32 rate, cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) u64 ncells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) u8 lacr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) spin_lock_irqsave(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (!vc->estimator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ncells = est->cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) est->last_cells = ncells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) est->cps = (est->avcps + 0x1f) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) cps = est->cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (cps < (est->maxcps >> 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) cps = est->maxcps >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) lacr = idt77252_rate_logindex(card, cps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (lacr > vc->max_er)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) lacr = vc->max_er;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (lacr != vc->lacr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) vc->lacr = lacr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) est->timer.expires = jiffies + ((HZ / 4) << est->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) add_timer(&est->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) spin_unlock_irqrestore(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static struct rate_estimator *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) idt77252_init_est(struct vc_map *vc, int pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) struct rate_estimator *est;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (!est)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) est->maxcps = pcr < 0 ? -pcr : pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) est->cps = est->maxcps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) est->avcps = est->cps << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) est->vc = vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) est->interval = 2; /* XXX: make this configurable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) est->ewma_log = 2; /* XXX: make this configurable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) timer_setup(&est->timer, idt77252_est_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) mod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) return est;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct atm_vcc *vcc, struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) int tst_free, tst_used, tst_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) unsigned long tmpl, modl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) int tcr, tcra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if ((qos->txtp.max_pcr == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) printk("%s: trying to open a CBR VC with cell rate = 0\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) tst_used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) tst_free = card->tst_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (test_bit(VCF_TX, &vc->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) tst_used = vc->ntste;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) tst_free += tst_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) tcr = atm_pcr_goal(&qos->txtp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) tcra = tcr >= 0 ? tcr : -tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) modl = tmpl % (unsigned long)card->utopia_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) tst_entries = (int) (tmpl / card->utopia_pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (tcr > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (modl > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) tst_entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) } else if (tcr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) tst_entries = tst_free - SAR_TST_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) if (tst_entries <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) printk("%s: no CBR bandwidth free.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return -ENOSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (tst_entries == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) printk("%s: selected CBR bandwidth < granularity.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) printk("%s: not enough CBR bandwidth free.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return -ENOSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) vc->ntste = tst_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) card->tst_free = tst_free - tst_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (test_bit(VCF_TX, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (tst_used == tst_entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) OPRINTK("%s: modify %d -> %d entries in TST.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) card->name, tst_used, tst_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct atm_vcc *vcc, struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct rate_estimator *est = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) int tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) spin_lock_irqsave(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (vc->estimator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) est = vc->estimator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) vc->estimator = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) spin_unlock_irqrestore(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (est) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) del_timer_sync(&est->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) kfree(est);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) tcr = atm_pcr_goal(&qos->txtp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (tcr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) tcr = card->link_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) vc->estimator = idt77252_init_est(vc, tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) vc->class = SCHED_UBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) vc->init_er = idt77252_rate_logindex(card, tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) vc->lacr = vc->init_er;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (tcr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) vc->max_er = vc->init_er;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) vc->max_er = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) struct atm_vcc *vcc, struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (test_bit(VCF_TX, &vc->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) switch (qos->txtp.traffic_class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) case ATM_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) vc->class = SCHED_CBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) case ATM_UBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) vc->class = SCHED_UBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) case ATM_VBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) case ATM_ABR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return -EPROTONOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) vc->scq = alloc_scq(card, vc->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (!vc->scq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) printk("%s: can't get SCQ.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) vc->scq->scd = get_free_scd(card, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (vc->scq->scd == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) printk("%s: no SCD available.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) free_scq(card, vc->scq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) fill_scd(card, vc->scq, vc->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (set_tct(card, vc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) printk("%s: class %d not supported.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) card->name, qos->txtp.traffic_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) card->scd2vc[vc->scd_index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) free_scq(card, vc->scq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) return -EPROTONOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) switch (vc->class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) case SCHED_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) error = idt77252_init_cbr(card, vc, vcc, qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) card->scd2vc[vc->scd_index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) free_scq(card, vc->scq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) clear_bit(VCF_IDLE, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) case SCHED_UBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) error = idt77252_init_ubr(card, vc, vcc, qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) card->scd2vc[vc->scd_index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) free_scq(card, vc->scq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) set_bit(VCF_IDLE, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) vc->tx_vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) set_bit(VCF_TX, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) struct atm_vcc *vcc, struct atm_qos *qos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) u32 rcte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) if (test_bit(VCF_RX, &vc->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) vc->rx_vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) set_bit(VCF_RX, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if ((vcc->vci == 3) || (vcc->vci == 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) flush_rx_pool(card, &vc->rcv.rx_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) rcte |= SAR_RCTE_CONNECTOPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) rcte |= SAR_RCTE_RAWCELLINTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) switch (qos->aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) rcte |= SAR_RCTE_RCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) case ATM_AAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) case ATM_AAL34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) rcte |= SAR_RCTE_AAL34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) rcte |= SAR_RCTE_AAL5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) rcte |= SAR_RCTE_RCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) if (qos->aal != ATM_AAL5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) rcte |= SAR_RCTE_FBP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) rcte |= SAR_RCTE_FBP_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) rcte |= SAR_RCTE_FBP_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) rcte |= SAR_RCTE_FBP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) rcte |= SAR_RCTE_FBP_01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) addr = card->rct_base + (vc->index << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) write_sram(card, addr, rcte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) idt77252_open(struct atm_vcc *vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) struct atm_dev *dev = vcc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) unsigned int inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) int vci = vcc->vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) short vpi = vcc->vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (vpi >= (1 << card->vpibits)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) printk("%s: unsupported VPI: %d\n", card->name, vpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) if (vci >= (1 << card->vcibits)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) printk("%s: unsupported VCI: %d\n", card->name, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) set_bit(ATM_VF_ADDR, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) mutex_lock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) switch (vcc->qos.aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) case ATM_AAL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) return -EPROTONOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) index = VPCI2VC(card, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (!card->vcs[index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (!card->vcs[index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) printk("%s: can't alloc vc in open()\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) card->vcs[index]->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) card->vcs[index]->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) spin_lock_init(&card->vcs[index]->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) vc = card->vcs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) vcc->dev_data = vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) card->name, vc->index, vcc->vpi, vcc->vci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) vcc->qos.rxtp.max_sdu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) if (vcc->qos.txtp.traffic_class != ATM_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) test_bit(VCF_TX, &vc->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) inuse = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) test_bit(VCF_RX, &vc->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) inuse += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (inuse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) printk("%s: %s vci already in use.\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) return -EADDRINUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (vcc->qos.txtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) set_bit(ATM_VF_READY, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) idt77252_close(struct atm_vcc *vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) struct atm_dev *dev = vcc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) struct vc_map *vc = vcc->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) mutex_lock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) card->name, vc->index, vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) clear_bit(ATM_VF_READY, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) spin_lock_irqsave(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) clear_bit(VCF_RX, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) vc->rx_vcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) spin_unlock_irqrestore(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) if ((vcc->vci == 3) || (vcc->vci == 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) DPRINTK("%s: closing a VC with pending rx buffers.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (vcc->qos.txtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) spin_lock_irqsave(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) clear_bit(VCF_TX, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) clear_bit(VCF_IDLE, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) clear_bit(VCF_RSV, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) vc->tx_vcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (vc->estimator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) del_timer(&vc->estimator->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) kfree(vc->estimator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) vc->estimator = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) spin_unlock_irqrestore(&vc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) timeout = 5 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) while (atomic_read(&vc->scq->used) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) timeout = msleep_interruptible(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) pr_warn("%s: SCQ drain timeout: %u used\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) card->name, atomic_read(&vc->scq->used));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) clear_scd(card, vc->scq, vc->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) if (vc->class == SCHED_CBR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) clear_tst(card, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) card->tst_free += vc->ntste;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) vc->ntste = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) card->scd2vc[vc->scd_index] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) free_scq(card, vc->scq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) struct atm_dev *dev = vcc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) struct vc_map *vc = vcc->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) mutex_lock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if (qos->txtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) if (!test_bit(VCF_TX, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) error = idt77252_init_tx(card, vc, vcc, qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) switch (qos->txtp.traffic_class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) case ATM_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) error = idt77252_init_cbr(card, vc, vcc, qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) case ATM_UBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) error = idt77252_init_ubr(card, vc, vcc, qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) if (!test_bit(VCF_IDLE, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) writel(TCMDQ_LACR | (vc->lacr << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) vc->index, SAR_REG_TCMDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) case ATM_VBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) case ATM_ABR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) error = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) if ((qos->rxtp.traffic_class != ATM_NONE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) !test_bit(VCF_RX, &vc->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) error = idt77252_init_rx(card, vc, vcc, qos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) set_bit(ATM_VF_HASQOS, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) mutex_unlock(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) int i, left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) left = (int) *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) return sprintf(page, "IDT77252 Interrupts:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return sprintf(page, "IDT77252 Transmit Connection Table:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) for (i = 0; i < card->tct_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) unsigned long tct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) vc = card->vcs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) if (!vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) vcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) if (vc->tx_vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) vcc = vc->tx_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) if (!vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) p = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) p += sprintf(p, " %08x", read_sram(card, tct + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) p += sprintf(p, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) return p - page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) /* Interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) idt77252_collect_stat(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) (void) readl(SAR_REG_CDC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) (void) readl(SAR_REG_VPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) (void) readl(SAR_REG_ICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) idt77252_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) struct idt77252_dev *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) stat = readl(SAR_REG_STAT) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) if (!stat) /* no interrupt for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) printk("%s: Re-entering irq_handler()\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) writel(stat, SAR_REG_STAT); /* reset interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) INTPRINTK("%s: TSIF\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) card->irqstat[15]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) idt77252_tx(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) INTPRINTK("%s: TXICP\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) card->irqstat[14]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) #ifdef CONFIG_ATM_IDT77252_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) idt77252_tx_dump(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) INTPRINTK("%s: TSQF\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) card->irqstat[12]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) idt77252_tx(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (stat & SAR_STAT_TMROF) { /* Timer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) INTPRINTK("%s: TMROF\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) card->irqstat[11]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) idt77252_collect_stat(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) INTPRINTK("%s: EPDU\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) card->irqstat[5]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) idt77252_rx(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) INTPRINTK("%s: RSQAF\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) card->irqstat[1]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) idt77252_rx(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) if (stat & SAR_STAT_RSQF) { /* RSQ is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) INTPRINTK("%s: RSQF\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) card->irqstat[6]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) idt77252_rx(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) INTPRINTK("%s: RAWCF\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) card->irqstat[4]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) idt77252_rx_raw(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) INTPRINTK("%s: PHYI", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) card->irqstat[10]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) if (card->atmdev->phy && card->atmdev->phy->interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) card->atmdev->phy->interrupt(card->atmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (stat & SAR_STAT_FBQ0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) card->irqstat[2]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) if (stat & SAR_STAT_FBQ1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) card->irqstat[3]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) if (stat & SAR_STAT_FBQ2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) card->irqstat[7]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) if (stat & SAR_STAT_FBQ3A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) card->irqstat[8]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) schedule_work(&card->tqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) idt77252_softint(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) struct idt77252_dev *card =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) container_of(work, struct idt77252_dev, tqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) for (done = 1; ; done = 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) stat = readl(SAR_REG_STAT) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) stat >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) stat >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) stat >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) open_card_oam(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) int vpi, vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) u32 rcte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) for (vci = 3; vci < 5; vci++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) index = VPCI2VC(card, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) if (!vc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) printk("%s: can't alloc vc\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) vc->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) card->vcs[index] = vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) flush_rx_pool(card, &vc->rcv.rx_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) rcte = SAR_RCTE_CONNECTOPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) SAR_RCTE_RAWCELLINTEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) SAR_RCTE_RCQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) SAR_RCTE_FBP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) addr = card->rct_base + (vc->index << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) write_sram(card, addr, rcte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) close_card_oam(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) int vpi, vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) for (vci = 3; vci < 5; vci++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) index = VPCI2VC(card, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) vc = card->vcs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) spin_lock_irqsave(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) waitfor_idle(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) spin_unlock_irqrestore(&card->cmd_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) DPRINTK("%s: closing a VC "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) "with pending rx buffers.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) open_card_ubr0(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) struct vc_map *vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) if (!vc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) printk("%s: can't alloc vc\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) card->vcs[0] = vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) vc->class = SCHED_UBR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) vc->scq = alloc_scq(card, vc->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if (!vc->scq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) printk("%s: can't get SCQ.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) card->scd2vc[0] = vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) vc->scd_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) vc->scq->scd = card->scd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) fill_scd(card, vc->scq, vc->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) write_sram(card, card->tct_base + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) write_sram(card, card->tct_base + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) write_sram(card, card->tct_base + 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) write_sram(card, card->tct_base + 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) write_sram(card, card->tct_base + 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) write_sram(card, card->tct_base + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) clear_bit(VCF_IDLE, &vc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) idt77252_dev_open(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) printk("%s: SAR not yet initialized.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) conf = SAR_CFG_RXPTH| /* enable receive path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) SAR_RX_DELAY | /* interrupt on complete PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) SAR_CFG_RAWIE | /* interrupt enable on raw cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) SAR_CFG_TMOIE | /* interrupt on timer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) SAR_CFG_FBIE | /* interrupt on low free buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) SAR_CFG_TXEN | /* transmit operation enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) SAR_CFG_TXINT | /* interrupt on transmit status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) SAR_CFG_TXUIE | /* interrupt on transmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) SAR_CFG_PHYIE /* enable PHY interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) #ifdef CONFIG_ATM_IDT77252_RCV_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) /* Test RAW cell receive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) conf |= SAR_CFG_VPECA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) if (open_card_oam(card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) printk("%s: Error initializing OAM.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) if (open_card_ubr0(card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) printk("%s: Error initializing UBR0.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) static void idt77252_dev_close(struct atm_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) close_card_oam(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) conf = SAR_CFG_RXPTH | /* enable receive path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) SAR_RX_DELAY | /* interrupt on complete PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) SAR_CFG_RAWIE | /* interrupt enable on raw cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) SAR_CFG_TMOIE | /* interrupt on timer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) SAR_CFG_FBIE | /* interrupt on low free buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) SAR_CFG_TXEN | /* transmit operation enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) SAR_CFG_TXINT | /* interrupt on transmit status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) SAR_CFG_TXUIE | /* interrupt on xmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) SAR_CFG_TXSFI /* interrupt on TSQ almost full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) /* Initialisation and Deinitialization of IDT77252 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) deinit_card(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) printk("%s: SAR not yet initialized.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) DIPRINTK("idt77252: deinitialize card %u\n", card->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) writel(0, SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) if (card->atmdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) atm_dev_deregister(card->atmdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) for (j = 0; j < FBQ_SIZE; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) skb = card->sbpool[i].skb[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) dma_unmap_single(&card->pcidev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) IDT77252_PRV_PADDR(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) (skb_end_pointer(skb) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) skb->data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) card->sbpool[i].skb[j] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) vfree(card->soft_tst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) vfree(card->scd2vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) vfree(card->vcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) if (card->raw_cell_hnd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) card->raw_cell_hnd, card->raw_cell_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (card->rsq.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) DIPRINTK("%s: Release RSQ ...\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) deinit_rsq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) if (card->tsq.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) DIPRINTK("%s: Release TSQ ...\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) deinit_tsq(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) DIPRINTK("idt77252: Release IRQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) free_irq(card->pcidev->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) if (card->fbq[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) iounmap(card->fbq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) if (card->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) iounmap(card->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) clear_bit(IDT77252_BIT_INIT, &card->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) DIPRINTK("%s: Card deinitialized.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) static void init_sram(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) for (i = 0; i < card->sramsize; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) write_sram(card, (i >> 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) /* set SRAM layout for THIS card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) if (card->sramsize == (512 * 1024)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) card->tct_base = SAR_SRAM_TCT_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) / SAR_SRAM_TCT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) card->rct_base = SAR_SRAM_RCT_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) / SAR_SRAM_RCT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) card->rt_base = SAR_SRAM_RT_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) card->scd_base = SAR_SRAM_SCD_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) / SAR_SRAM_SCD_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) card->tst[0] = SAR_SRAM_TST1_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) card->tst[1] = SAR_SRAM_TST2_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) card->abrst_size = SAR_ABRSTD_SIZE_8K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) card->fifo_base = SAR_SRAM_FIFO_128_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) card->fifo_size = SAR_RXFD_SIZE_32K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) card->tct_base = SAR_SRAM_TCT_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) / SAR_SRAM_TCT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) card->rct_base = SAR_SRAM_RCT_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) / SAR_SRAM_RCT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) card->rt_base = SAR_SRAM_RT_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) card->scd_base = SAR_SRAM_SCD_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) / SAR_SRAM_SCD_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) card->tst[0] = SAR_SRAM_TST1_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) card->tst[1] = SAR_SRAM_TST2_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) card->abrst_size = SAR_ABRSTD_SIZE_1K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) card->fifo_base = SAR_SRAM_FIFO_32_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) card->fifo_size = SAR_RXFD_SIZE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /* Initialize TCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) for (i = 0; i < card->tct_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) /* Initialize RCT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) for (i = 0; i < card->rct_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) (u32) SAR_RCTE_RAWCELLINTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) (u32) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) (u32) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) (u32) 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) /* Initialize rate table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) for (i = 0; i < 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) write_sram(card, card->rt_base + i, log_to_rate[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) for (i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) tmp = rate_to_log[(i << 2) + 0] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) tmp |= rate_to_log[(i << 2) + 1] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) tmp |= rate_to_log[(i << 2) + 2] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) tmp |= rate_to_log[(i << 2) + 3] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) write_sram(card, card->rt_base + 256 + i, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) #if 0 /* Fill RDF and AIR tables. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) for (i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) tmp = RDF[0][(i << 1) + 0] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) tmp |= RDF[0][(i << 1) + 1] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) write_sram(card, card->rt_base + 512 + i, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) for (i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) tmp = AIR[0][(i << 1) + 0] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) tmp |= AIR[0][(i << 1) + 1] << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) write_sram(card, card->rt_base + 640 + i, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) IPRINTK("%s: initialize rate table ...\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) writel(card->rt_base << 2, SAR_REG_RTBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) /* Initialize TSTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) IPRINTK("%s: initialize TST ...\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) card->tst_free = card->tst_size - 2; /* last two are jumps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) write_sram(card, i, TSTE_OPC_VAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) idt77252_sram_write_errors = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) idt77252_sram_write_errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) write_sram(card, i, TSTE_OPC_VAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) idt77252_sram_write_errors = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) idt77252_sram_write_errors = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) card->tst_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) writel(card->tst[0] << 2, SAR_REG_TSTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /* Initialize ABRSTD and Receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) IPRINTK("%s: initialize ABRSTD ...\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) writel(card->abrst_size | (card->abrst_base << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) SAR_REG_ABRSTD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) IPRINTK("%s: initialize receive fifo ...\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) writel(card->fifo_size | (card->fifo_base << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) SAR_REG_RXFD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) IPRINTK("%s: SRAM initialization complete.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) static int init_card(struct atm_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) struct idt77252_dev *card = dev->dev_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) struct pci_dev *pcidev = card->pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) unsigned long tmpl, modl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) unsigned int linkrate, rsvdcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) unsigned int tst_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) struct net_device *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) char tname[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) u_char pci_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) int i, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) printk("Error: SAR already initialized.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) /* P C I C O N F I G U R A T I O N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) /* Set PCI Retry-Timeout and TRDY timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) IPRINTK("%s: Checking PCI retries.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) printk("%s: can't read PCI retry timeout.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) if (pci_byte != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) card->name, pci_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) printk("%s: can't set PCI retry timeout.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) IPRINTK("%s: Checking PCI TRDY.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) printk("%s: can't read PCI TRDY timeout.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) if (pci_byte != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) card->name, pci_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) printk("%s: can't set PCI TRDY timeout.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) /* Reset Timer register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) printk("%s: resetting timer overflow.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) writel(SAR_STAT_TMROF, SAR_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) IPRINTK("%s: Request IRQ ... ", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) card->name, card) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) printk("%s: can't allocate IRQ.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) IPRINTK("got %d.\n", pcidev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) /* C H E C K A N D I N I T S R A M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) IPRINTK("%s: Initializing SRAM\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) /* preset size of connecton table, so that init_sram() knows about it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) #ifndef ATM_IDT77252_SEND_IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) SAR_CFG_NO_IDLE | /* Do not send idle cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) if (card->sramsize == (512 * 1024))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) conf |= SAR_CFG_CNTBL_1k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) conf |= SAR_CFG_CNTBL_512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) switch (vpibits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) conf |= SAR_CFG_VPVCS_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) conf |= SAR_CFG_VPVCS_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) conf |= SAR_CFG_VPVCS_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) conf |= SAR_CFG_VPVCS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) init_sram(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) /********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /* Initialize TSQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) if (0 != init_tsq(card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) /* Initialize RSQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) if (0 != init_rsq(card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) card->vpibits = vpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) if (card->sramsize == (512 * 1024)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) card->vcibits = 10 - card->vpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) card->vcibits = 9 - card->vpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) card->vcimask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) for (k = 0, i = 1; k < card->vcibits; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) card->vcimask |= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) i <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) writel(0, SAR_REG_VPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) /* Little Endian Order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) writel(0, SAR_REG_GP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) /* Initialize RAW Cell Handle Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) card->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) 2 * sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) &card->raw_cell_paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) if (!card->raw_cell_hnd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) printk("%s: memory allocation failure.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) writel(card->raw_cell_paddr, SAR_REG_RAWHND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) card->raw_cell_hnd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) size = sizeof(struct vc_map *) * card->tct_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) card->vcs = vzalloc(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) if (!card->vcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) printk("%s: memory allocation failure.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) size = sizeof(struct vc_map *) * card->scd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) card->name, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) card->scd2vc = vzalloc(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) if (!card->scd2vc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) printk("%s: memory allocation failure.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) size = sizeof(struct tst_info) * (card->tst_size - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) card->name, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) card->soft_tst = vmalloc(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) if (!card->soft_tst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) printk("%s: memory allocation failure.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) for (i = 0; i < card->tst_size - 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) card->soft_tst[i].tste = TSTE_OPC_VAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) card->soft_tst[i].vc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) if (dev->phy == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) printk("%s: No LT device defined.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) if (dev->phy->ioctl == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) printk("%s: LT had no IOCTL function defined.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) #ifdef CONFIG_ATM_IDT77252_USE_SUNI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) * this is a jhs hack to get around special functionality in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * phy driver for the atecom hardware; the functionality doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) * exist in the linux atm suni driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * it isn't the right way to do things, but as the guy from NIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) * said, talking about their measurement of the fine structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) * constant, "it's good enough for government work."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) linkrate = 149760000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) card->link_pcr = (linkrate / 8 / 53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) card->name, linkrate, card->link_pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) #ifdef ATM_IDT77252_SEND_IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) card->utopia_pcr = card->link_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) card->utopia_pcr = (160000000 / 8 / 54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) rsvdcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) if (card->utopia_pcr > card->link_pcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) rsvdcr = card->utopia_pcr - card->link_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) modl = tmpl % (unsigned long)card->utopia_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) if (modl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) tst_entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) card->tst_free -= tst_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) #ifdef HAVE_EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) idt77252_eeprom_init(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) printk("%s: EEPROM: %02x:", card->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) idt77252_eeprom_read_status(card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) for (i = 0; i < 0x80; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) printk(" %02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) idt77252_eeprom_read_byte(card, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) #endif /* HAVE_EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * XXX: <hack>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) sprintf(tname, "eth%d", card->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) memcpy(card->atmdev->esi, tmp->dev_addr, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) dev_put(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) printk("%s: ESI %pM\n", card->name, card->atmdev->esi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) * XXX: </hack>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) /* Set Maximum Deficit Count for now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) writel(0xffff, SAR_REG_MDFCT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) set_bit(IDT77252_BIT_INIT, &card->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) /* Probing of IDT77252 ABR SAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) static int idt77252_preset(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) u16 pci_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) /* P C I C O N F I G U R A T I O N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) printk("%s: can't read PCI_COMMAND.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) if (!(pci_command & PCI_COMMAND_IO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) printk("%s: PCI_COMMAND: %04x (???)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) card->name, pci_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) return (-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) printk("%s: can't write PCI_COMMAND.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) /* G E N E R I C R E S E T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) /* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) writel(SAR_CFG_SWRST, SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) writel(0, SAR_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) IPRINTK("%s: Software resetted.\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) static unsigned long probe_sram(struct idt77252_dev *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) u32 data, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) writel(0, SAR_REG_DR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) writel(ATM_POISON, SAR_REG_DR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) data = readl(SAR_REG_DR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) if (data != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) return addr * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) static int idt77252_init_one(struct pci_dev *pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) static struct idt77252_dev **last = &idt77252_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) static int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) unsigned long membase, srambase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) struct idt77252_dev *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) struct atm_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) if ((err = pci_enable_device(pcidev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) goto err_out_disable_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) if (!card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) printk("idt77252-%d: can't allocate private data\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) goto err_out_disable_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) card->revision = pcidev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) card->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) card->pcidev = pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) sprintf(card->name, "idt77252-%d", card->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) INIT_WORK(&card->tqueue, idt77252_softint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) membase = pci_resource_start(pcidev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) srambase = pci_resource_start(pcidev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) mutex_init(&card->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) spin_lock_init(&card->cmd_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) spin_lock_init(&card->tst_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) timer_setup(&card->tst_timer, tst_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) /* Do the I/O remapping... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) card->membase = ioremap(membase, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) if (!card->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) printk("%s: can't ioremap() membase\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) goto err_out_free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) if (idt77252_preset(card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) printk("%s: preset failed\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) printk("%s: can't register atm device\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) goto err_out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) dev->dev_data = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) card->atmdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) #ifdef CONFIG_ATM_IDT77252_USE_SUNI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) suni_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) if (!dev->phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) printk("%s: can't init SUNI\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) goto err_out_deinit_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) card->sramsize = probe_sram(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (!card->fbq[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) printk("%s: can't ioremap() FBQ%d\n", card->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) goto err_out_deinit_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) card->name, ((card->revision > 1) && (card->revision < 25)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) 'A' + card->revision - 1 : '?', membase, srambase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) card->sramsize / 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) if (init_card(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) printk("%s: init_card failed\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) goto err_out_deinit_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) dev->ci_range.vpi_bits = card->vpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) dev->ci_range.vci_bits = card->vcibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) dev->link_rate = card->link_pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) if (dev->phy->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) dev->phy->start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) if (idt77252_dev_open(card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) printk("%s: dev_open failed\n", card->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) goto err_out_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) *last = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) last = &card->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) err_out_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) if (dev->phy->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) dev->phy->stop(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) err_out_deinit_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) err_out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) iounmap(card->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) err_out_free_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) err_out_disable_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) pci_disable_device(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) static const struct pci_device_id idt77252_pci_tbl[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) static struct pci_driver idt77252_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) .name = "idt77252",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) .id_table = idt77252_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) .probe = idt77252_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) static int __init idt77252_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) printk("%s: at %p\n", __func__, idt77252_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) sizeof(struct idt77252_skb_prv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) __func__, (unsigned long) sizeof(skb->cb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) (unsigned long) sizeof(struct atm_skb_data) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) sizeof(struct idt77252_skb_prv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) return pci_register_driver(&idt77252_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) static void __exit idt77252_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) struct idt77252_dev *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) struct atm_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) pci_unregister_driver(&idt77252_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) while (idt77252_chain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) card = idt77252_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) dev = card->atmdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) idt77252_chain = card->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) if (dev->phy->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) dev->phy->stop(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) deinit_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) pci_disable_device(card->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) kfree(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) DIPRINTK("idt77252: finished cleanup-module().\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) module_init(idt77252_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) module_exit(idt77252_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) module_param(vpibits, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) #ifdef CONFIG_ATM_IDT77252_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) module_param(debug, ulong, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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