^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Madge Horizon ATM Adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) 1995-1999 Madge Networks Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) IMPORTANT NOTE: Madge Networks no longer makes the adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) supported by this driver and makes no commitment to maintain it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* too many macros - change to inline functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef DRIVER_ATM_HORIZON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DRIVER_ATM_HORIZON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_ATM_HORIZON_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DEBUG_HORIZON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEV_LABEL "hrz"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifndef PCI_VENDOR_ID_MADGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_VENDOR_ID_MADGE 0x10B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef PCI_DEVICE_ID_MADGE_HORIZON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCI_DEVICE_ID_MADGE_HORIZON 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) // diagnostic output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRINTK(severity,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) printk(severity DEV_LABEL ": " format "\n" , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifdef DEBUG_HORIZON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DBG_ERR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DBG_WARN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DBG_INFO 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DBG_VCC 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DBG_QOS 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DBG_TX 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DBG_RX 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DBG_SKB 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DBG_IRQ 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DBG_FLOW 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DBG_BUS 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DBG_REGS 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DBG_DATA 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DBG_MASK 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* the ## prevents the annoying double expansion of the macro arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PRINTDB(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PRINTDM(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ( (debug & (bits)) ? printk (format , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PRINTDE(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PRINTD(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PRINTD(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PRINTDB(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PRINTDM(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PRINTDE(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PRINTDD(sec,fmt,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PRINTDDB(sec,fmt,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PRINTDDM(sec,fmt,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PRINTDDE(sec,fmt,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) // fixed constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPARE_BUFFER_POOL_SIZE MAX_VCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HRZ_MAX_VPI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Horizon specific bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HRZ_IO_EXTENT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DATA_PORT_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TX_CHANNEL_PORT_OFF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TX_DESCRIPTOR_PORT_OFF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MEMORY_PORT_OFF 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MEM_WR_ADDR_REG_OFF 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MEM_RD_ADDR_REG_OFF 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CONTROL_0_REG 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INT_SOURCE_REG_OFF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INT_ENABLE_REG_OFF 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MASTER_RX_ADDR_REG_OFF 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MASTER_RX_COUNT_REG_OFF 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MASTER_TX_ADDR_REG_OFF 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MASTER_TX_COUNT_REG_OFF 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TX_DESCRIPTOR_REG_OFF 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TX_CHANNEL_CONFIG_DATA_OFF 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TX_FREE_BUFFER_COUNT_OFF 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RX_FREE_BUFFER_COUNT_OFF 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TX_CONFIG_OFF 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TX_STATUS_OFF 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RX_CONFIG_OFF 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RX_LINE_CONFIG_OFF 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RX_QUEUE_RD_PTR_OFF 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RX_QUEUE_WR_PTR_OFF 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MAX_AAL5_CELL_COUNT_OFF 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RX_CHANNEL_PORT_OFF 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TX_CELL_COUNT_OFF 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RX_CELL_COUNT_OFF 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HEC_ERROR_COUNT_OFF 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define UNASSIGNED_CELL_COUNT_OFF 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Control 0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SEEPROM_DO 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SEEPROM_DI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SEEPROM_SK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SEEPROM_CS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DEBUG_BIT_0 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DEBUG_BIT_1 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DEBUG_BIT_2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) // RESERVED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DEBUG_BIT_0_OE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DEBUG_BIT_1_OE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DEBUG_BIT_2_OE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) // RESERVED 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DEBUG_BIT_0_STATE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DEBUG_BIT_1_STATE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DEBUG_BIT_2_STATE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) // RESERVED 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GENERAL_BIT_0 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GENERAL_BIT_1 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GENERAL_BIT_2 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GENERAL_BIT_3 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RESET_HORIZON 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RESET_ATM 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RESET_RX 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RESET_TX 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RESET_HOST 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) // RESERVED 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TARGET_RETRY_DISABLE 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ATM_LAYER_SELECT 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ATM_LAYER_STATUS 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) // RESERVED 0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Interrupt source and enable registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RX_DATA_AV 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RX_DISABLED 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TIMING_MARKER 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FORCED 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RX_BUS_MASTER_COMPLETE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TX_BUS_MASTER_COMPLETE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ABR_TX_CELL_COUNT_INT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DEBUG_INT 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) // RESERVED 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* PIO and Bus Mastering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MAX_PIO_COUNT 0x000000ff // 255 - make tunable?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) // 8188 is a hard limit for bus mastering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MAX_TRANSFER_COUNT 0x00001ffc // 8188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MASTER_TX_AUTO_APPEND_DESC 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* TX channel config command port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCR_TIMER_ACCESS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SCR_TIMER_ACCESS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BUCKET_CAPACITY_ACCESS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BUCKET_FULLNESS_ACCESS 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RATE_TYPE_ACCESS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) // UNUSED 0x00F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TX_CHANNEL_CONFIG_MULT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) // UNUSED 0xF800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BUCKET_MAX_SIZE 0x003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* TX channel config data port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLOCK_SELECT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLOCK_DISABLE 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IDLE_RATE_TYPE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ABR_RATE_TYPE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define VBR_RATE_TYPE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CBR_RATE_TYPE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* TX config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRVR_DRVRBAR_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TXCLK_MUX_SELECT_RCLK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TRANSMIT_TIMING_MARKER 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LOOPBACK_TIMING_MARKER 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TX_TEST_MODE_16MHz 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TX_TEST_MODE_8MHz 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TX_TEST_MODE_5_33MHz 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TX_TEST_MODE_4MHz 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TX_TEST_MODE_3_2MHz 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TX_TEST_MODE_2_66MHz 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TX_TEST_MODE_2_29MHz 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TX_NORMAL_OPERATION 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ABR_ROUND_ROBIN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* TX status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IDLE_CHANNELS_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ABR_CELL_COUNT_REACHED_MULT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ABR_CELL_COUNT_REACHED_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* RX config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define RX_ENABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* RX line config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SIGNAL_LOSS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define FREQUENCY_DETECT_ERROR 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define LOCK_DETECT_ERROR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SELECT_INTERNAL_LOOPBACK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define LOCK_DETECT_ENABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define FREQUENCY_DETECT_ENABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define USER_FRAQ 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GXTALOUT_SELECT_DIV4 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GXTALOUT_SELECT_NO_GATING 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TIMING_MARKER_RECEIVED 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* RX channel port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define RX_CHANNEL_MASK 0x03FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) // UNUSED 0x3C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FLUSH_CHANNEL 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Receive queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define RX_Q_ENTRY_CHANNEL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SIMONS_DODGEY_MARKER 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RX_CONGESTION_EXPERIENCED 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RX_CRC_10_OK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RX_CRC_32_OK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RX_COMPLETE_FRAME 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Offsets and constants for use with the buffer memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Buffer pointers and channel types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define BUFFER_PTR_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define RX_INT_THRESHOLD_MULT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define RX_INT_THRESHOLD_MASK 0x07FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define INT_EVERY_N_CELLS 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CONGESTION_EXPERIENCED 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define FIRST_CELL_OF_AAL5_FRAME 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CHANNEL_TYPE_AAL5 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CHANNEL_TYPE_RAW_CELLS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CHANNEL_TYPE_AAL3_4 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Buffer status stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BUFF_STATUS_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BUFF_STATUS_EMPTY 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define BUFF_STATUS_CELL_AV 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define BUFF_STATUS_LAST_CELL_AV 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Transmit channel stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Receive channel stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define RX_CHANNEL_DISABLED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define RX_CHANNEL_IDLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* General things */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define INITIAL_CRC 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) // A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) // word addresses and so standard C pointer operations break (as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) // assume byte addresses); so we pretend that Horizon words (and word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) // pointers) are bytes (and byte pointers) for the purposes of having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) // a memory map that works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) typedef u8 HDW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) typedef struct cell_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) HDW payload[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) HDW next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) HDW cell_count; // AAL5 rx bufs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) HDW res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) HDW partial_crc; // AAL5 rx bufs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) HDW cell_header; // RAW bufs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } cell_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) typedef struct tx_ch_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) HDW rd_buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) HDW wr_buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) HDW partial_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) HDW cell_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } tx_ch_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) typedef struct rx_ch_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) HDW wr_buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) HDW rd_buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } rx_ch_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) typedef struct rx_q_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) HDW entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } rx_q_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TX_CHANS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define RX_CHANS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define RX_QS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MAX_VCS RX_CHANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Horizon buffer memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) // TX Channel Descriptors 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) // TX Initial Buffers 8 // TX_CHANS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define BUFN1_SIZE 118 // (126 - TX_CHANS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) // RX/TX Start/End Buffers 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define BUFN2_SIZE 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) // RX Queue Entries 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define BUFN3_SIZE 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) // RX Channel Descriptors 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define BUFN4_SIZE 1408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) // TOTAL cell_buff chunks 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) // cell_buf bufs[2048];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) // HDW dws[32768];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) typedef struct MEMMAP {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cell_buf inittxbufs[TX_CHANS]; // these are really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cell_buf bufn1[BUFN1_SIZE]; // part of this pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cell_buf txfreebufstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cell_buf txfreebufend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cell_buf rxfreebufstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } MEMMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define memmap ((MEMMAP *)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* end horizon specific bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) aal0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) aal34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) aal5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } hrz_aal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tx_busy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rx_busy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ultra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } hrz_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) // a single struct pointed to by atm_vcc->dev_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int tx_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int rx_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u16 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u16 tx_xbr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u16 tx_pcr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u16 tx_scr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u16 tx_bucket_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) hrz_aal aal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } hrz_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct hrz_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 * membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct sk_buff * rx_skb; // skb being RXed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int rx_bytes; // bytes remaining to RX within region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) void * rx_addr; // addr to send bytes to (for PIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int rx_channel; // channel that the skb is going out on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct sk_buff * tx_skb; // skb being TXed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int tx_bytes; // bytes remaining to TX within region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void * tx_addr; // addr to send bytes from (for PIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct iovec * tx_iovec; // remaining regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int tx_regions; // number of remaining regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spinlock_t mem_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) wait_queue_head_t tx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 tx_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u8 tx_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rx_q_entry * rx_q_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rx_q_entry * rx_q_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rx_q_entry * rx_q_wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct atm_dev * atm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 last_vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int noof_spare_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 spare_buffers[SPARE_BUFFER_POOL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u16 tx_channel_record[TX_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) // this is what we follow when we get incoming data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 txer[MAX_VCS/32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct atm_vcc * rxer[MAX_VCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) // cell rate allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spinlock_t rate_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int rx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int tx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) // dev stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long tx_cell_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long rx_cell_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long hec_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned long unassigned_cell_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct pci_dev * pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct timer_list housekeeping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) typedef struct hrz_dev hrz_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* macros for use later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define INTERESTING_INTERRUPTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) // 190 cells by default (192 TX buffers - 2 elbow room, see docs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) // Have enough RX buffers (unless we allow other buffer splits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* multi-statement macro protector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define DW(x) do{ x } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Turn the LEDs on and off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) // The LEDs bits are upside down in that setting the bit in the debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) // register will turn the appropriate LED off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define YELLOW_LED DEBUG_BIT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define GREEN_LED DEBUG_BIT_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define YELLOW_LED_OE DEBUG_BIT_0_OE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define GREEN_LED_OE DEBUG_BIT_1_OE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define GREEN_LED_OFF(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define GREEN_LED_ON(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define YELLOW_LED_OFF(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define YELLOW_LED_ON(dev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) round_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) round_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) round_nearest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } rounding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #endif /* DRIVER_ATM_HORIZON_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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