^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) he.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ForeRunnerHE ATM Adapter driver for ATM on Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 1999-2001 Naval Research Laboratory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) This library is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) modify it under the terms of the GNU Lesser General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) License as published by the Free Software Foundation; either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) version 2.1 of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) This library is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Lesser General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) You should have received a copy of the GNU Lesser General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) License along with this library; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) he.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ForeRunnerHE ATM Adapter driver for ATM on Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Copyright (C) 1999-2000 Naval Research Laboratory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Permission to use, copy, modify and distribute this software and its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) documentation is hereby granted, provided that both the copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) notice and this permission notice appear in all copies of the software,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) derivative works or modified versions, and any portions thereof, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) that both notices appear in supporting documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RESULTING FROM THE USE OF THIS SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifndef _HE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define _HE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DEV_LABEL "he"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CONFIG_DEFAULT_VCIBITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CONFIG_DEFAULT_VPIBITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CONFIG_IRQ_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CONFIG_IRQ_THRESH (CONFIG_IRQ_SIZE/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CONFIG_TPDRQ_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CONFIG_RBRQ_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CONFIG_RBRQ_THRESH 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CONFIG_TBRQ_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CONFIG_TBRQ_THRESH 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CONFIG_RBPL_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CONFIG_RBPL_THRESH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CONFIG_RBPL_BUFSIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* 5.1.3 initialize connection memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CONFIG_RSRA 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CONFIG_RCMLBM 0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CONFIG_RCMABR 0x0d800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CONFIG_RSRB 0x0e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CONFIG_TSRA 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CONFIG_TSRB 0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CONFIG_TSRC 0x0c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CONFIG_TSRD 0x0e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CONFIG_TMABR 0x0f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CONFIG_TPDBA 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HE_MAXCIDBITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* 2.9.3.3 interrupt encodings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct he_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) volatile u32 isw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IRQ_ALIGNMENT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NEXT_ENTRY(base, tail, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (((unsigned long)base)|(((unsigned long)(tail+1))&mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ITYPE_INVALID 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ITYPE_TBRQ_THRESH (0<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ITYPE_TPD_COMPLETE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ITYPE_RBPS_THRESH (2<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ITYPE_RBPL_THRESH (3<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ITYPE_RBRQ_THRESH (4<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ITYPE_RBRQ_TIMER (5<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ITYPE_PHY (6<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ITYPE_OTHER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ITYPE_PARITY 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ITYPE_ABORT 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ITYPE_GROUP(x) (x & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ITYPE_TYPE(x) (x & 0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HE_NUM_GROUPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* 2.1.4 transmit packet descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct he_tpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* read by the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) volatile u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) volatile u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TPD_MAXIOV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 addr, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } iovec[TPD_MAXIOV];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define address0 iovec[0].addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define length0 iovec[0].len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* linux-atm extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TPD_ALIGNMENT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TPD_LEN_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TPD_ADDR_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TPD_MASK 0xffffffc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TPD_ADDR(x) ((x) & TPD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* table 2.3 transmit buffer return elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct he_tbrq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) volatile u32 tbre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TBRQ_ALIGNMENT CONFIG_TBRQ_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TBRQ_TPD(tbrq) ((tbrq)->tbre & 0xffffffc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* table 2.21 receive buffer return queue element field organization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct he_rbrq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) volatile u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) volatile u32 cidlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RBRQ_ALIGNMENT CONFIG_RBRQ_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RBRQ_ADDR(rbrq) ((rbrq)->addr & 0xffffffc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RBRQ_CID(rbrq) (((rbrq)->cidlen >> 16) & 0x1fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RBRQ_BUFLEN(rbrq) ((rbrq)->cidlen & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* figure 2.3 transmit packet descriptor ready queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct he_tpdrq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) volatile u32 tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) volatile u32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* table 2.30 host status page detail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct he_hsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct he_hsp_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) volatile u32 tbrq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) volatile u32 reserved1[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) volatile u32 rbrq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) volatile u32 reserved2[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } group[HE_NUM_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * figure 2.9 receive buffer pools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * since a virtual address might be more than 32 bits, we store an index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * in the virt member of he_rbp. NOTE: the lower six bits in the rbrq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * addr member are used for buffer status further limiting us to 26 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct he_rbp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) volatile u32 phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) volatile u32 idx; /* virt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RBP_IDX_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * the he dma engine will try to hold an extra 16 buffers in its local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * caches. and add a couple buffers for safety.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RBPL_TABLE_SIZE (CONFIG_RBPL_SIZE + 16 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct he_buff {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef notyet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct he_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 rpbl_size, rpbl_qsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct he_rpb_entry *rbpl_ba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct he_vcc_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct he_cs_stper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) long pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HE_NUM_CS_STPER 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct he_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) char prod_id[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) char mac_addr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int vcibits, vpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int cells_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int bytes_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int cells_per_lbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int r0_numrows, r0_startrow, r0_numbuffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int r1_numrows, r1_startrow, r1_numbuffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int tx_numrows, tx_startrow, tx_numbuffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int buffer_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct he_vcc_table *he_vcc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef notyet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct he_group group[HE_NUM_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct he_cs_stper cs_stper[HE_NUM_CS_STPER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned total_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dma_addr_t irq_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct he_irq *irq_base, *irq_head, *irq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) volatile unsigned *irq_tailoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int irq_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct dma_pool *tpd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct list_head outstanding_tpds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_addr_t tpdrq_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spinlock_t global_lock; /* 8.1.5 pci transaction ordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) error problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dma_addr_t rbrq_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct he_rbrq *rbrq_base, *rbrq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int rbrq_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct he_buff **rbpl_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long *rbpl_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long rbpl_hint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct dma_pool *rbpl_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dma_addr_t rbpl_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct he_rbp *rbpl_base, *rbpl_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct list_head rbpl_outstanding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int rbpl_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dma_addr_t tbrq_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct he_tbrq *tbrq_base, *tbrq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int tbrq_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dma_addr_t hsp_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct he_hsp *hsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct atm_dev *atm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct he_dev *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HE_MAXIOV 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct he_vcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct list_head buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int pdu_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int rc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) wait_queue_head_t rx_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) wait_queue_head_t tx_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HE_VCC(vcc) ((struct he_vcc *)(vcc->dev_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PCI_VENDOR_ID_FORE 0x1127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PCI_DEVICE_ID_FORE_HE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define GEN_CNTL_0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define INT_PROC_ENBL (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SLAVE_ENDIAN_MODE (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MRL_ENB (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MRM_ENB (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define INIT_ENB (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IGNORE_TIMEOUT (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ENBL_64 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MIN_PCI_LATENCY 32 /* errata 8.1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define he_is622(dev) ((dev)->media & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define he_isMM(dev) ((dev)->media & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define HE_REGMAP_SIZE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RESET_CNTL 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define BOARD_RST_STATUS (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define HOST_CNTL 0x80004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PCI_BUS_SIZE64 (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DESC_RD_STATIC_64 (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DATA_RD_STATIC_64 (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DATA_WR_STATIC_64 (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ID_CS (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ID_WREN (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ID_DOUT (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define ID_DOFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ID_DIN (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ID_CLOCK (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define QUICK_RD_RETRY (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define QUICK_WR_RETRY (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OUTFF_ENB (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CMDFF_ENB (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PERR_INT_ENB (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IGNORE_INTR (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define LB_SWAP 0x80008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SWAP_RNUM_MAX(x) (x<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define DATA_WR_SWAP (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DESC_RD_SWAP (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DATA_RD_SWAP (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define INTR_SWAP (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DESC_WR_SWAP (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SDRAM_INIT (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define BIG_ENDIAN_HOST (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define XFER_SIZE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define LB_MEM_ADDR 0x8000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define LB_MEM_DATA 0x80010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define LB_MEM_ACCESS 0x80014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define LB_MEM_HNDSHK (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define LM_MEM_WRITE (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define LM_MEM_READ (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SDRAM_CTL 0x80018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define LB_64_ENB (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define LB_TWR (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define LB_TRP (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define LB_TRAS (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define INT_FIFO 0x8001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define INT_MASK_D (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define INT_MASK_C (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define INT_MASK_B (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define INT_MASK_A (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define INT_CLEAR_D (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define INT_CLEAR_C (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define INT_CLEAR_B (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define INT_CLEAR_A (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ABORT_ADDR 0x80020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IRQ0_BASE 0x80080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IRQ_BASE(x) (x<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IRQ0_HEAD 0x80084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IRQ_SIZE(x) (x<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define IRQ_THRESH(x) (x<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define IRQ_HEAD(x) (x<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* #define IRQ_PENDING (1) conflict with linux/irq.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define IRQ0_CNTL 0x80088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define IRQ_ADDRSEL(x) (x<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define IRQ_INT_A (0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IRQ_INT_B (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define IRQ_INT_C (2<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define IRQ_INT_D (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define IRQ_TYPE_ADDR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define IRQ_TYPE_LINE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define IRQ0_DATA 0x8008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define IRQ1_BASE 0x80090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define IRQ1_HEAD 0x80094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define IRQ1_CNTL 0x80098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define IRQ1_DATA 0x8009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define IRQ2_BASE 0x800a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define IRQ2_HEAD 0x800a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define IRQ2_CNTL 0x800a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define IRQ2_DATA 0x800ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define IRQ3_BASE 0x800b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define IRQ3_HEAD 0x800b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define IRQ3_CNTL 0x800b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define IRQ3_DATA 0x800bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define GRP_10_MAP 0x800c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define GRP_32_MAP 0x800c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define GRP_54_MAP 0x800c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define GRP_76_MAP 0x800cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define G0_RBPS_S 0x80400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define G0_RBPS_T 0x80404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define RBP_TAIL(x) ((x)<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define RBP_MASK(x) ((x)|0x1fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define G0_RBPS_QI 0x80408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define RBP_QSIZE(x) ((x)<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define RBP_INT_ENB (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define RBP_THRESH(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define G0_RBPS_BS 0x8040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define G0_RBPL_S 0x80410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define G0_RBPL_T 0x80414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define G0_RBPL_QI 0x80418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define G0_RBPL_BS 0x8041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define G1_RBPS_S 0x80420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define G1_RBPS_T 0x80424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define G1_RBPS_QI 0x80428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define G1_RBPS_BS 0x8042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define G1_RBPL_S 0x80430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define G1_RBPL_T 0x80434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define G1_RBPL_QI 0x80438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define G1_RBPL_BS 0x8043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define G2_RBPS_S 0x80440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define G2_RBPS_T 0x80444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define G2_RBPS_QI 0x80448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define G2_RBPS_BS 0x8044c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define G2_RBPL_S 0x80450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define G2_RBPL_T 0x80454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define G2_RBPL_QI 0x80458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define G2_RBPL_BS 0x8045c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define G3_RBPS_S 0x80460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define G3_RBPS_T 0x80464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define G3_RBPS_QI 0x80468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define G3_RBPS_BS 0x8046c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define G3_RBPL_S 0x80470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define G3_RBPL_T 0x80474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define G3_RBPL_QI 0x80478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define G3_RBPL_BS 0x8047c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define G4_RBPS_S 0x80480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define G4_RBPS_T 0x80484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define G4_RBPS_QI 0x80488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define G4_RBPS_BS 0x8048c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define G4_RBPL_S 0x80490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define G4_RBPL_T 0x80494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define G4_RBPL_QI 0x80498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define G4_RBPL_BS 0x8049c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define G5_RBPS_S 0x804a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define G5_RBPS_T 0x804a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define G5_RBPS_QI 0x804a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define G5_RBPS_BS 0x804ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define G5_RBPL_S 0x804b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define G5_RBPL_T 0x804b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define G5_RBPL_QI 0x804b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define G5_RBPL_BS 0x804bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define G6_RBPS_S 0x804c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define G6_RBPS_T 0x804c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define G6_RBPS_QI 0x804c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define G6_RBPS_BS 0x804cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define G6_RBPL_S 0x804d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define G6_RBPL_T 0x804d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define G6_RBPL_QI 0x804d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define G6_RBPL_BS 0x804dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define G7_RBPS_S 0x804e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define G7_RBPS_T 0x804e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define G7_RBPS_QI 0x804e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define G7_RBPS_BS 0x804ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define G7_RBPL_S 0x804f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define G7_RBPL_T 0x804f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define G7_RBPL_QI 0x804f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define G7_RBPL_BS 0x804fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define G0_RBRQ_ST 0x80500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define G0_RBRQ_H 0x80504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define G0_RBRQ_Q 0x80508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define RBRQ_THRESH(x) ((x)<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define RBRQ_SIZE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define G0_RBRQ_I 0x8050c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define RBRQ_TIME(x) ((x)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define RBRQ_COUNT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* fill in 1 ... 7 later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define G0_TBRQ_B_T 0x80600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define G0_TBRQ_H 0x80604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define G0_TBRQ_S 0x80608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define G0_TBRQ_THRESH 0x8060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define TBRQ_THRESH(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* fill in 1 ... 7 later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define RH_CONFIG 0x805c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PHY_INT_ENB (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define OAM_GID(x) (x<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define PTMR_PRE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define G0_INMQ_S 0x80580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define G0_INMQ_L 0x80584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define G1_INMQ_S 0x80588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define G1_INMQ_L 0x8058c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define G2_INMQ_S 0x80590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define G2_INMQ_L 0x80594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define G3_INMQ_S 0x80598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define G3_INMQ_L 0x8059c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define G4_INMQ_S 0x805a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define G4_INMQ_L 0x805a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define G5_INMQ_S 0x805a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define G5_INMQ_L 0x805ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define G6_INMQ_S 0x805b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define G6_INMQ_L 0x805b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define G7_INMQ_S 0x805b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define G7_INMQ_L 0x805bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define TPDRQ_B_H 0x80680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define TPDRQ_T 0x80684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define TPDRQ_S 0x80688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define UBUFF_BA 0x8068c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define RLBF0_H 0x806c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define RLBF0_T 0x806c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define RLBF1_H 0x806c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define RLBF1_T 0x806cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define RLBC_H 0x806d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define RLBC_T 0x806d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define RLBC_H2 0x806d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define TLBF_H 0x806e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define TLBF_T 0x806e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define RLBF0_C 0x806e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define RLBF1_C 0x806ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define RXTHRSH 0x806f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define LITHRSH 0x806f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define LBARB 0x80700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SLICE_X(x) (x<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define ARB_RNUM_MAX(x) (x<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define TH_PRTY(x) (x<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define RH_PRTY(x) (x<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define TL_PRTY(x) (x<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define RL_PRTY(x) (x<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define BUS_MULTI(x) (x<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define NET_PREF(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SDRAMCON 0x80704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define BANK_ON (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define WIDE_DATA (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define TWR_WAIT (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define TRP_WAIT (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define TRAS_WAIT (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define REF_RATE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define LBSTAT 0x80708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define RCC_STAT 0x8070c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define RCC_BUSY (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define TCMCONFIG 0x80740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define TM_DESL2 (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define TM_BANK_WAIT(x) (x<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define TM_ADD_BANK4(x) (x<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define TM_PAR_CHECK(x) (x<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define TM_RW_WAIT(x) (x<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define TM_SRAM_TYPE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define TSRB_BA 0x80744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define TSRC_BA 0x80748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define TMABR_BA 0x8074c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define TPD_BA 0x80750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define TSRD_BA 0x80758
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define TX_CONFIG 0x80760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define DRF_THRESH(x) (x<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define TX_UT_MODE(x) (x<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define TX_VCI_MASK(x) (x<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define LBFREE_CNT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define TXAAL5_PROTO 0x80764
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define CPCS_UU(x) (x<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define CPI(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define RCMCONFIG 0x80780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define RM_DESL2(x) (x<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define RM_BANK_WAIT(x) (x<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define RM_ADD_BANK(x) (x<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define RM_PAR_CHECK(x) (x<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define RM_RW_WAIT(x) (x<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define RM_SRAM_TYPE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define RCMRSRB_BA 0x80784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define RCMLBM_BA 0x80788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define RCMABR_BA 0x8078c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define RC_CONFIG 0x807c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define UT_RD_DELAY(x) (x<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define WRAP_MODE(x) (x<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define RC_UT_MODE(x) (x<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define RX_ENABLE (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define RX_VALVP(x) (x<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define RX_VALVC(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define MCC 0x807c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define OEC 0x807c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define DCC 0x807cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define CEC 0x807d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define HSP_BA 0x807f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define LB_CONFIG 0x807f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define LB_SIZE(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define CON_DAT 0x807f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define CON_CTL 0x807fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define CON_CTL_MBOX (2<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define CON_CTL_TCM (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define CON_CTL_RCM (0<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define CON_CTL_WRITE (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define CON_CTL_READ (0<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define CON_CTL_BUSY (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define CON_CTL_ADDR(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define FRAMER 0x80800 /* to 0x80bfc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* 3.3 network controller (internal) mailbox registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define CS_STPER0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define CS_STPER31 0x01f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define CS_STTIM0 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define CS_STTIM31 0x03f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define CS_TGRLD0 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define CS_TGRLD15 0x04f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define CS_ERTHR0 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define CS_ERTHR1 0x051
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define CS_ERTHR2 0x052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define CS_ERTHR3 0x053
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define CS_ERTHR4 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define CS_ERCTL0 0x055
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define TX_ENABLE (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define ER_ENABLE (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define CS_ERCTL1 0x056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define CS_ERCTL2 0x057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define CS_ERSTAT0 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define CS_ERSTAT1 0x059
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define CS_RTCCT 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define CS_RTFWC 0x061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define CS_RTFWR 0x062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define CS_RTFTC 0x063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define CS_RTATR 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define CS_TFBSET 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define CS_TFBADD 0x071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define CS_TFBSUB 0x072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define CS_WCRMAX 0x073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define CS_WCRMIN 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define CS_WCRINC 0x075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define CS_WCRDEC 0x076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define CS_WCRCEIL 0x077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define CS_BWDCNT 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define CS_OTPPER 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define CS_OTWPER 0x081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define CS_OTTLIM 0x082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define CS_OTTCNT 0x083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define CS_HGRRT0 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define CS_HGRRT7 0x097
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define CS_ORPTRS 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define RXCON_CLOSE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define TCM_MEM_SIZE 0x20000 /* 2M of 32-bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* 2.5 transmit connection memory registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define TSR0_CONN_STATE(x) ((x>>28) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define TSR0_USE_WMIN (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define TSR0_GROUP(x) ((x & 0x7)<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define TSR0_ABR (2<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define TSR0_UBR (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define TSR0_CBR (0<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define TSR0_PROT (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define TSR0_AAL0_SDU (2<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define TSR0_AAL0 (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define TSR0_AAL5 (0<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define TSR0_HALT_ER (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define TSR0_MARK_CI (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define TSR0_MARK_ER (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define TSR0_UPDATE_GER (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define TSR0_RC_INDEX(x) (x & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define TSR1_PCR(x) ((x & 0x7FFF)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define TSR1_MCR(x) (x & 0x7FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define TSR2_ACR(x) ((x & 0x7FFF)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define TSR3_NRM_CNT(x) ((x & 0xFF)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define TSR3_CRM_CNT(x) (x & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define TSR4_FLUSH_CONN (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define TSR4_SESSION_ENDED (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define TSR4_CRC10 (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define TSR4_NULL_CRC10 (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define TSR4_PROT (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define TSR4_AAL0_SDU (2<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define TSR4_AAL0 (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define TSR4_AAL5 (0<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define TSR9_OPEN_CONN (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define TSR11_ICR(x) ((x & 0x7FFF)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define TSR11_TRM(x) ((x & 0x7)<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define TSR11_NRM(x) ((x & 0x7)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define TSR11_ADTF(x) (x & 0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define TSR13_RDF(x) ((x & 0xF)<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define TSR13_RIF(x) ((x & 0xF)<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define TSR13_CDF(x) ((x & 0x7)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define TSR13_CRM(x) (x & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define TSR14_DELETE (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define TSR14_ABR_CLOSE (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* 2.7.1 per connection receieve state registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define RSR0_START_PDU (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define RSR0_OPEN_CONN (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define RSR0_CLOSE_CONN (0<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define RSR0_PPD_ENABLE (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define RSR0_EPD_ENABLE (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define RSR0_TCP_CKSUM (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define RSR0_AAL5 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define RSR0_AAL0 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define RSR0_AAL0_SDU (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define RSR0_RAWCELL (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define RSR0_RAWCELL_CRC10 (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define RSR1_AQI_ENABLE (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define RSR1_RBPL_ONLY (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define RSR1_GROUP(x) ((x)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define RSR4_AQI_ENABLE (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define RSR4_GROUP(x) ((x)<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define RSR4_RBPL_ONLY (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* 2.1.4 transmit packet descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define TPD_USERCELL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define TPD_SEGMENT_OAMF5 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define TPD_END2END_OAMF5 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define TPD_RMCELL 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define TPD_CELLTYPE(x) (x<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define TPD_EOS (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define TPD_CLP (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define TPD_INT (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define TPD_LST (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* table 4.3 serial eeprom information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define PROD_ID 0x08 /* char[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define PROD_ID_LEN 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define HW_REV 0x26 /* char[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define M_SN 0x3a /* integer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define MEDIA 0x3e /* integer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define HE155MM 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define HE622MM 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define HE155SM 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define HE622SM 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define MAC_ADDR 0x42 /* char[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define CS_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define CS_HIGH ID_CS /* HOST_CNTL_ID_PROM_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define CLK_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define CLK_HIGH ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define SI_HIGH ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define EEPROM_DELAY 400 /* microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #endif /* _HE_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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