^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) he.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ForeRunnerHE ATM Adapter driver for ATM on Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 1999-2001 Naval Research Laboratory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) This library is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) modify it under the terms of the GNU Lesser General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) License as published by the Free Software Foundation; either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) version 2.1 of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) This library is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Lesser General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) You should have received a copy of the GNU Lesser General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) License along with this library; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) he.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ForeRunnerHE ATM Adapter driver for ATM on Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Copyright (C) 1999-2001 Naval Research Laboratory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Permission to use, copy, modify and distribute this software and its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) documentation is hereby granted, provided that both the copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) notice and this permission notice appear in all copies of the software,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) derivative works or modified versions, and any portions thereof, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) that both notices appear in supporting documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RESULTING FROM THE USE OF THIS SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) This driver was written using the "Programmer's Reference Manual for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ForeRunnerHE(tm)", MANU0361-01 - Rev. A, 08/21/98.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) AUTHORS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) chas williams <chas@cmf.nrl.navy.mil>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) eric kinzie <ekinzie@cmf.nrl.navy.mil>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) NOTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 4096 supported 'connections'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) group 0 is used for all traffic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) interrupt queue 0 is used for all interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) aal0 support (based on work from ulrich.u.muller@nokia.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <linux/atm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <linux/sonet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #undef USE_SCATTERGATHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #undef USE_CHECKSUM_HW /* still confused about this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* #undef HE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include "he.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include "suni.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/atm_he.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define hprintk(fmt,args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef HE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HPRINTK(fmt,args...) printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #else /* !HE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HPRINTK(fmt,args...) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif /* HE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int he_open(struct atm_vcc *vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void he_close(struct atm_vcc *vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int he_send(struct atm_vcc *vcc, struct sk_buff *skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int he_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static irqreturn_t he_irq_handler(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void he_tasklet(unsigned long data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int he_proc_read(struct atm_dev *dev,loff_t *pos,char *page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int he_start(struct atm_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void he_stop(struct he_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void he_phy_put(struct atm_dev *, unsigned char, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned char he_phy_get(struct atm_dev *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static u8 read_prom_byte(struct he_dev *he_dev, int addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* globals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct he_dev *he_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static bool disable64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static short nvpibits = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static short nvcibits = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static short rx_skb_reserve = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static bool irq_coalesce = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static bool sdh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Read from EEPROM = 0000 0011b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned int readtab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CS_HIGH | CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CS_LOW | CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) CLK_HIGH, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CLK_HIGH, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CLK_HIGH, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CLK_HIGH, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CLK_HIGH, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CLK_HIGH, /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CLK_LOW | SI_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CLK_HIGH | SI_HIGH, /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_LOW | SI_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CLK_HIGH | SI_HIGH /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Clock to read from/write to the EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static unsigned int clocktab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CLK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CLK_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct atmdev_ops he_ops =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .open = he_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .close = he_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .ioctl = he_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .send = he_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .phy_put = he_phy_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .phy_get = he_phy_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .proc_read = he_proc_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .owner = THIS_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define he_readl(dev, reg) readl((dev)->membase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* section 2.12 connection memory access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) he_writel(he_dev, val, CON_DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (void) he_readl(he_dev, CON_DAT); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define he_writel_rcm(dev, val, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) he_writel_internal(dev, val, reg, CON_CTL_RCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define he_writel_tcm(dev, val, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) he_writel_internal(dev, val, reg, CON_CTL_TCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define he_writel_mbox(dev, val, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) he_writel_internal(dev, val, reg, CON_CTL_MBOX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return he_readl(he_dev, CON_DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define he_readl_rcm(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) he_readl_internal(dev, reg, CON_CTL_RCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define he_readl_tcm(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) he_readl_internal(dev, reg, CON_CTL_TCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define he_readl_mbox(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) he_readl_internal(dev, reg, CON_CTL_MBOX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* figure 2.2 connection id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define he_mkcid(dev, vpi, vci) (((vpi << (dev)->vcibits) | vci) & 0x1fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* 2.5.1 per connection transmit state registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define he_writel_tsr0(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define he_readl_tsr0(dev, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define he_writel_tsr1(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define he_writel_tsr2(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define he_writel_tsr3(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define he_writel_tsr4(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* from page 2-20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * NOTE While the transmit connection is active, bits 23 through 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * of this register must not be written by the host. Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * enables should be used during normal operation when writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * the most significant byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define he_writel_tsr4_upper(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) he_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CON_CTL_TCM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) | CON_BYTE_DISABLE_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) | CON_BYTE_DISABLE_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) | CON_BYTE_DISABLE_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define he_readl_tsr4(dev, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define he_writel_tsr5(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define he_writel_tsr6(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define he_writel_tsr7(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define he_writel_tsr8(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define he_writel_tsr9(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define he_writel_tsr10(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define he_writel_tsr11(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define he_writel_tsr12(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define he_writel_tsr13(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define he_writel_tsr14(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) he_writel_tcm(dev, val, CONFIG_TSRD | cid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define he_writel_tsr14_upper(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) he_writel_internal(dev, val, CONFIG_TSRD | cid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CON_CTL_TCM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) | CON_BYTE_DISABLE_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) | CON_BYTE_DISABLE_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) | CON_BYTE_DISABLE_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* 2.7.1 per connection receive state registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define he_writel_rsr0(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define he_readl_rsr0(dev, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) he_readl_rcm(dev, 0x00000 | (cid << 3) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define he_writel_rsr1(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define he_writel_rsr2(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define he_writel_rsr3(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define he_writel_rsr4(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define he_writel_rsr5(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define he_writel_rsr6(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define he_writel_rsr7(dev, val, cid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static __inline__ struct atm_vcc*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) __find_vcc(struct he_dev *he_dev, unsigned cid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct hlist_head *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct atm_vcc *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct sock *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) short vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) vpi = cid >> he_dev->vcibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) vci = cid & ((1 << he_dev->vcibits) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sk_for_each(s, head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vcc = atm_sk(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (vcc->dev == he_dev->atm_dev &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) vcc->vci == vci && vcc->vpi == vpi &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) vcc->qos.rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int he_init_one(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct pci_device_id *pci_ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct atm_dev *atm_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct he_dev *he_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) printk(KERN_INFO "ATM he driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (pci_enable_device(pci_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) printk(KERN_WARNING "he: no suitable dma available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto init_one_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) atm_dev = atm_dev_register(DEV_LABEL, &pci_dev->dev, &he_ops, -1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!atm_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto init_one_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pci_set_drvdata(pci_dev, atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) he_dev = kzalloc(sizeof(struct he_dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!he_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) goto init_one_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) he_dev->pci_dev = pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) he_dev->atm_dev = atm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) he_dev->atm_dev->dev_data = he_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) atm_dev->dev_data = he_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) he_dev->number = atm_dev->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_lock_init(&he_dev->global_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (he_start(atm_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) he_stop(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto init_one_failure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) he_dev->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (he_devs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) he_dev->next = he_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) he_devs = he_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) init_one_failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (atm_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) atm_dev_deregister(atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) kfree(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_disable_device(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static void he_remove_one(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct atm_dev *atm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct he_dev *he_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) atm_dev = pci_get_drvdata(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) he_dev = HE_DEV(atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* need to remove from he_devs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) he_stop(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) atm_dev_deregister(atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) kfree(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pci_disable_device(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) rate_to_atmf(unsigned rate) /* cps to atm forum format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define NONZERO (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned exp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) rate <<= 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) while (rate > 0x3ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ++exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rate >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return (NONZERO | (exp << 9) | (rate & 0x1ff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void he_init_rx_lbfp0(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) lbufd_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) lbm_offset = he_readl(he_dev, RCMLBM_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) he_writel(he_dev, lbufd_index, RLBF0_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) lbufd_index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (++lbuf_count == lbufs_per_row) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) lbuf_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) row_offset += he_dev->bytes_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) lbm_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) he_writel(he_dev, lbufd_index - 2, RLBF0_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void he_init_rx_lbfp1(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) lbufd_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) he_writel(he_dev, lbufd_index, RLBF1_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) lbufd_index += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (++lbuf_count == lbufs_per_row) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) lbuf_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) row_offset += he_dev->bytes_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) lbm_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) he_writel(he_dev, lbufd_index - 2, RLBF1_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static void he_init_tx_lbfp(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) lbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) he_writel(he_dev, lbufd_index, TLBF_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) lbufd_index += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (++lbuf_count == lbufs_per_row) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) lbuf_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) row_offset += he_dev->bytes_per_row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) lbm_offset += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) he_writel(he_dev, lbufd_index - 1, TLBF_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int he_init_tpdrq(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) he_dev->tpdrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) &he_dev->tpdrq_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (he_dev->tpdrq_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) hprintk("failed to alloc tpdrq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) he_dev->tpdrq_tail = he_dev->tpdrq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) he_dev->tpdrq_head = he_dev->tpdrq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) he_writel(he_dev, 0, TPDRQ_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void he_init_cs_block(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned clock, rate, delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* 5.1.7 cs block initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) for (reg = 0; reg < 0x20; ++reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* rate grid timer reload values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clock = he_is622(he_dev) ? 66667000 : 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) rate = he_dev->atm_dev->link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) delta = rate / 16 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) for (reg = 0; reg < 0x10; ++reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* 2.4 internal transmit function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * we initialize the first row in the rate grid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * values are period (in clock cycles) of timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned period = clock / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) he_writel_mbox(he_dev, period, CS_TGRLD0 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rate -= delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (he_is622(he_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* table 5.2 (4 cells per lbuf) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) he_writel_mbox(he_dev, 0x1801, CS_ERCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) he_writel_mbox(he_dev, 0x14585, CS_RTFWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) he_writel_mbox(he_dev, 0x4680, CS_RTATR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* table 5.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* table 5.9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) he_writel_mbox(he_dev, 0x5, CS_OTPPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) he_writel_mbox(he_dev, 0x14, CS_OTWPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* table 5.1 (4 cells per lbuf) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* table 5.3, 5.4, 5.5, 5.6, 5.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) he_writel_mbox(he_dev, 0x4701, CS_ERCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) he_writel_mbox(he_dev, 0xf424, CS_RTFWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) he_writel_mbox(he_dev, 0x4680, CS_RTATR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* table 5.8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* table 5.9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) he_writel_mbox(he_dev, 0x6, CS_OTPPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) he_writel_mbox(he_dev, 0x1e, CS_OTWPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) he_writel_mbox(he_dev, 0x8, CS_OTTLIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) for (reg = 0; reg < 0x8; ++reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int he_init_cs_block_rcm(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned (*rategrid)[16][16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned rate, delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int i, j, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned rate_atmf, exp, man;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned long long rate_cps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int mult, buf, buf_limit = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) rategrid = kmalloc( sizeof(unsigned) * 16 * 16, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!rategrid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* initialize rate grid group table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) for (reg = 0x0; reg < 0xff; ++reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* initialize rate controller groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for (reg = 0x100; reg < 0x1ff; ++reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* initialize tNrm lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* the manual makes reference to a routine in a sample driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) for proper configuration; fortunately, we only need this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) in order to support abr connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* initialize rate to group table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) rate = he_dev->atm_dev->link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) delta = rate / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * 2.4 transmit internal functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * we construct a copy of the rate grid used by the scheduler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * in order to construct the rate to group table below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) for (j = 0; j < 16; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) (*rategrid)[0][j] = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) rate -= delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) for (i = 1; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) for (j = 0; j < 16; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (i > 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) (*rategrid)[i][j] = (*rategrid)[i - 1][j] / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) (*rategrid)[i][j] = (*rategrid)[i - 1][j] / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * 2.4 transmit internal function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * this table maps the upper 5 bits of exponent and mantissa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * of the atm forum representation of the rate into an index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * on rate grid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rate_atmf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) while (rate_atmf < 0x400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) man = (rate_atmf & 0x1f) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) exp = rate_atmf >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) instead of '/ 512', use '>> 9' to prevent a call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) to divdu3 on x86 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) rate_cps = (unsigned long long) (1UL << exp) * (man + 512) >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (rate_cps < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) rate_cps = 10; /* 2.2.1 minimum payload rate is 10 cps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) for (i = 255; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if ((*rategrid)[i/16][i%16] >= rate_cps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break; /* pick nearest rate instead? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * each table entry is 16 bits: (rate grid index (8 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * and a buffer limit (8 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * there are two table entries in each 32-bit register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #ifdef notdef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) buf = rate_cps * he_dev->tx_numbuffs /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) (he_dev->atm_dev->link_rate * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* this is pretty, but avoids _divdu3 and is mostly correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (rate_cps > (272ULL * mult))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) buf = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) else if (rate_cps > (204ULL * mult))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) buf = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) else if (rate_cps > (136ULL * mult))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) buf = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) else if (rate_cps > (68ULL * mult))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) buf = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (buf > buf_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) buf = buf_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) reg = (reg << 16) | ((i << 8) | buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define RTGTBL_OFFSET 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (rate_atmf & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) he_writel_rcm(he_dev, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) CONFIG_RCMABR + RTGTBL_OFFSET + (rate_atmf >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ++rate_atmf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) kfree(rategrid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int he_init_group(struct he_dev *he_dev, int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct he_buff *heb, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) G0_RBPS_BS + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* bitmap table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) he_dev->rbpl_table = kmalloc_array(BITS_TO_LONGS(RBPL_TABLE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) sizeof(*he_dev->rbpl_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!he_dev->rbpl_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) hprintk("unable to allocate rbpl bitmap table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) bitmap_zero(he_dev->rbpl_table, RBPL_TABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* rbpl_virt 64-bit pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) he_dev->rbpl_virt = kmalloc_array(RBPL_TABLE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) sizeof(*he_dev->rbpl_virt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!he_dev->rbpl_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) hprintk("unable to allocate rbpl virt table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) goto out_free_rbpl_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* large buffer pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) he_dev->rbpl_pool = dma_pool_create("rbpl", &he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) CONFIG_RBPL_BUFSIZE, 64, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (he_dev->rbpl_pool == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) hprintk("unable to create rbpl pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) goto out_free_rbpl_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) he_dev->rbpl_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) CONFIG_RBPL_SIZE * sizeof(struct he_rbp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) &he_dev->rbpl_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (he_dev->rbpl_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) hprintk("failed to alloc rbpl_base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto out_destroy_rbpl_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) INIT_LIST_HEAD(&he_dev->rbpl_outstanding);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) for (i = 0; i < CONFIG_RBPL_SIZE; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) heb = dma_pool_alloc(he_dev->rbpl_pool, GFP_KERNEL, &mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!heb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) goto out_free_rbpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) heb->mapping = mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) list_add(&heb->entry, &he_dev->rbpl_outstanding);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) set_bit(i, he_dev->rbpl_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) he_dev->rbpl_virt[i] = heb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) he_dev->rbpl_hint = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) he_dev->rbpl_base[i].idx = i << RBP_IDX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) he_dev->rbpl_base[i].phys = mapping + offsetof(struct he_buff, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) he_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) G0_RBPL_T + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) G0_RBPL_BS + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RBP_THRESH(CONFIG_RBPL_THRESH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) RBP_QSIZE(CONFIG_RBPL_SIZE - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) RBP_INT_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) G0_RBPL_QI + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* rx buffer ready queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) he_dev->rbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) &he_dev->rbrq_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (he_dev->rbrq_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) hprintk("failed to allocate rbrq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) goto out_free_rbpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) he_dev->rbrq_head = he_dev->rbrq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) RBRQ_THRESH(CONFIG_RBRQ_THRESH) | RBRQ_SIZE(CONFIG_RBRQ_SIZE - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) G0_RBRQ_Q + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (irq_coalesce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) hprintk("coalescing interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) G0_RBRQ_I + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) G0_RBRQ_I + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* tx buffer ready queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) he_dev->tbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &he_dev->tbrq_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (he_dev->tbrq_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) hprintk("failed to allocate tbrq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto out_free_rbpq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) he_dev->tbrq_head = he_dev->tbrq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) out_free_rbpq_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBRQ_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) sizeof(struct he_rbrq), he_dev->rbrq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) he_dev->rbrq_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) out_free_rbpl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBPL_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) sizeof(struct he_rbp), he_dev->rbpl_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) he_dev->rbpl_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) out_destroy_rbpl_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dma_pool_destroy(he_dev->rbpl_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) out_free_rbpl_virt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) kfree(he_dev->rbpl_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) out_free_rbpl_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) kfree(he_dev->rbpl_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int he_init_irq(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* 2.9.3.5 tail offset for each interrupt queue is located after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) end of the interrupt queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) he_dev->irq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) (CONFIG_IRQ_SIZE + 1) * sizeof(struct he_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) &he_dev->irq_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (he_dev->irq_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) hprintk("failed to allocate irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) he_dev->irq_tailoffset = (unsigned *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) &he_dev->irq_base[CONFIG_IRQ_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *he_dev->irq_tailoffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) he_dev->irq_head = he_dev->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) he_dev->irq_tail = he_dev->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) for (i = 0; i < CONFIG_IRQ_SIZE; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) he_dev->irq_base[i].isw = ITYPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) IRQ_SIZE(CONFIG_IRQ_SIZE) | IRQ_THRESH(CONFIG_IRQ_THRESH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) IRQ0_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) he_writel(he_dev, 0x0, IRQ0_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) he_writel(he_dev, 0x0, IRQ1_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) he_writel(he_dev, 0x0, IRQ1_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) he_writel(he_dev, 0x0, IRQ1_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) he_writel(he_dev, 0x0, IRQ1_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) he_writel(he_dev, 0x0, IRQ2_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) he_writel(he_dev, 0x0, IRQ2_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) he_writel(he_dev, 0x0, IRQ2_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) he_writel(he_dev, 0x0, IRQ2_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) he_writel(he_dev, 0x0, IRQ3_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) he_writel(he_dev, 0x0, IRQ3_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) he_writel(he_dev, 0x0, IRQ3_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) he_writel(he_dev, 0x0, IRQ3_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* 2.9.3.2 interrupt queue mapping registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) he_writel(he_dev, 0x0, GRP_10_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) he_writel(he_dev, 0x0, GRP_32_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) he_writel(he_dev, 0x0, GRP_54_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) he_writel(he_dev, 0x0, GRP_76_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (request_irq(he_dev->pci_dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) he_irq_handler, IRQF_SHARED, DEV_LABEL, he_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) hprintk("irq %d already in use\n", he_dev->pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) he_dev->irq = he_dev->pci_dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int he_start(struct atm_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct he_dev *he_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) unsigned long membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u32 gen_cntl_0, host_cntl, lb_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 cache_size, timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned int status, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int i, group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) he_dev = HE_DEV(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pci_dev = he_dev->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) membase = pci_resource_start(pci_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) HPRINTK("membase = 0x%lx irq = %d.\n", membase, pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * pci bus controller initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* 4.3 pci bus controller-specific initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) hprintk("can't read GEN_CNTL_0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) gen_cntl_0 |= (MRL_ENB | MRM_ENB | IGNORE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) hprintk("can't write GEN_CNTL_0.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (pci_read_config_word(pci_dev, PCI_COMMAND, &command) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) hprintk("can't read PCI_COMMAND.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (pci_write_config_word(pci_dev, PCI_COMMAND, command) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) hprintk("can't enable memory.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (pci_read_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, &cache_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) hprintk("can't read cache line size?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (cache_size < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) cache_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, cache_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) hprintk("can't set cache line size to %d\n", cache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) hprintk("can't read latency timer?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* from table 3.9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * LAT_TIMER = 1 + AVG_LAT + BURST_SIZE/BUS_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * AVG_LAT: The average first data read/write latency [maximum 16 clock cycles]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * BURST_SIZE: 1536 bytes (read) for 622, 768 bytes (read) for 155 [192 clock cycles]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define LAT_TIMER 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (timer < LAT_TIMER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) HPRINTK("latency timer was %d, setting to %d\n", timer, LAT_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) timer = LAT_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, timer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) hprintk("can't set latency timer to %d\n", timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) hprintk("can't set up page mapping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* 4.4 card reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) he_writel(he_dev, 0x0, RESET_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) he_writel(he_dev, 0xff, RESET_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) msleep(16); /* 16 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) status = he_readl(he_dev, RESET_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if ((status & BOARD_RST_STATUS) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) hprintk("reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* 4.5 set bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) host_cntl = he_readl(he_dev, HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (host_cntl & PCI_BUS_SIZE64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) gen_cntl_0 |= ENBL_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) gen_cntl_0 &= ~ENBL_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (disable64 == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) hprintk("disabling 64-bit pci bus transfers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) gen_cntl_0 &= ~ENBL_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (gen_cntl_0 & ENBL_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) hprintk("64-bit transfers enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* 4.7 read prom contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) for (i = 0; i < PROD_ID_LEN; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) he_dev->prod_id[i] = read_prom_byte(he_dev, PROD_ID + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) he_dev->media = read_prom_byte(he_dev, MEDIA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) for (i = 0; i < 6; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev->esi[i] = read_prom_byte(he_dev, MAC_ADDR + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) hprintk("%s%s, %pM\n", he_dev->prod_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) he_dev->media & 0x40 ? "SM" : "MM", dev->esi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) he_dev->atm_dev->link_rate = he_is622(he_dev) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ATM_OC12_PCR : ATM_OC3_PCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* 4.6 set host endianess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) lb_swap = he_readl(he_dev, LB_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (he_is622(he_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) lb_swap &= ~XFER_SIZE; /* 4 cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) lb_swap |= XFER_SIZE; /* 8 cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) lb_swap |= DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) lb_swap &= ~(DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) DATA_WR_SWAP | DATA_RD_SWAP | DESC_RD_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #endif /* __BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) he_writel(he_dev, lb_swap, LB_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* 4.8 sdram controller initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* 4.9 initialize rnum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) lb_swap |= SWAP_RNUM_MAX(0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) he_writel(he_dev, lb_swap, LB_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* 4.10 initialize the interrupt queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if ((err = he_init_irq(he_dev)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* 4.11 enable pci bus controller state machines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) host_cntl |= (OUTFF_ENB | CMDFF_ENB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) QUICK_RD_RETRY | QUICK_WR_RETRY | PERR_INT_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) he_writel(he_dev, host_cntl, HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) gen_cntl_0 |= INT_PROC_ENBL|INIT_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * atm network controller initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* 5.1.1 generic configuration state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * local (cell) buffer memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * HE155 HE622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * 0 ____________1023 bytes 0 _______________________2047 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * | utility | | rx0 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * 5|____________| 255|___________________| u |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * 6| | 256| | t |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * | | | | i |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * | rx0 | row | tx | l |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * | | | | i |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * | | 767|___________________| t |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * 517|____________| 768| | y |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * row 518| | | rx1 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * | | 1023|___________________|___|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * | tx |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * 1535|____________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * 1536| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * | rx1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * 2047|____________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* total 4096 connections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) he_dev->vcibits = CONFIG_DEFAULT_VCIBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) he_dev->vpibits = CONFIG_DEFAULT_VPIBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (nvpibits != -1 && nvcibits != -1 && nvpibits+nvcibits != HE_MAXCIDBITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) hprintk("nvpibits + nvcibits != %d\n", HE_MAXCIDBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (nvpibits != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) he_dev->vpibits = nvpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) he_dev->vcibits = HE_MAXCIDBITS - nvpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (nvcibits != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) he_dev->vcibits = nvcibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) he_dev->vpibits = HE_MAXCIDBITS - nvcibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (he_is622(he_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) he_dev->cells_per_row = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) he_dev->bytes_per_row = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) he_dev->r0_numrows = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) he_dev->tx_numrows = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) he_dev->r1_numrows = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) he_dev->r0_startrow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) he_dev->tx_startrow = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) he_dev->r1_startrow = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) he_dev->cells_per_row = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) he_dev->bytes_per_row = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) he_dev->r0_numrows = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) he_dev->tx_numrows = 1018;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) he_dev->r1_numrows = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) he_dev->r0_startrow = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) he_dev->tx_startrow = 518;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) he_dev->r1_startrow = 1536;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) he_dev->cells_per_lbuf = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) he_dev->buffer_limit = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) he_dev->r0_numbuffs = he_dev->r0_numrows *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) he_dev->cells_per_row / he_dev->cells_per_lbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (he_dev->r0_numbuffs > 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) he_dev->r0_numbuffs = 2560;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) he_dev->r1_numbuffs = he_dev->r1_numrows *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) he_dev->cells_per_row / he_dev->cells_per_lbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (he_dev->r1_numbuffs > 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) he_dev->r1_numbuffs = 2560;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) he_dev->tx_numbuffs = he_dev->tx_numrows *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) he_dev->cells_per_row / he_dev->cells_per_lbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (he_dev->tx_numbuffs > 5120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) he_dev->tx_numbuffs = 5120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* 5.1.2 configure hardware dependent registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) SLICE_X(0x2) | ARB_RNUM_MAX(0xf) | TH_PRTY(0x3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) RH_PRTY(0x3) | TL_PRTY(0x2) | RL_PRTY(0x1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) (he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) (he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) LBARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) he_writel(he_dev, BANK_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) (he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) SDRAMCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) (he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) RM_RW_WAIT(1), RCMCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) (he_is622(he_dev) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) TM_RW_WAIT(1), TCMCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) (he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) (he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) RX_VALVP(he_dev->vpibits) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) RX_VALVC(he_dev->vcibits), RC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) he_writel(he_dev, DRF_THRESH(0x20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) (he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) TX_VCI_MASK(he_dev->vcibits) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) LBFREE_CNT(he_dev->tx_numbuffs), TX_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) he_writel(he_dev, 0x0, TXAAL5_PROTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) he_writel(he_dev, PHY_INT_ENB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) (he_is622(he_dev) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) RH_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* 5.1.3 initialize connection memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) for (i = 0; i < TCM_MEM_SIZE; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) he_writel_tcm(he_dev, 0, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) for (i = 0; i < RCM_MEM_SIZE; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) he_writel_rcm(he_dev, 0, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * transmit connection memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * tx memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * 0x0 ___________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * | TSRa |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * 0x8000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * | TSRb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * 0xc000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * | TSRc |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * 0xe000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * | TSRd |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * 0xf000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * | tmABR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * 0x10000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * | tmTPD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * |___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * 0x1ffff|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * receive connection memory map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * 0x0 ___________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * | RSRa |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * 0x8000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * | rx0/1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * | LBM | link lists of local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * | tx | buffer memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * 0xd000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * | rmABR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * 0xe000|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * | RSRb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * |___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * 0xffff|___________________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) he_writel(he_dev, 0x08000, RCMLBM_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) he_writel(he_dev, 0x0e000, RCMRSRB_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) he_writel(he_dev, 0x0d800, RCMABR_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* 5.1.4 initialize local buffer free pools linked lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) he_init_rx_lbfp0(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) he_init_rx_lbfp1(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) he_writel(he_dev, 0x0, RLBC_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) he_writel(he_dev, 0x0, RLBC_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) he_writel(he_dev, 0x0, RLBC_H2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) he_init_tx_lbfp(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* 5.1.5 initialize intermediate receive queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (he_is622(he_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) he_writel(he_dev, 0x000f, G0_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) he_writel(he_dev, 0x200f, G0_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) he_writel(he_dev, 0x001f, G1_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) he_writel(he_dev, 0x201f, G1_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) he_writel(he_dev, 0x002f, G2_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) he_writel(he_dev, 0x202f, G2_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) he_writel(he_dev, 0x003f, G3_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) he_writel(he_dev, 0x203f, G3_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) he_writel(he_dev, 0x004f, G4_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) he_writel(he_dev, 0x204f, G4_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) he_writel(he_dev, 0x005f, G5_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) he_writel(he_dev, 0x205f, G5_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) he_writel(he_dev, 0x006f, G6_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) he_writel(he_dev, 0x206f, G6_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) he_writel(he_dev, 0x007f, G7_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) he_writel(he_dev, 0x207f, G7_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) he_writel(he_dev, 0x0000, G0_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) he_writel(he_dev, 0x0008, G0_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) he_writel(he_dev, 0x0001, G1_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) he_writel(he_dev, 0x0009, G1_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) he_writel(he_dev, 0x0002, G2_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) he_writel(he_dev, 0x000a, G2_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) he_writel(he_dev, 0x0003, G3_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) he_writel(he_dev, 0x000b, G3_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) he_writel(he_dev, 0x0004, G4_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) he_writel(he_dev, 0x000c, G4_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) he_writel(he_dev, 0x0005, G5_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) he_writel(he_dev, 0x000d, G5_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) he_writel(he_dev, 0x0006, G6_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) he_writel(he_dev, 0x000e, G6_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) he_writel(he_dev, 0x0007, G7_INMQ_S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) he_writel(he_dev, 0x000f, G7_INMQ_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* 5.1.6 application tunable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) he_writel(he_dev, 0x0, MCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) he_writel(he_dev, 0x0, OEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) he_writel(he_dev, 0x0, DCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) he_writel(he_dev, 0x0, CEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* 5.1.7 cs block initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) he_init_cs_block(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* 5.1.8 cs block connection memory initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (he_init_cs_block_rcm(he_dev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* 5.1.10 initialize host structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) he_init_tpdrq(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) he_dev->tpd_pool = dma_pool_create("tpd", &he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) sizeof(struct he_tpd), TPD_ALIGNMENT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (he_dev->tpd_pool == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) hprintk("unable to create tpd dma_pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) INIT_LIST_HEAD(&he_dev->outstanding_tpds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (he_init_group(he_dev, 0) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) for (group = 1; group < HE_NUM_GROUPS; ++group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) G0_RBPS_BS + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) G0_RBPL_QI + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) G0_RBRQ_Q + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) he_writel(he_dev, TBRQ_THRESH(0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) G0_TBRQ_THRESH + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* host status page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) he_dev->hsp = dma_alloc_coherent(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) sizeof(struct he_hsp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) &he_dev->hsp_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (he_dev->hsp == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) hprintk("failed to allocate host status page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* initialize framer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #ifdef CONFIG_ATM_HE_USE_SUNI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (he_isMM(he_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) suni_init(he_dev->atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) he_dev->atm_dev->phy->start(he_dev->atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #endif /* CONFIG_ATM_HE_USE_SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (sdh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* this really should be in suni.c but for now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) val = (val & ~SUNI_TPOP_APM_S) | (SUNI_TPOP_S_SDH << SUNI_TPOP_APM_S_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) he_phy_put(he_dev->atm_dev, SUNI_TACP_IUCHP_CLP, SUNI_TACP_IUCHP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* 5.1.12 enable transmit and receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) reg = he_readl_mbox(he_dev, CS_ERCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) reg |= TX_ENABLE|ER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) he_writel_mbox(he_dev, reg, CS_ERCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) reg = he_readl(he_dev, RC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) reg |= RX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) he_writel(he_dev, reg, RC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) for (i = 0; i < HE_NUM_CS_STPER; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) he_dev->cs_stper[i].inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) he_dev->cs_stper[i].pcr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) he_dev->total_bw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* atm linux initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) he_dev->atm_dev->ci_range.vpi_bits = he_dev->vpibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) he_dev->atm_dev->ci_range.vci_bits = he_dev->vcibits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) he_dev->irq_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) he_dev->rbrq_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) he_dev->rbpl_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) he_dev->tbrq_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) HPRINTK("hell bent for leather!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) he_stop(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct he_buff *heb, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) u32 gen_cntl_0, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) pci_dev = he_dev->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (he_dev->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) gen_cntl_0 &= ~(INT_PROC_ENBL | INIT_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) tasklet_disable(&he_dev->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /* disable recv and transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) reg = he_readl_mbox(he_dev, CS_ERCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) reg &= ~(TX_ENABLE|ER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) he_writel_mbox(he_dev, reg, CS_ERCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) reg = he_readl(he_dev, RC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) reg &= ~(RX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) he_writel(he_dev, reg, RC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #ifdef CONFIG_ATM_HE_USE_SUNI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) he_dev->atm_dev->phy->stop(he_dev->atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #endif /* CONFIG_ATM_HE_USE_SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (he_dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) free_irq(he_dev->irq, he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (he_dev->irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) dma_free_coherent(&he_dev->pci_dev->dev, (CONFIG_IRQ_SIZE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * sizeof(struct he_irq), he_dev->irq_base, he_dev->irq_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (he_dev->hsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dma_free_coherent(&he_dev->pci_dev->dev, sizeof(struct he_hsp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) he_dev->hsp, he_dev->hsp_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (he_dev->rbpl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBPL_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * sizeof(struct he_rbp), he_dev->rbpl_base, he_dev->rbpl_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) kfree(he_dev->rbpl_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) kfree(he_dev->rbpl_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dma_pool_destroy(he_dev->rbpl_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (he_dev->rbrq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) he_dev->rbrq_base, he_dev->rbrq_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (he_dev->tbrq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) he_dev->tbrq_base, he_dev->tbrq_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (he_dev->tpdrq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) he_dev->tpdrq_base, he_dev->tpdrq_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dma_pool_destroy(he_dev->tpd_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (he_dev->pci_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) pci_read_config_word(he_dev->pci_dev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) pci_write_config_word(he_dev->pci_dev, PCI_COMMAND, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (he_dev->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) iounmap(he_dev->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static struct he_tpd *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) __alloc_tpd(struct he_dev *he_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct he_tpd *tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) tpd = dma_pool_alloc(he_dev->tpd_pool, GFP_ATOMIC, &mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (tpd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) tpd->status = TPD_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) tpd->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) tpd->iovec[0].addr = 0; tpd->iovec[0].len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) tpd->iovec[1].addr = 0; tpd->iovec[1].len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) tpd->iovec[2].addr = 0; tpd->iovec[2].len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define AAL5_LEN(buf,len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ((((unsigned char *)(buf))[(len)-6] << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) (((unsigned char *)(buf))[(len)-5]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* 2.10.1.2 receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * aal5 packets can optionally return the tcp checksum in the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * 16 bits of the crc (RSR0_TCP_CKSUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define TCP_CKSUM(buf,len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ((((unsigned char *)(buf))[(len)-2] << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) (((unsigned char *)(buf))[(len-1)]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) he_service_rbrq(struct he_dev *he_dev, int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct he_rbrq *rbrq_tail = (struct he_rbrq *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ((unsigned long)he_dev->rbrq_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) he_dev->hsp->group[group].rbrq_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) unsigned cid, lastcid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct atm_vcc *vcc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct he_vcc *he_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct he_buff *heb, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int pdus_assembled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) int updated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) read_lock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) while (he_dev->rbrq_head != rbrq_tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ++updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) HPRINTK("%p rbrq%d 0x%x len=%d cid=0x%x %s%s%s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) he_dev->rbrq_head, group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) RBRQ_ADDR(he_dev->rbrq_head),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) RBRQ_BUFLEN(he_dev->rbrq_head),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) RBRQ_CID(he_dev->rbrq_head),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) RBRQ_CRC_ERR(he_dev->rbrq_head) ? " CRC_ERR" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) RBRQ_LEN_ERR(he_dev->rbrq_head) ? " LEN_ERR" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) RBRQ_END_PDU(he_dev->rbrq_head) ? " END_PDU" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) RBRQ_AAL5_PROT(he_dev->rbrq_head) ? " AAL5_PROT" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) RBRQ_CON_CLOSED(he_dev->rbrq_head) ? " CON_CLOSED" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) RBRQ_HBUF_ERR(he_dev->rbrq_head) ? " HBUF_ERR" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) i = RBRQ_ADDR(he_dev->rbrq_head) >> RBP_IDX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) heb = he_dev->rbpl_virt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) cid = RBRQ_CID(he_dev->rbrq_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (cid != lastcid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) vcc = __find_vcc(he_dev, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) lastcid = cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (vcc == NULL || (he_vcc = HE_VCC(vcc)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) hprintk("vcc/he_vcc == NULL (cid 0x%x)\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (!RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) clear_bit(i, he_dev->rbpl_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) list_del(&heb->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) goto next_rbrq_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hprintk("HBUF_ERR! (cid 0x%x)\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) atomic_inc(&vcc->stats->rx_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) goto return_host_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) heb->len = RBRQ_BUFLEN(he_dev->rbrq_head) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) clear_bit(i, he_dev->rbpl_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) list_move_tail(&heb->entry, &he_vcc->buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) he_vcc->pdu_len += heb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (RBRQ_CON_CLOSED(he_dev->rbrq_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) lastcid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) HPRINTK("wake_up rx_waitq (cid 0x%x)\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) wake_up(&he_vcc->rx_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) goto return_host_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (!RBRQ_END_PDU(he_dev->rbrq_head))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) goto next_rbrq_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (RBRQ_LEN_ERR(he_dev->rbrq_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) || RBRQ_CRC_ERR(he_dev->rbrq_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) HPRINTK("%s%s (%d.%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) RBRQ_CRC_ERR(he_dev->rbrq_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ? "CRC_ERR " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) RBRQ_LEN_ERR(he_dev->rbrq_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ? "LEN_ERR" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) atomic_inc(&vcc->stats->rx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) goto return_host_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) skb = atm_alloc_charge(vcc, he_vcc->pdu_len + rx_skb_reserve,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) HPRINTK("charge failed (%d.%d)\n", vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) goto return_host_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (rx_skb_reserve > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) skb_reserve(skb, rx_skb_reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) __net_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) list_for_each_entry(heb, &he_vcc->buffers, entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) skb_put_data(skb, &heb->data, heb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) switch (vcc->qos.aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* 2.10.1.5 raw cell receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) skb->len = ATM_AAL0_SDU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) skb_set_tail_pointer(skb, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* 2.10.1.2 aal5 receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) skb->len = AAL5_LEN(skb->data, he_vcc->pdu_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) skb_set_tail_pointer(skb, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #ifdef USE_CHECKSUM_HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (vcc->vpi == 0 && vcc->vci >= ATM_NOT_RSV_VCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) skb->ip_summed = CHECKSUM_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) skb->csum = TCP_CKSUM(skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) he_vcc->pdu_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #ifdef should_never_happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (skb->len > vcc->qos.rxtp.max_sdu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) hprintk("pdu_len (%d) > vcc->qos.rxtp.max_sdu (%d)! cid 0x%x\n", skb->len, vcc->qos.rxtp.max_sdu, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #ifdef notdef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ATM_SKB(skb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) spin_unlock(&he_dev->global_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) vcc->push(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) spin_lock(&he_dev->global_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) atomic_inc(&vcc->stats->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return_host_buffers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ++pdus_assembled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) list_for_each_entry_safe(heb, next, &he_vcc->buffers, entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) INIT_LIST_HEAD(&he_vcc->buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) he_vcc->pdu_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) next_rbrq_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) he_dev->rbrq_head = (struct he_rbrq *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ((unsigned long) he_dev->rbrq_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) RBRQ_MASK(he_dev->rbrq_head + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) read_unlock(&vcc_sklist_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (updated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (updated > he_dev->rbrq_peak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) he_dev->rbrq_peak = updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) G0_RBRQ_H + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return pdus_assembled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) he_service_tbrq(struct he_dev *he_dev, int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) struct he_tbrq *tbrq_tail = (struct he_tbrq *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ((unsigned long)he_dev->tbrq_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) he_dev->hsp->group[group].tbrq_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct he_tpd *tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) int slot, updated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) struct he_tpd *__tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) /* 2.1.6 transmit buffer return queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) while (he_dev->tbrq_head != tbrq_tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ++updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) HPRINTK("tbrq%d 0x%x%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) TBRQ_TPD(he_dev->tbrq_head),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) TBRQ_EOS(he_dev->tbrq_head) ? " EOS" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) TBRQ_MULTIPLE(he_dev->tbrq_head) ? " MULTIPLE" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) tpd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) list_for_each_entry(__tpd, &he_dev->outstanding_tpds, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) if (TPD_ADDR(__tpd->status) == TBRQ_TPD(he_dev->tbrq_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) tpd = __tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) list_del(&__tpd->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (tpd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) hprintk("unable to locate tpd for dma buffer %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) TBRQ_TPD(he_dev->tbrq_head));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) goto next_tbrq_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (TBRQ_EOS(he_dev->tbrq_head)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) HPRINTK("wake_up(tx_waitq) cid 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) he_mkcid(he_dev, tpd->vcc->vpi, tpd->vcc->vci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (tpd->vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) wake_up(&HE_VCC(tpd->vcc)->tx_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) goto next_tbrq_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) for (slot = 0; slot < TPD_MAXIOV; ++slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (tpd->iovec[slot].addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) dma_unmap_single(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) tpd->iovec[slot].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) tpd->iovec[slot].len & TPD_LEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (tpd->iovec[slot].len & TPD_LST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (tpd->skb) { /* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (tpd->vcc && tpd->vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) tpd->vcc->pop(tpd->vcc, tpd->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) dev_kfree_skb_any(tpd->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) next_tbrq_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (tpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) dma_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) he_dev->tbrq_head = (struct he_tbrq *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ((unsigned long) he_dev->tbrq_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) TBRQ_MASK(he_dev->tbrq_head + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (updated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (updated > he_dev->tbrq_peak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) he_dev->tbrq_peak = updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) G0_TBRQ_H + (group * 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) he_service_rbpl(struct he_dev *he_dev, int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct he_rbp *new_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) struct he_rbp *rbpl_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) struct he_buff *heb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) int moved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) rbpl_head = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) RBPL_MASK(he_readl(he_dev, G0_RBPL_S)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) new_tail = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) RBPL_MASK(he_dev->rbpl_tail+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* table 3.42 -- rbpl_tail should never be set to rbpl_head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (new_tail == rbpl_head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) i = find_next_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE, he_dev->rbpl_hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (i > (RBPL_TABLE_SIZE - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) i = find_first_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (i > (RBPL_TABLE_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) he_dev->rbpl_hint = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) heb = dma_pool_alloc(he_dev->rbpl_pool, GFP_ATOMIC, &mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (!heb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) heb->mapping = mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) list_add(&heb->entry, &he_dev->rbpl_outstanding);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) he_dev->rbpl_virt[i] = heb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) set_bit(i, he_dev->rbpl_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) new_tail->idx = i << RBP_IDX_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) new_tail->phys = mapping + offsetof(struct he_buff, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) he_dev->rbpl_tail = new_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ++moved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (moved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) he_tasklet(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) struct he_dev *he_dev = (struct he_dev *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) int group, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) int updated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) HPRINTK("tasklet (0x%lx)\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) while (he_dev->irq_head != he_dev->irq_tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ++updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) type = ITYPE_TYPE(he_dev->irq_head->isw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) group = ITYPE_GROUP(he_dev->irq_head->isw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) case ITYPE_RBRQ_THRESH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) HPRINTK("rbrq%d threshold\n", group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) case ITYPE_RBRQ_TIMER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (he_service_rbrq(he_dev, group))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) he_service_rbpl(he_dev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) case ITYPE_TBRQ_THRESH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) HPRINTK("tbrq%d threshold\n", group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) case ITYPE_TPD_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) he_service_tbrq(he_dev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) case ITYPE_RBPL_THRESH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) he_service_rbpl(he_dev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) case ITYPE_RBPS_THRESH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* shouldn't happen unless small buffers enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) case ITYPE_PHY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) HPRINTK("phy interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #ifdef CONFIG_ATM_HE_USE_SUNI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) he_dev->atm_dev->phy->interrupt(he_dev->atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) case ITYPE_OTHER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) switch (type|group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) case ITYPE_PARITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) hprintk("parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) case ITYPE_ABORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) case ITYPE_TYPE(ITYPE_INVALID):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* see 8.1.1 -- check all queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) HPRINTK("isw not updated 0x%x\n", he_dev->irq_head->isw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) he_service_rbrq(he_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) he_service_rbpl(he_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) he_service_tbrq(he_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) hprintk("bad isw 0x%x?\n", he_dev->irq_head->isw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) he_dev->irq_head->isw = ITYPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) he_dev->irq_head = (struct he_irq *) NEXT_ENTRY(he_dev->irq_base, he_dev->irq_head, IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (updated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (updated > he_dev->irq_peak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) he_dev->irq_peak = updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) he_writel(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) IRQ_SIZE(CONFIG_IRQ_SIZE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) IRQ_THRESH(CONFIG_IRQ_THRESH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) IRQ_TAIL(he_dev->irq_tail), IRQ0_HEAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata; flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) he_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) struct he_dev *he_dev = (struct he_dev * )dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if (he_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) he_dev->irq_tail = (struct he_irq *) (((unsigned long)he_dev->irq_base) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) (*he_dev->irq_tailoffset << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (he_dev->irq_tail == he_dev->irq_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) HPRINTK("tailoffset not updated?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) he_dev->irq_tail = (struct he_irq *) ((unsigned long)he_dev->irq_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) ((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (he_dev->irq_head == he_dev->irq_tail /* && !IRQ_PENDING */)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) hprintk("spurious (or shared) interrupt?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (he_dev->irq_head != he_dev->irq_tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) tasklet_schedule(&he_dev->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) (void) he_readl(he_dev, INT_FIFO); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) __enqueue_tpd(struct he_dev *he_dev, struct he_tpd *tpd, unsigned cid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct he_tpdrq *new_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) HPRINTK("tpdrq %p cid 0x%x -> tpdrq_tail %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) tpd, cid, he_dev->tpdrq_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) /* new_tail = he_dev->tpdrq_tail; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) new_tail = (struct he_tpdrq *) ((unsigned long) he_dev->tpdrq_base |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) TPDRQ_MASK(he_dev->tpdrq_tail+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * check to see if we are about to set the tail == head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * if true, update the head pointer from the adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * to see if this is really the case (reading the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * head for every enqueue would be unnecessarily slow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (new_tail == he_dev->tpdrq_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) he_dev->tpdrq_head = (struct he_tpdrq *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) (((unsigned long)he_dev->tpdrq_base) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) TPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (new_tail == he_dev->tpdrq_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) hprintk("tpdrq full (cid 0x%x)\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) * FIXME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) * push tpd onto a transmit backlog queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * after service_tbrq, service the backlog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * for now, we just drop the pdu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) for (slot = 0; slot < TPD_MAXIOV; ++slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (tpd->iovec[slot].addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) dma_unmap_single(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) tpd->iovec[slot].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) tpd->iovec[slot].len & TPD_LEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (tpd->skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (tpd->vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) tpd->vcc->pop(tpd->vcc, tpd->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) dev_kfree_skb_any(tpd->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) atomic_inc(&tpd->vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dma_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) /* 2.1.5 transmit packet descriptor ready queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) list_add_tail(&tpd->entry, &he_dev->outstanding_tpds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) he_dev->tpdrq_tail->tpd = TPD_ADDR(tpd->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) he_dev->tpdrq_tail->cid = cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) he_dev->tpdrq_tail = new_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) (void) he_readl(he_dev, TPDRQ_T); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) he_open(struct atm_vcc *vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) struct he_dev *he_dev = HE_DEV(vcc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) struct he_vcc *he_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) unsigned cid, rsr0, rsr1, rsr4, tsr0, tsr0_aal, tsr4, period, reg, clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) short vpi = vcc->vpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) int vci = vcc->vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (vci == ATM_VCI_UNSPEC || vpi == ATM_VPI_UNSPEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) HPRINTK("open vcc %p %d.%d\n", vcc, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) set_bit(ATM_VF_ADDR, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) cid = he_mkcid(he_dev, vpi, vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) he_vcc = kmalloc(sizeof(struct he_vcc), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (he_vcc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) hprintk("unable to allocate he_vcc during open\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) INIT_LIST_HEAD(&he_vcc->buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) he_vcc->pdu_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) he_vcc->rc_index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) init_waitqueue_head(&he_vcc->rx_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) init_waitqueue_head(&he_vcc->tx_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) vcc->dev_data = he_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (vcc->qos.txtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) int pcr_goal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) pcr_goal = atm_pcr_goal(&vcc->qos.txtp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (pcr_goal == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) pcr_goal = he_dev->atm_dev->link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (pcr_goal < 0) /* means round down, technically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) pcr_goal = -pcr_goal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) HPRINTK("open tx cid 0x%x pcr_goal %d\n", cid, pcr_goal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) switch (vcc->qos.aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) tsr0_aal = TSR0_AAL5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) tsr4 = TSR4_AAL5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) tsr0_aal = TSR0_AAL0_SDU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) tsr4 = TSR4_AAL0_SDU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) goto open_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) tsr0 = he_readl_tsr0(he_dev, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (TSR0_CONN_STATE(tsr0) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) hprintk("cid 0x%x not idle (tsr0 = 0x%x)\n", cid, tsr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) goto open_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) switch (vcc->qos.txtp.traffic_class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) case ATM_UBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) /* 2.3.3.1 open connection ubr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) tsr0 = TSR0_UBR | TSR0_GROUP(0) | tsr0_aal |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) TSR0_USE_WMIN | TSR0_UPDATE_GER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) case ATM_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) /* 2.3.3.2 open connection cbr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* 8.2.3 cbr scheduler wrap problem -- limit to 90% total link rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) if ((he_dev->total_bw + pcr_goal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) > (he_dev->atm_dev->link_rate * 9 / 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) goto open_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) spin_lock_irqsave(&he_dev->global_lock, flags); /* also protects he_dev->cs_stper[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /* find an unused cs_stper register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) for (reg = 0; reg < HE_NUM_CS_STPER; ++reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (he_dev->cs_stper[reg].inuse == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) he_dev->cs_stper[reg].pcr == pcr_goal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (reg == HE_NUM_CS_STPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) goto open_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) he_dev->total_bw += pcr_goal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) he_vcc->rc_index = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ++he_dev->cs_stper[reg].inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) he_dev->cs_stper[reg].pcr = pcr_goal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) clock = he_is622(he_dev) ? 66667000 : 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) period = clock / pcr_goal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) HPRINTK("rc_index = %d period = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) reg, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) he_writel_mbox(he_dev, rate_to_atmf(period/2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) CS_STPER0 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) tsr0 = TSR0_CBR | TSR0_GROUP(0) | tsr0_aal |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) TSR0_RC_INDEX(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) goto open_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) he_writel_tsr0(he_dev, tsr0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) he_writel_tsr4(he_dev, tsr4 | 1, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) he_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) TSR1_PCR(rate_to_atmf(pcr_goal)), cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) he_writel_tsr2(he_dev, TSR2_ACR(rate_to_atmf(pcr_goal)), cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) he_writel_tsr9(he_dev, TSR9_OPEN_CONN, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) he_writel_tsr3(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) he_writel_tsr5(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) he_writel_tsr6(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) he_writel_tsr7(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) he_writel_tsr8(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) he_writel_tsr10(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) he_writel_tsr11(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) he_writel_tsr12(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) he_writel_tsr13(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) he_writel_tsr14(he_dev, 0x0, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) (void) he_readl_tsr0(he_dev, cid); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) unsigned aal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) HPRINTK("open rx cid 0x%x (rx_waitq %p)\n", cid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) &HE_VCC(vcc)->rx_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) switch (vcc->qos.aal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) case ATM_AAL5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) aal = RSR0_AAL5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) case ATM_AAL0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) aal = RSR0_RAWCELL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) goto open_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) rsr0 = he_readl_rsr0(he_dev, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (rsr0 & RSR0_OPEN_CONN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) hprintk("cid 0x%x not idle (rsr0 = 0x%x)\n", cid, rsr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) goto open_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) rsr1 = RSR1_GROUP(0) | RSR1_RBPL_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) rsr4 = RSR4_GROUP(0) | RSR4_RBPL_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) rsr0 = vcc->qos.rxtp.traffic_class == ATM_UBR ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) (RSR0_EPD_ENABLE|RSR0_PPD_ENABLE) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #ifdef USE_CHECKSUM_HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (vpi == 0 && vci >= ATM_NOT_RSV_VCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) rsr0 |= RSR0_TCP_CKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) he_writel_rsr4(he_dev, rsr4, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) he_writel_rsr1(he_dev, rsr1, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /* 5.1.11 last parameter initialized should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) the open/closed indication in rsr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) he_writel_rsr0(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) rsr0 | RSR0_START_PDU | RSR0_OPEN_CONN | aal, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) open_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) kfree(he_vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) clear_bit(ATM_VF_ADDR, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) set_bit(ATM_VF_READY, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) he_close(struct atm_vcc *vcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) DECLARE_WAITQUEUE(wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct he_dev *he_dev = HE_DEV(vcc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) struct he_tpd *tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) unsigned cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) struct he_vcc *he_vcc = HE_VCC(vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #define MAX_RETRY 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) int retry = 0, sleep = 1, tx_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) HPRINTK("close vcc %p %d.%d\n", vcc, vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) clear_bit(ATM_VF_READY, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) HPRINTK("close rx cid 0x%x\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* 2.7.2.2 close receive operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* wait for previous close (if any) to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) while (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) HPRINTK("close cid 0x%x RCC_BUSY\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) udelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) add_wait_queue(&he_vcc->rx_waitq, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) he_writel_rsr0(he_dev, RSR0_CLOSE_CONN, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) he_writel_mbox(he_dev, cid, RXCON_CLOSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) timeout = schedule_timeout(30*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) remove_wait_queue(&he_vcc->rx_waitq, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) hprintk("close rx timeout cid 0x%x\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) HPRINTK("close rx cid 0x%x complete\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) if (vcc->qos.txtp.traffic_class != ATM_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) volatile unsigned tsr4, tsr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) HPRINTK("close tx cid 0x%x\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /* 2.1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * ... the host must first stop queueing packets to the TPDRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) * on the connection to be closed, then wait for all outstanding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) * packets to be transmitted and their buffers returned to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) * TBRQ. When the last packet on the connection arrives in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) * TBRQ, the host issues the close command to the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) while (((tx_inuse = refcount_read(&sk_atm(vcc)->sk_wmem_alloc)) > 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) (retry < MAX_RETRY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) msleep(sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (sleep < 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) sleep = sleep * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) ++retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if (tx_inuse > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) hprintk("close tx cid 0x%x tx_inuse = %d\n", cid, tx_inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /* 2.3.1.1 generic close operations with flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) he_writel_tsr4_upper(he_dev, TSR4_FLUSH_CONN, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* also clears TSR4_SESSION_ENDED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) switch (vcc->qos.txtp.traffic_class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) case ATM_UBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) he_writel_tsr1(he_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) TSR1_MCR(rate_to_atmf(200000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) | TSR1_PCR(0), cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) case ATM_CBR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) he_writel_tsr14_upper(he_dev, TSR14_DELETE, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) (void) he_readl_tsr4(he_dev, cid); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) tpd = __alloc_tpd(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (tpd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) hprintk("close tx he_alloc_tpd failed cid 0x%x\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) goto close_tx_incomplete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) tpd->status |= TPD_EOS | TPD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) tpd->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) tpd->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) add_wait_queue(&he_vcc->tx_waitq, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) __enqueue_tpd(he_dev, tpd, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) timeout = schedule_timeout(30*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) remove_wait_queue(&he_vcc->tx_waitq, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) hprintk("close tx timeout cid 0x%x\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) goto close_tx_incomplete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) while (!((tsr4 = he_readl_tsr4(he_dev, cid)) & TSR4_SESSION_ENDED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) HPRINTK("close tx cid 0x%x !TSR4_SESSION_ENDED (tsr4 = 0x%x)\n", cid, tsr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) udelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) while (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) HPRINTK("close tx cid 0x%x TSR0_CONN_STATE != 0 (tsr0 = 0x%x)\n", cid, tsr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) udelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) close_tx_incomplete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (vcc->qos.txtp.traffic_class == ATM_CBR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) int reg = he_vcc->rc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) HPRINTK("cs_stper reg = %d\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) if (he_dev->cs_stper[reg].inuse == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) hprintk("cs_stper[%d].inuse = 0!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) --he_dev->cs_stper[reg].inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) he_dev->total_bw -= he_dev->cs_stper[reg].pcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) HPRINTK("close tx cid 0x%x complete\n", cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) kfree(he_vcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) clear_bit(ATM_VF_ADDR, &vcc->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) he_send(struct atm_vcc *vcc, struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) struct he_dev *he_dev = HE_DEV(vcc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) unsigned cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) struct he_tpd *tpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #ifdef USE_SCATTERGATHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) int i, slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #define HE_TPD_BUFSIZE 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) HPRINTK("send %d.%d\n", vcc->vpi, vcc->vci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) if ((skb->len > HE_TPD_BUFSIZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ((vcc->qos.aal == ATM_AAL0) && (skb->len != ATM_AAL0_SDU))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) hprintk("buffer too large (or small) -- %d bytes\n", skb->len );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) #ifndef USE_SCATTERGATHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (skb_shinfo(skb)->nr_frags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) hprintk("no scatter/gather support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) tpd = __alloc_tpd(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) if (tpd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (vcc->qos.aal == ATM_AAL5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) tpd->status |= TPD_CELLTYPE(TPD_USERCELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) char *pti_clp = (void *) (skb->data + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) int clp, pti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) pti = (*pti_clp & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) clp = (*pti_clp & ATM_HDR_CLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) tpd->status |= TPD_CELLTYPE(pti);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (clp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) tpd->status |= TPD_CLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) skb_pull(skb, ATM_AAL0_SDU - ATM_CELL_PAYLOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #ifdef USE_SCATTERGATHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) tpd->iovec[slot].addr = dma_map_single(&he_dev->pci_dev->dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) skb_headlen(skb), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) tpd->iovec[slot].len = skb_headlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) ++slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if (slot == TPD_MAXIOV) { /* queue tpd; start new tpd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) tpd->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) tpd->skb = NULL; /* not the last fragment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) so dont ->push() yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) __enqueue_tpd(he_dev, tpd, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) tpd = __alloc_tpd(he_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if (tpd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (vcc->pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) vcc->pop(vcc, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) atomic_inc(&vcc->stats->tx_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) tpd->status |= TPD_USERCELL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) tpd->iovec[slot].addr = skb_frag_dma_map(&he_dev->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) tpd->iovec[slot].len = skb_frag_size(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) ++slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) tpd->iovec[slot - 1].len |= TPD_LST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) tpd->address0 = dma_map_single(&he_dev->pci_dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) tpd->length0 = skb->len | TPD_LST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) tpd->status |= TPD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) tpd->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) tpd->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) ATM_SKB(skb)->vcc = vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) __enqueue_tpd(he_dev, tpd, cid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) atomic_inc(&vcc->stats->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) he_ioctl(struct atm_dev *atm_dev, unsigned int cmd, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) struct he_dev *he_dev = HE_DEV(atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) struct he_ioctl_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) case HE_GET_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) if (copy_from_user(®, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) sizeof(struct he_ioctl_reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) switch (reg.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) case HE_REGTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (reg.addr >= HE_REGMAP_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) reg.val = he_readl(he_dev, reg.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) case HE_REGTYPE_RCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) reg.val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) he_readl_rcm(he_dev, reg.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) case HE_REGTYPE_TCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) reg.val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) he_readl_tcm(he_dev, reg.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) case HE_REGTYPE_MBOX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) reg.val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) he_readl_mbox(he_dev, reg.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (copy_to_user(arg, ®,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) sizeof(struct he_ioctl_reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) #ifdef CONFIG_ATM_HE_USE_SUNI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (atm_dev->phy && atm_dev->phy->ioctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) err = atm_dev->phy->ioctl(atm_dev, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #else /* CONFIG_ATM_HE_USE_SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) #endif /* CONFIG_ATM_HE_USE_SUNI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) he_phy_put(struct atm_dev *atm_dev, unsigned char val, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) struct he_dev *he_dev = HE_DEV(atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) HPRINTK("phy_put(val 0x%x, addr 0x%lx)\n", val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) he_writel(he_dev, val, FRAMER + (addr*4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) (void) he_readl(he_dev, FRAMER + (addr*4)); /* flush posted writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) he_phy_get(struct atm_dev *atm_dev, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) struct he_dev *he_dev = HE_DEV(atm_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) reg = he_readl(he_dev, FRAMER + (addr*4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) HPRINTK("phy_get(addr 0x%lx) =0x%x\n", addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) he_proc_read(struct atm_dev *dev, loff_t *pos, char *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) struct he_dev *he_dev = HE_DEV(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) int left, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #ifdef notdef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) struct he_rbrq *rbrq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) struct he_tpdrq *tpdrq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) int rbpl_head, rbpl_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static long mcc = 0, oec = 0, dcc = 0, cec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) left = *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) return sprintf(page, "ATM he driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) return sprintf(page, "%s%s\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) he_dev->prod_id, he_dev->media & 0x40 ? "SM" : "MM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) return sprintf(page, "Mismatched Cells VPI/VCI Not Open Dropped Cells RCM Dropped Cells\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) spin_lock_irqsave(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) mcc += he_readl(he_dev, MCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) oec += he_readl(he_dev, OEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) dcc += he_readl(he_dev, DCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) cec += he_readl(he_dev, CEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) spin_unlock_irqrestore(&he_dev->global_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) return sprintf(page, "%16ld %16ld %13ld %17ld\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) mcc, oec, dcc, cec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) return sprintf(page, "irq_size = %d inuse = ? peak = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) CONFIG_IRQ_SIZE, he_dev->irq_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) return sprintf(page, "tpdrq_size = %d inuse = ?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) CONFIG_TPDRQ_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) return sprintf(page, "rbrq_size = %d inuse = ? peak = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) CONFIG_RBRQ_SIZE, he_dev->rbrq_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) return sprintf(page, "tbrq_size = %d peak = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) CONFIG_TBRQ_SIZE, he_dev->tbrq_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) #ifdef notdef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) rbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) rbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) inuse = rbpl_head - rbpl_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) if (inuse < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) inuse += CONFIG_RBPL_SIZE * sizeof(struct he_rbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) inuse /= sizeof(struct he_rbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) return sprintf(page, "rbpl_size = %d inuse = %d\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) CONFIG_RBPL_SIZE, inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return sprintf(page, "rate controller periods (cbr)\n pcr #vc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) for (i = 0; i < HE_NUM_CS_STPER; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) return sprintf(page, "cs_stper%-2d %8ld %3d\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) he_dev->cs_stper[i].pcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) he_dev->cs_stper[i].inuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) if (!left--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) return sprintf(page, "total bw (cbr): %d (limit %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) he_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) /* eeprom routines -- see 4.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) static u8 read_prom_byte(struct he_dev *he_dev, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) u32 val = 0, tmp_read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) int i, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) u8 byte_read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) val = readl(he_dev->membase + HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) val &= 0xFFFFE0FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) /* Turn on write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) val |= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) he_writel(he_dev, val, HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) /* Send READ instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) for (i = 0; i < ARRAY_SIZE(readtab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) he_writel(he_dev, val | readtab[i], HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) udelay(EEPROM_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) /* Next, we need to send the byte address to read from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) for (i = 7; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) udelay(EEPROM_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) udelay(EEPROM_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) val &= 0xFFFFF7FF; /* Turn off write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) he_writel(he_dev, val, HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) /* Now, we can read data from the EEPROM by clocking it in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) for (i = 7; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) udelay(EEPROM_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) tmp_read = he_readl(he_dev, HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) byte_read |= (unsigned char)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) ((tmp_read & ID_DOUT) >> ID_DOFFSET << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) udelay(EEPROM_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) he_writel(he_dev, val | ID_CS, HOST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) udelay(EEPROM_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) return byte_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) MODULE_AUTHOR("chas williams <chas@cmf.nrl.navy.mil>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) MODULE_DESCRIPTION("ForeRunnerHE ATM Adapter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) module_param(disable64, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) MODULE_PARM_DESC(disable64, "disable 64-bit pci bus transfers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) module_param(nvpibits, short, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) MODULE_PARM_DESC(nvpibits, "numbers of bits for vpi (default 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) module_param(nvcibits, short, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) MODULE_PARM_DESC(nvcibits, "numbers of bits for vci (default 12)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) module_param(rx_skb_reserve, short, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) MODULE_PARM_DESC(rx_skb_reserve, "padding for receive skb (default 16)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) module_param(irq_coalesce, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) MODULE_PARM_DESC(irq_coalesce, "use interrupt coalescing (default 1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) module_param(sdh, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) MODULE_PARM_DESC(sdh, "use SDH framing (default 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static const struct pci_device_id he_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) { PCI_VDEVICE(FORE, PCI_DEVICE_ID_FORE_HE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) MODULE_DEVICE_TABLE(pci, he_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static struct pci_driver he_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .name = "he",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .probe = he_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .remove = he_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .id_table = he_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) module_pci_driver(he_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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