^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _FORE200E_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _FORE200E_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* rx buffer sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAX_PDU_SIZE 65535 /* maximum PDU size supported by AALs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BUFFER_S1_NBR (RBD_BLK_SIZE * 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BUFFER_L1_NBR (RBD_BLK_SIZE * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BUFFER_S2_NBR (RBD_BLK_SIZE * 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BUFFER_L2_NBR (RBD_BLK_SIZE * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QUEUE_SIZE_CMD 16 /* command queue capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QUEUE_SIZE_RX 64 /* receive queue capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QUEUE_SIZE_TX 256 /* transmit queue capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QUEUE_SIZE_BS 32 /* buffer supply queue capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FORE200E_VPI_BITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FORE200E_VCI_BITS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TSD_FIXED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TSD_EXTENSION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TSD_NBR (TSD_FIXED + TSD_EXTENSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* the cp starts putting a received PDU into one *small* buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) then it uses a number of *large* buffers for the trailing data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) we compute here the total number of receive segment descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) required to hold the largest possible PDU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RSD_FIXED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) so we add one extra RSD to RSD_EXTENSION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RSD_NBR (RSD_FIXED + RSD_EXTENSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* bitfields endian games */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #if defined(__LITTLE_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BITFIELD2(b1, b2) b1; b2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BITFIELD3(b1, b2, b3) b1; b2; b3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #elif defined(__BIG_ENDIAN_BITFIELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BITFIELD2(b1, b2) b2; b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BITFIELD3(b1, b2, b3) b3; b2; b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #error unknown bitfield endianess
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* ATM cell header (minus HEC byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) typedef struct atm_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BITFIELD5(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 clp : 1, /* cell loss priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 plt : 3, /* payload type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 vci : 16, /* virtual channel identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 vpi : 8, /* virtual path identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 gfc : 4 /* generic flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } atm_header_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* ATM adaptation layer id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) typedef enum fore200e_aal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FORE200E_AAL0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FORE200E_AAL34 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FORE200E_AAL5 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } fore200e_aal_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* transmit PDU descriptor specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) typedef struct tpd_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) BITFIELD4(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 length : 16, /* total PDU length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 nseg : 8, /* number of transmit segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum fore200e_aal aal : 4, /* adaptation layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 intr : 4 /* interrupt requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } tpd_spec_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* transmit PDU rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) typedef struct tpd_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) BITFIELD2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 idle_cells : 16, /* number of idle cells to insert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 data_cells : 16 /* number of data cells to transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } tpd_rate_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* transmit segment descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) typedef struct tsd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 buffer; /* transmit buffer DMA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 length; /* number of bytes in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } tsd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* transmit PDU descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) typedef struct tpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct atm_header atm_header; /* ATM header minus HEC byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct tpd_spec spec; /* tpd specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct tpd_rate rate; /* tpd rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 pad; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } tpd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* receive segment descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) typedef struct rsd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 handle; /* host supplied receive buffer handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 length; /* number of bytes in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } rsd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* receive PDU descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) typedef struct rpd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct atm_header atm_header; /* ATM header minus HEC byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 nseg; /* number of receive segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } rpd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* buffer scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) typedef enum buffer_scheme {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) BUFFER_SCHEME_ONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) BUFFER_SCHEME_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BUFFER_SCHEME_NBR /* always last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } buffer_scheme_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* buffer magnitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) typedef enum buffer_magn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) BUFFER_MAGN_SMALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BUFFER_MAGN_LARGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) BUFFER_MAGN_NBR /* always last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } buffer_magn_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* receive buffer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) typedef struct rbd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 handle; /* host supplied handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 buffer_haddr; /* host DMA address of host buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } rbd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* receive buffer descriptor block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) typedef struct rbd_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } rbd_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* tpd DMA address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) typedef struct tpd_haddr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) BITFIELD3(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 size : 4, /* tpd size expressed in 32 byte blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 pad : 1, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } tpd_haddr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TPD_HADDR_SHIFT 5 /* addr aligned on 32 byte boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* cp resident transmit queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) typedef struct cp_txq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct tpd_haddr tpd_haddr; /* host DMA address of tpd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 status_haddr; /* host DMA address of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } cp_txq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* cp resident receive queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) typedef struct cp_rxq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 rpd_haddr; /* host DMA address of rpd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 status_haddr; /* host DMA address of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } cp_rxq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* cp resident buffer supply queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) typedef struct cp_bsq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 rbd_block_haddr; /* host DMA address of rbd block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 status_haddr; /* host DMA address of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } cp_bsq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) typedef volatile enum status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) STATUS_PENDING = (1<<0), /* initial status (written by host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) STATUS_FREE = (1<<2), /* initial status (written by host) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) STATUS_ERROR = (1<<3) /* completion status (written by cp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } status_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* cp operation code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) typedef enum opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) OPCODE_INITIALIZE = 1, /* initialize board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) OPCODE_GET_STATS, /* get board statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) OPCODE_SET_OC3, /* set OC-3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) OPCODE_GET_OC3, /* get OC-3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) OPCODE_RESET_STATS, /* reset board statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) firmware to be low order bits from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) the VPI field of the ATM cell header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } opcode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* virtual path / virtual channel identifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) typedef struct vpvc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) BITFIELD3(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 vci : 16, /* virtual channel identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 vpi : 8, /* virtual path identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 pad : 8 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } vpvc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* activate VC command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) typedef struct activate_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) BITFIELD4(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum opcode opcode : 8, /* cp opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) enum fore200e_aal aal : 8, /* adaptation layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum buffer_scheme scheme : 8, /* buffer scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 pad : 8 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } activate_opcode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* activate VC command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) typedef struct activate_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct activate_opcode opcode; /* activate VC command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct vpvc vpvc; /* VPI/VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 mtu; /* for AAL0 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } activate_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* deactivate VC command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) typedef struct deactivate_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) BITFIELD2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum opcode opcode : 8, /* cp opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 pad : 24 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } deactivate_opcode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* deactivate VC command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) typedef struct deactivate_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct deactivate_opcode opcode; /* deactivate VC command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct vpvc vpvc; /* VPI/VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } deactivate_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* OC-3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) typedef struct oc3_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) Saturn User Network Interface documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for a description of the OC-3 chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } oc3_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* set/get OC-3 regs command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) typedef struct oc3_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) BITFIELD4(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) enum opcode opcode : 8, /* cp opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 reg : 8, /* register index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 value : 8, /* register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 mask : 8 /* register mask that specifies which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bits of the register value field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) are significant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } oc3_opcode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* set/get OC-3 regs command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) typedef struct oc3_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 regs_haddr; /* host DMA address of OC-3 regs buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } oc3_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* physical encoding statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) typedef struct stats_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) __be32 crc_header_errors; /* cells received with bad header CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __be32 framing_errors; /* cells received with bad framing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) __be32 pad[ 2 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } stats_phy_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* OC-3 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) typedef struct stats_oc3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __be32 section_bip8_errors; /* section 8 bit interleaved parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __be32 path_bip8_errors; /* path 8 bit interleaved parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __be32 line_bip24_errors; /* line 24 bit interleaved parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __be32 line_febe_errors; /* line far end block errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __be32 path_febe_errors; /* path far end block errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __be32 corr_hcs_errors; /* correctable header check sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __be32 ucorr_hcs_errors; /* uncorrectable header check sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __be32 pad[ 1 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } stats_oc3_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* ATM statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) typedef struct stats_atm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) __be32 cells_transmitted; /* cells transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __be32 cells_received; /* cells received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __be32 vpi_bad_range; /* cell drops: VPI out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __be32 vpi_no_conn; /* cell drops: no connection for VPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __be32 vci_bad_range; /* cell drops: VCI out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __be32 vci_no_conn; /* cell drops: no connection for VCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __be32 pad[ 2 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } stats_atm_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* AAL0 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) typedef struct stats_aal0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __be32 cells_transmitted; /* cells transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __be32 cells_received; /* cells received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) __be32 cells_dropped; /* cells dropped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __be32 pad[ 1 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } stats_aal0_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* AAL3/4 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) typedef struct stats_aal34 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __be32 cells_transmitted; /* cells transmitted from segmented PDUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __be32 cells_received; /* cells reassembled into PDUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) __be32 cells_crc_errors; /* payload CRC error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __be32 cells_protocol_errors; /* SAR or CS layer protocol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __be32 cells_dropped; /* cells dropped: partial reassembly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) __be32 cspdus_transmitted; /* CS PDUs transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __be32 cspdus_received; /* CS PDUs received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __be32 cspdus_protocol_errors; /* CS layer protocol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __be32 cspdus_dropped; /* reassembled PDUs drop'd (in cells) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __be32 pad[ 3 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } stats_aal34_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* AAL5 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) typedef struct stats_aal5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __be32 cells_transmitted; /* cells transmitted from segmented SDUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __be32 cells_received; /* cells reassembled into SDUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __be32 cells_dropped; /* reassembled PDUs dropped (in cells) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __be32 congestion_experienced; /* CRC error and length wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __be32 cspdus_transmitted; /* CS PDUs transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) __be32 cspdus_received; /* CS PDUs received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __be32 cspdus_crc_errors; /* CS PDUs CRC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __be32 cspdus_protocol_errors; /* CS layer protocol errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) __be32 cspdus_dropped; /* reassembled PDUs dropped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __be32 pad[ 3 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } stats_aal5_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* auxiliary statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) typedef struct stats_aux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) __be32 small_b1_failed; /* receive BD allocation failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __be32 large_b1_failed; /* receive BD allocation failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __be32 small_b2_failed; /* receive BD allocation failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __be32 large_b2_failed; /* receive BD allocation failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __be32 rpd_alloc_failed; /* receive PDU allocation failures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) __be32 receive_carrier; /* no carrier = 0, carrier = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) __be32 pad[ 2 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } stats_aux_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* whole statistics buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) typedef struct stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct stats_phy phy; /* physical encoding statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct stats_oc3 oc3; /* OC-3 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct stats_atm atm; /* ATM statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct stats_aal0 aal0; /* AAL0 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct stats_aal34 aal34; /* AAL3/4 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct stats_aal5 aal5; /* AAL5 statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct stats_aux aux; /* auxiliary statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } stats_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* get statistics command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) typedef struct stats_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) BITFIELD2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) enum opcode opcode : 8, /* cp opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 pad : 24 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } stats_opcode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* get statistics command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) typedef struct stats_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct stats_opcode opcode; /* get statistics command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 stats_haddr; /* host DMA address of stats buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } stats_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* expansion PROM data (PCI specific) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) typedef struct prom_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 hw_revision; /* hardware revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 serial_number; /* board serial number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 mac_addr[ 8 ]; /* board MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } prom_data_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* get expansion PROM data command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) typedef struct prom_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) BITFIELD2(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) enum opcode opcode : 8, /* cp opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 pad : 24 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } prom_opcode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* get expansion PROM data command block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) typedef struct prom_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct prom_opcode opcode; /* get PROM data command opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 prom_haddr; /* host DMA address of PROM buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) } prom_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* cp command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) typedef union cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum opcode opcode; /* operation code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct activate_block activate_block; /* activate VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct deactivate_block deactivate_block; /* deactivate VC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct stats_block stats_block; /* get statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct prom_block prom_block; /* get expansion PROM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct oc3_block oc3_block; /* get/set OC-3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 pad[ 4 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } cmd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* cp resident command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) typedef struct cp_cmdq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) union cmd cmd; /* command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 status_haddr; /* host DMA address of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 pad[ 3 ]; /* i960 padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } cp_cmdq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* host resident transmit queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) typedef struct host_txq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct cp_txq_entry __iomem *cp_entry; /* addr of cp resident tx queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) enum status* status; /* addr of host resident status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct tpd* tpd; /* addr of transmit PDU descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 tpd_dma; /* DMA address of tpd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct sk_buff* skb; /* related skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void* data; /* copy of misaligned data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned long incarn; /* vc_map incarnation when submitted for tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct fore200e_vc_map* vc_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } host_txq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* host resident receive queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) typedef struct host_rxq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct cp_rxq_entry __iomem *cp_entry; /* addr of cp resident rx queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) enum status* status; /* addr of host resident status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct rpd* rpd; /* addr of receive PDU descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 rpd_dma; /* DMA address of rpd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } host_rxq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* host resident buffer supply queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) typedef struct host_bsq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct cp_bsq_entry __iomem *cp_entry; /* addr of cp resident buffer supply queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) enum status* status; /* addr of host resident status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 rbd_block_dma; /* DMA address od rdb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } host_bsq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* host resident command queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) typedef struct host_cmdq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct cp_cmdq_entry __iomem *cp_entry; /* addr of cp resident cmd queue entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) enum status *status; /* addr of host resident status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } host_cmdq_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* chunk of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) typedef struct chunk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void* alloc_addr; /* base address of allocated chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void* align_addr; /* base address of aligned chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dma_addr_t dma_addr; /* DMA address of aligned chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int direction; /* direction of DMA mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 alloc_size; /* length of allocated chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 align_size; /* length of aligned chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } chunk_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define dma_size align_size /* DMA useable size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* host resident receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) typedef struct buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct buffer* next; /* next receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) enum buffer_scheme scheme; /* buffer scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) enum buffer_magn magn; /* buffer magnitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct chunk data; /* data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #ifdef FORE200E_BSQ_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned long index; /* buffer # in queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int supplied; /* 'buffer supplied' flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) } buffer_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #if (BITS_PER_LONG == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #else /* deal with 64 bit pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* host resident command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) typedef struct host_cmdq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int head; /* head of cmd queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct chunk status; /* array of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } host_cmdq_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* host resident transmit queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) typedef struct host_txq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int head; /* head of tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int tail; /* tail of tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct chunk tpd; /* array of tpds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct chunk status; /* arry of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int txing; /* number of pending PDUs in tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } host_txq_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* host resident receive queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) typedef struct host_rxq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int head; /* head of rx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct chunk rpd; /* array of rpds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct chunk status; /* array of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) } host_rxq_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* host resident buffer supply queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) typedef struct host_bsq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int head; /* head of buffer supply queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct chunk rbd_block; /* array of rbds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct chunk status; /* array of completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct buffer* buffer; /* array of rx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct buffer* freebuf; /* list of free rx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) volatile int freebuf_count; /* count of free rx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } host_bsq_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* header of the firmware image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) typedef struct fw_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __le32 magic; /* magic number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) __le32 version; /* firmware version id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __le32 load_offset; /* fw load offset in board memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) __le32 start_offset; /* fw execution start address in board memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } fw_header_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* receive buffer supply queues scheme specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) typedef struct bs_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 queue_length; /* queue capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 buffer_size; /* host buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 pool_size; /* number of rbds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 supply_blksize; /* num of rbds in I/O block (multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) of 4 between 4 and 124 inclusive) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } bs_spec_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* initialization command block (one-time command, not in cmd queue) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) typedef struct init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) enum opcode opcode; /* initialize command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) enum status status; /* related status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 receive_threshold; /* not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 num_connect; /* ATM connections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 cmd_queue_len; /* length of command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 tx_queue_len; /* length of transmit queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 rx_queue_len; /* length of receive queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 rsd_extension; /* number of extra 32 byte blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 tsd_extension; /* number of extra 32 byte blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 conless_vpvc; /* not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 pad[ 2 ]; /* force quad alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } init_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) typedef enum media_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } media_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* cp resident queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) typedef struct cp_queues {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 cp_cmdq; /* command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 cp_txq; /* transmit queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u32 cp_rxq; /* receive queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u32 imask; /* 1 enables cp to host interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 istat; /* 1 for interrupt posted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 heap_base; /* offset form beginning of ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 heap_size; /* space available for queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 hlogger; /* non zero for host logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 heartbeat; /* cp heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 fw_release; /* firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 mon960_release; /* i960 monitor version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 tq_plen; /* transmit throughput measurements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* make sure the init block remains on a quad word boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct init_block init; /* one time cmd, not in cmd queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) enum media_type media_type; /* media type id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 oc3_revision; /* OC-3 revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } cp_queues_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* boot status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) typedef enum boot_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } boot_status_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* software UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) typedef struct soft_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 send; /* write register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 recv; /* read register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } soft_uart_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define FORE200E_CP_MONITOR_UART_FREE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* i960 monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) typedef struct cp_monitor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct soft_uart soft_uart; /* software UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) enum boot_status bstat; /* boot status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 app_base; /* application base offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u32 mon_version; /* i960 monitor version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) } cp_monitor_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) typedef enum fore200e_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) FORE200E_STATE_BLANK, /* initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) FORE200E_STATE_REGISTER, /* device registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) FORE200E_STATE_CONFIGURE, /* bus interface configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) FORE200E_STATE_MAP, /* board space mapped in host memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) FORE200E_STATE_RESET, /* board resetted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) FORE200E_STATE_START_FW, /* firmware started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) FORE200E_STATE_INITIALIZE, /* initialize command successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) FORE200E_STATE_INIT_CMDQ, /* command queue initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) FORE200E_STATE_INIT_RXQ, /* receive queue initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) FORE200E_STATE_IRQ, /* host interrupt requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) FORE200E_STATE_COMPLETE /* initialization completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } fore200e_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* PCA-200E registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) typedef struct fore200e_pca_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) volatile u32 __iomem * hcr; /* address of host control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) volatile u32 __iomem * imr; /* address of host interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) volatile u32 __iomem * psr; /* address of PCI specific register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) } fore200e_pca_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* SBA-200E registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) typedef struct fore200e_sba_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 __iomem *hcr; /* address of host control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u32 __iomem *bsr; /* address of burst transfer size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u32 __iomem *isr; /* address of interrupt level selection register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) } fore200e_sba_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* model-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) typedef union fore200e_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct fore200e_pca_regs pca; /* PCA-200E registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct fore200e_sba_regs sba; /* SBA-200E registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) } fore200e_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct fore200e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* bus-dependent data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) typedef struct fore200e_bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) char* model_name; /* board model name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) char* proc_name; /* board name under /proc/atm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int buffer_alignment; /* rx buffers DMA alignment requirement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int status_alignment; /* status words DMA alignment requirement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 (*read)(volatile u32 __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) void (*write)(u32, volatile u32 __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int (*configure)(struct fore200e*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int (*map)(struct fore200e*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) void (*reset)(struct fore200e*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int (*prom_read)(struct fore200e*, struct prom_data*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) void (*unmap)(struct fore200e*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) void (*irq_enable)(struct fore200e*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int (*irq_check)(struct fore200e*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) void (*irq_ack)(struct fore200e*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int (*proc_read)(struct fore200e*, char*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } fore200e_bus_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* vc mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) typedef struct fore200e_vc_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct atm_vcc* vcc; /* vcc entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned long incarn; /* vcc incarnation number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } fore200e_vc_map_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define FORE200E_VC_MAP(fore200e, vpi, vci) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* per-device data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) typedef struct fore200e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct list_head entry; /* next device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) const struct fore200e_bus* bus; /* bus-dependent code and data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) union fore200e_regs regs; /* bus-dependent registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct atm_dev* atm_dev; /* ATM device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) enum fore200e_state state; /* device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) char name[16]; /* device name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int irq; /* irq number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned long phys_base; /* physical base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) void __iomem * virt_base; /* virtual base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) unsigned char esi[ ESI_LEN ]; /* end system identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct cp_monitor __iomem * cp_monitor; /* i960 monitor address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct cp_queues __iomem * cp_queues; /* cp resident queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct host_cmdq host_cmdq; /* host resident cmd queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct host_txq host_txq; /* host resident tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct host_rxq host_rxq; /* host resident rx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* host resident buffer supply queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 available_cell_rate; /* remaining pseudo-CBR bw on link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int loop_mode; /* S/UNI loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct stats* stats; /* last snapshot of the stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct mutex rate_mtx; /* protects rate reservation ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) spinlock_t q_lock; /* protects queue ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #ifdef FORE200E_USE_TASKLET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct tasklet_struct tx_tasklet; /* performs tx interrupt work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct tasklet_struct rx_tasklet; /* performs rx interrupt work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned long tx_sat; /* tx queue saturation count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned long incarn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct fore200e_vc_map vc_map[ NBR_CONNECT ]; /* vc mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) } fore200e_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* per-vcc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) typedef struct fore200e_vcc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) enum buffer_scheme scheme; /* rx buffer scheme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct tpd_rate rate; /* tx rate control data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int rx_min_pdu; /* size of smallest PDU received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int rx_max_pdu; /* size of largest PDU received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int tx_min_pdu; /* size of smallest PDU transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int tx_max_pdu; /* size of largest PDU transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) unsigned long tx_pdu; /* nbr of tx pdus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) unsigned long rx_pdu; /* nbr of rx pdus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) } fore200e_vcc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* 200E-series common memory layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define FORE200E_CP_MONITOR_OFFSET 0x00000400 /* i960 monitor interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define FORE200E_CP_QUEUES_OFFSET 0x00004d40 /* cp resident queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* PCA-200E memory layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define PCA200E_IOSPACE_LENGTH 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define PCA200E_HCR_OFFSET 0x00100000 /* board control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define PCA200E_IMR_OFFSET 0x00100004 /* host IRQ mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define PCA200E_PSR_OFFSET 0x00100008 /* PCI specific register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* PCA-200E host control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define PCA200E_HCR_RESET (1<<0) /* read / write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define PCA200E_HCR_I960FAIL (1<<2) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define PCA200E_HCR_INTRB (1<<2) /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define PCA200E_HCR_INTRA (1<<3) /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define PCA200E_HCR_OUTFULL (1<<4) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define PCA200E_HCR_CLRINTR (1<<4) /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define PCA200E_HCR_ESPHOLD (1<<5) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define PCA200E_HCR_INFULL (1<<6) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define PCA200E_HCR_TESTMODE (1<<7) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* PCA-200E PCI bus interface regs (offsets in PCI config space) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define PCA200E_PCI_THRESHOLD 0x42 /* burst / continuous req threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* PBI master control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define SBA200E_PROM_NAME "FORE,sba-200e" /* device name in openprom tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* size of SBA-200E registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define SBA200E_HCR_LENGTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define SBA200E_BSR_LENGTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SBA200E_ISR_LENGTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define SBA200E_RAM_LENGTH 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* SBA-200E SBUS burst transfer size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define SBA200E_BSR_BURST4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define SBA200E_BSR_BURST8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define SBA200E_BSR_BURST16 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* SBA-200E host control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define SBA200E_HCR_I960FAIL (1<<2) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define SBA200E_HCR_I960SETINTR (1<<2) /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define SBA200E_HCR_OUTFULL (1<<3) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define SBA200E_HCR_INTR_CLR (1<<3) /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define SBA200E_HCR_ESPHOLD (1<<5) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define SBA200E_HCR_INFULL (1<<6) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define SBA200E_HCR_TESTMODE (1<<7) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define SBA200E_HCR_INTR_REQ (1<<8) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #endif /* _FORE200E_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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