^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/atm/firestream.h - FireStream 155 (MB86697) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FireStream 50 (MB86695) device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /***********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * first the defines for the chip. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ***********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /********************* General chip parameters. ************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FS_NR_FREE_POOLS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FS_NR_RX_QUEUES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /********************* queues and queue access macros ******************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* A queue entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct FS_QENTRY {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 p0, p1, p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* A freepool entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct FS_BPENTRY {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 bsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 aal_bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* The hardware doesn't look at this, but we need the SKB somewhere... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct freepool *fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct fs_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STATUS_CODE(qe) ((qe->cmd >> 22) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* OFFSETS against the base of a QUEUE... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QSA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QEA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QRP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QWP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QCNF 0x10 /* Only for Release queues! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Not for the transmit pending queue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* OFFSETS against the base of a FREE POOL... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FPCNF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FPSA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FPEA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FPCNT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FPCTU 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define Q_SA(b) (b + QSA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define Q_EA(b) (b + QEA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define Q_RP(b) (b + QRP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define Q_WP(b) (b + QWP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define Q_CNF(b) (b + QCNF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FP_CNF(b) (b + FPCNF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FP_SA(b) (b + FPSA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FP_EA(b) (b + FPEA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FP_CNT(b) (b + FPCNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FP_CTU(b) (b + FPCTU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* bits in a queue register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define Q_FULL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define Q_EMPTY 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define Q_INCWRAP 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define Q_ADDR_MASK 0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* bits in a FreePool config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RBFP_RBS (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RBFP_RBSVAL (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RBFP_CME (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RBFP_DLP (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RBFP_BFPWT (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* FireStream commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QE_CMD_NULL (0x00 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QE_CMD_REG_RD (0x01 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QE_CMD_REG_RDM (0x02 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QE_CMD_REG_WR (0x03 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QE_CMD_REG_WRM (0x04 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QE_CMD_CONFIG_TX (0x05 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QE_CMD_CONFIG_RX (0x06 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QE_CMD_PRP_RD (0x07 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QE_CMD_PRP_RDM (0x2a << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QE_CMD_PRP_WR (0x09 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QE_CMD_PRP_WRM (0x2b << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QE_CMD_RX_EN (0x0a << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QE_CMD_RX_PURGE (0x0b << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QE_CMD_RX_PURGE_INH (0x0c << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QE_CMD_TX_EN (0x0d << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QE_CMD_TX_PURGE (0x0e << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QE_CMD_TX_PURGE_INH (0x0f << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QE_CMD_RST_CG (0x10 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QE_CMD_SET_CG (0x11 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QE_CMD_RST_CLP (0x12 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QE_CMD_SET_CLP (0x13 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QE_CMD_OVERRIDE (0x14 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QE_CMD_ADD_BFP (0x15 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QE_CMD_DUMP_TX (0x16 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QE_CMD_DUMP_RX (0x17 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QE_CMD_LRAM_RD (0x18 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QE_CMD_LRAM_RDM (0x28 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QE_CMD_LRAM_WR (0x19 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QE_CMD_LRAM_WRM (0x29 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QE_CMD_LRAM_BSET (0x1a << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QE_CMD_LRAM_BCLR (0x1b << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QE_CMD_CONFIG_SEGM (0x1c << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QE_CMD_READ_SEGM (0x1d << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QE_CMD_CONFIG_ROUT (0x1e << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QE_CMD_READ_ROUT (0x1f << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QE_CMD_CONFIG_TM (0x20 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define QE_CMD_READ_TM (0x21 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define QE_CMD_CONFIG_TXBM (0x22 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QE_CMD_READ_TXBM (0x23 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QE_CMD_CONFIG_RXBM (0x24 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QE_CMD_READ_RXBM (0x25 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define QE_CMD_CONFIG_REAS (0x26 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QE_CMD_READ_REAS (0x27 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QE_TRANSMIT_DE (0x0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QE_CMD_LINKED (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QE_CMD_IMM (0x2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QE_CMD_IMM_INQ (0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TD_EPI (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TD_COMMAND (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TD_DATA (0x0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TD_RM_CELL (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TD_OAM_CELL (0x2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TD_OAM_CELL_SEGMENT (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TD_BPI (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FP_FLAGS_EPI (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TX_PQ(i) (0x00 + (i) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TXB_RQ (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ST_Q (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RXB_FP(i) (0x90 + (i) * 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RXB_RQ(i) (0x134 + (i) * 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TXQ_HP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TXQ_LP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Phew. You don't want to know how many revisions these simple queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * address macros went through before I got them nice and compact as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * they are now. -- REW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* And now for something completely different:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * The rest of the registers... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CMDR0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CMDR1 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CMDR2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CMDR3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SARMODE0 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SARMODE0_TXVCS_0 (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SARMODE0_TXVCS_1k (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SARMODE0_TXVCS_2k (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SARMODE0_TXVCS_4k (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SARMODE0_TXVCS_8k (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SARMODE0_TXVCS_16k (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SARMODE0_TXVCS_32k (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SARMODE0_TXVCS_64k (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SARMODE0_TXVCS_32 (0x8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SARMODE0_ABRVCS_0 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SARMODE0_ABRVCS_512 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SARMODE0_ABRVCS_1k (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SARMODE0_ABRVCS_2k (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SARMODE0_ABRVCS_4k (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SARMODE0_ABRVCS_8k (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SARMODE0_ABRVCS_16k (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SARMODE0_ABRVCS_32k (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SARMODE0_ABRVCS_32 (0x9 << 4) /* The others are "8", this one really has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) be 9. Tell me you don't believe me. -- REW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SARMODE0_RXVCS_0 (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SARMODE0_RXVCS_1k (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SARMODE0_RXVCS_2k (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SARMODE0_RXVCS_4k (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SARMODE0_RXVCS_8k (0x4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SARMODE0_RXVCS_16k (0x5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SARMODE0_RXVCS_32k (0x6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SARMODE0_RXVCS_64k (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SARMODE0_RXVCS_32 (0x8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SARMODE0_CALSUP_1 (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SARMODE0_CALSUP_2 (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SARMODE0_CALSUP_3 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SARMODE0_CALSUP_4 (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SARMODE0_PRPWT_FS50_0 (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SARMODE0_PRPWT_FS50_2 (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SARMODE0_PRPWT_FS50_5 (0x2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SARMODE0_PRPWT_FS50_11 (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SARMODE0_PRPWT_FS155_0 (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SARMODE0_PRPWT_FS155_1 (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SARMODE0_PRPWT_FS155_2 (0x2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SARMODE0_PRPWT_FS155_3 (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SARMODE0_SRTS0 (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SARMODE0_SRTS1 (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SARMODE0_RUN (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SARMODE0_UNLOCK (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SARMODE0_CWRE (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SARMODE0_INTMODE_READCLEAR (0x0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SARMODE0_INTMODE_READNOCLEAR (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SARMODE0_INTMODE_READNOCLEARINHIBIT (0x2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SARMODE0_INTMODE_READCLEARINHIBIT (0x3 << 28) /* Tell me you don't believe me. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SARMODE0_GINT (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SARMODE0_SHADEN (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SARMODE1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SARMODE1_TRTL_SHIFT 0 /* Program to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SARMODE1_RRTL_SHIFT 4 /* Program to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SARMODE1_TAGM (0x1 << 8) /* Program to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SARMODE1_HECM0 (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SARMODE1_HECM1 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SARMODE1_HECM2 (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SARMODE1_GFCE (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SARMODE1_GFCR (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SARMODE1_PMS (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SARMODE1_GPRI (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SARMODE1_GPAS (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SARMODE1_GVAS (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SARMODE1_GNAM (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SARMODE1_GPLEN (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SARMODE1_DUMPE (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SARMODE1_OAMCRC (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SARMODE1_DCOAM (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SARMODE1_DCRM (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SARMODE1_TSTLP (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SARMODE1_DEFHEC (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ISR 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IUSR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMR 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ISR_LPCO (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ISR_DPCO (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ISR_RBRQ0_W (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ISR_RBRQ1_W (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ISR_RBRQ2_W (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ISR_RBRQ3_W (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ISR_RBRQ0_NF (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ISR_RBRQ1_NF (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ISR_RBRQ2_NF (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ISR_RBRQ3_NF (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ISR_BFP_SC (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ISR_INIT (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ISR_INIT_ERR (0x1 << 12) /* Documented as "reserved" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ISR_USCEO (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ISR_UPEC0 (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ISR_VPFCO (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ISR_CRCCO (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ISR_HECO (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ISR_TBRQ_W (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ISR_TBRQ_NF (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ISR_CTPQ_E (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ISR_GFC_C0 (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ISR_PCI_FTL (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ISR_CSQ_W (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ISR_CSQ_NF (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ISR_EXT_INT (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ISR_RXDMA_S (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TMCONF 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CALPRESCALE 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CELLOSCONF 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CELLOSCONF_COTS (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CELLOSCONF_CEN (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CELLOSCONF_SC8 (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CELLOSCONF_SC4 (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CELLOSCONF_SC2 (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CELLOSCONF_SC1 (0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CELLOSCONF_COBS (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CELLOSCONF_COPK (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CELLOSCONF_COST (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define RAS0 0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define RAS0_DCD_XHLT (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define RAS0_VPSEL (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define RAS0_VCSEL (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define RAS1 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define RAS1_UTREG (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DMAMR 0x1cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DMAMR_TX_MODE_FULL (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DMAMR_TX_MODE_PART (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DMAMR_TX_MODE_NONE (0x2 << 0) /* And 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define RAS2 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RAS2_NNI (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define RAS2_USEL (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define RAS2_UBS (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct fs_transmit_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 atm_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 TMC[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 rtag[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TC_FLAGS_AAL5 (0x0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TC_FLAGS_TRANSPARENT_PAYLOAD (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TC_FLAGS_TRANSPARENT_CELL (0x2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TC_FLAGS_STREAMING (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define TC_FLAGS_PACKET (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TC_FLAGS_TYPE_ABR (0x0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TC_FLAGS_TYPE_CBR (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define TC_FLAGS_TYPE_VBR (0x2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TC_FLAGS_TYPE_UBR (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TC_FLAGS_CAL0 (0x0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TC_FLAGS_CAL1 (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TC_FLAGS_CAL2 (0x2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TC_FLAGS_CAL3 (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define RC_FLAGS_NAM (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define RC_FLAGS_RXBM_PSB (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define RC_FLAGS_RXBM_CIF (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define RC_FLAGS_RXBM_PMB (0x2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define RC_FLAGS_RXBM_STR (0x4 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define RC_FLAGS_RXBM_SAF (0x6 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define RC_FLAGS_RXBM_POS (0x6 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define RC_FLAGS_BFPS (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define RC_FLAGS_BFPS_BFP (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define RC_FLAGS_BFPS_BFP0 (0x0 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define RC_FLAGS_BFPS_BFP1 (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define RC_FLAGS_BFPS_BFP2 (0x2 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define RC_FLAGS_BFPS_BFP3 (0x3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define RC_FLAGS_BFPS_BFP4 (0x4 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define RC_FLAGS_BFPS_BFP5 (0x5 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define RC_FLAGS_BFPS_BFP6 (0x6 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define RC_FLAGS_BFPS_BFP7 (0x7 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define RC_FLAGS_BFPS_BFP01 (0x8 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define RC_FLAGS_BFPS_BFP23 (0x9 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define RC_FLAGS_BFPS_BFP45 (0xa << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define RC_FLAGS_BFPS_BFP67 (0xb << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define RC_FLAGS_BFPS_BFP07 (0xc << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define RC_FLAGS_BFPS_BFP27 (0xd << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define RC_FLAGS_BFPS_BFP47 (0xe << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define RC_FLAGS_BFPP (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define RC_FLAGS_TEVC (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define RC_FLAGS_TEP (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define RC_FLAGS_AAL5 (0x0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define RC_FLAGS_TRANSP (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define RC_FLAGS_TRANSC (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define RC_FLAGS_ML (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define RC_FLAGS_TRBRM (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define RC_FLAGS_PRI (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define RC_FLAGS_HOAM (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define RC_FLAGS_CRC10 (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define RAC 0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define RAM 0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Then the datastructures that the DRIVER uses. *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TXQ_NENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define RXRQ_NENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct fs_vcc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int channo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) wait_queue_head_t close_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct sk_buff *last_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct FS_QENTRY *sa, *ea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct freepool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int nr_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct fs_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct fs_dev *next; /* other FS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned char irq; /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct pci_dev *pci_dev; /* PCI stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct atm_dev *atm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long hw_base; /* mem base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void __iomem *base; /* Mapping of base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int channo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct queue hp_txq, lp_txq, tx_relq, st_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct freepool rx_fp[FS_NR_FREE_POOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct queue rx_rq[FS_NR_RX_QUEUES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int nchannels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct atm_vcc **atm_vccs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) void *tx_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ntxpckts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Number of channesl that the FS50 supports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define FS50_CHANNEL_BITS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define FS50_NR_CHANNELS (1 << FS50_CHANNEL_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define FS_DEV(atm_dev) ((struct fs_dev *) (atm_dev)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define FS_VCC(atm_vcc) ((struct fs_vcc *) (atm_vcc)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define FS_IS50 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define FS_IS155 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define IS_FS50(dev) (dev->flags & FS_IS50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define IS_FS155(dev) (dev->flags & FS_IS155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Within limits this is user-configurable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Note: Currently the sum (10 -> 1k channels) is hardcoded in the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define FS155_VPI_BITS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define FS155_VCI_BITS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define FS155_CHANNEL_BITS (FS155_VPI_BITS + FS155_VCI_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define FS155_NR_CHANNELS (1 << FS155_CHANNEL_BITS)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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