^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/atm/eni.h - Efficient Networks ENI155P device driver declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DRIVER_ATM_ENI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRIVER_ATM_ENI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/atm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/atmdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sonet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "midway.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEV_LABEL "eni"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UBR_BUFFER (128*1024) /* UBR buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RX_DMA_BUF 8 /* burst and skip a few things */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TX_DMA_BUF 100 /* should be enough for 64 kB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DEFAULT_RX_MULT 300 /* max_sdu*3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DEFAULT_TX_MULT 300 /* max_sdu*3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ENI_ZEROES_SIZE 4 /* need that many DMA-able zero bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct eni_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *start; /* counting in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct eni_tx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *send; /* base, 0 if unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int prescaler; /* shaping prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int resolution; /* shaping divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long tx_pos; /* current TX write position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long words; /* size of TX queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int index; /* TX channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int reserved; /* reserved peak cell rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int shaping; /* shaped peak cell rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct sk_buff_head backlog; /* queue of waiting TX buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct eni_vcc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int (*rx)(struct atm_vcc *vcc); /* RX function, NULL if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *recv; /* receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long words; /* its size in words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long descr; /* next descriptor (RX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long rx_pos; /* current RX descriptor pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct eni_tx *tx; /* TXer, NULL if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int rxing; /* number of pending PDUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int servicing; /* number of waiting VCs (0 or 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int txing; /* number of pending TX bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ktime_t timestamp; /* for RX timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct atm_vcc *next; /* next pending RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct sk_buff *last; /* last PDU being DMAed (used to carry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) discard information) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct eni_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*-------------------------------- spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) spinlock_t lock; /* sync with interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct tasklet_struct task; /* tasklet for interrupt work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 events; /* pending events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*-------------------------------- base pointers into Midway address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *phy; /* PHY interface chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __iomem *reg; /* register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *ram; /* RAM base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __iomem *vci; /* VCI table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *rx_dma; /* RX DMA queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *tx_dma; /* TX DMA queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *service; /* service list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*-------------------------------- TX part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct eni_tx tx[NR_CHAN]; /* TX channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct eni_tx *ubr; /* UBR channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct sk_buff_head tx_queue; /* PDUs currently being TX DMAed*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) wait_queue_head_t tx_wait; /* for close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int tx_bw; /* remaining bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 dma[TX_DMA_BUF*2]; /* DMA request scratch area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct eni_zero { /* aligned "magic" zeroes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int tx_mult; /* buffer size multiplier (percent) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*-------------------------------- RX part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 serv_read; /* host service read index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct atm_vcc *fast,*last_fast;/* queues of VCCs with pending PDUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct atm_vcc *slow,*last_slow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct atm_vcc **rx_map; /* for fast lookups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sk_buff_head rx_queue; /* PDUs currently being RX-DMAed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) wait_queue_head_t rx_wait; /* for close */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int rx_mult; /* buffer size multiplier (percent) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*-------------------------------- statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long lost; /* number of lost cells (RX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*-------------------------------- memory management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long base_diff; /* virtual-real base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int free_len; /* free list length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct eni_free *free_list; /* free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int free_list_size; /* maximum size of free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*-------------------------------- ENI links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct atm_dev *more; /* other ENI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*-------------------------------- general information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int mem; /* RAM on board (in bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int asic; /* PCI interface type, 0 for FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int irq; /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct pci_dev *pci_dev; /* PCI stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ENI_DEV(d) ((struct eni_dev *) (d)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ENI_VCC(d) ((struct eni_vcc *) (d)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct eni_skb_prv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct atm_skb_data _; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long pos; /* position of next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int size; /* PDU size in reassembly buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dma_addr_t paddr; /* DMA handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ENI_PRV_SIZE(skb) (((struct eni_skb_prv *) (skb)->cb)->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ENI_PRV_POS(skb) (((struct eni_skb_prv *) (skb)->cb)->pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ENI_PRV_PADDR(skb) (((struct eni_skb_prv *) (skb)->cb)->paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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