^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Madge Ambassador ATM Adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) 1995-1999 Madge Networks Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef AMBASSADOR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define AMBASSADOR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef CONFIG_ATM_AMBASSADOR_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DEBUG_AMBASSADOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEV_LABEL "amb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef PCI_VENDOR_ID_MADGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_VENDOR_ID_MADGE 0x10B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_DEVICE_ID_MADGE_AMBASSADOR 0x1001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) // diagnostic output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PRINTK(severity,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) printk(severity DEV_LABEL ": " format "\n" , ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef DEBUG_AMBASSADOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DBG_ERR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DBG_WARN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DBG_INFO 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DBG_INIT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DBG_LOAD 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DBG_VCC 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DBG_QOS 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DBG_CMD 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DBG_TX 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DBG_RX 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DBG_SKB 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DBG_POOL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DBG_IRQ 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DBG_FLOW 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DBG_REGS 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DBG_DATA 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DBG_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* the ## prevents the annoying double expansion of the macro arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PRINTDB(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PRINTDM(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ( (debug & (bits)) ? printk (format , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PRINTDE(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PRINTD(bits,format,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PRINTD(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PRINTDB(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PRINTDM(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PRINTDE(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PRINTDD(bits,format,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PRINTDDB(sec,fmt,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PRINTDDM(sec,fmt,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PRINTDDE(sec,fmt,args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) // tunable values (?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* MUST be powers of two -- why ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define COM_Q_ENTRIES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TX_Q_ENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RX_Q_ENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) // fixed values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) // guessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AMB_EXTENT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) // Minimum allowed size for an Ambassador queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MIN_QUEUE_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) // Ambassador microcode allows 1 to 4 pools, we use 4 (simpler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NUM_RX_POOLS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) // minimum RX buffers required to cope with replenishing delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MIN_RX_BUFFERS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) // minimum PCI latency we will tolerate (32 IS TOO SMALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MIN_PCI_LATENCY 64 // 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) // VCs supported by card (VPI always 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NUM_VPI_BITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NUM_VCI_BITS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NUM_VCS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* The status field bits defined so far. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RX_ERR 0x8000 // always present if there is an error (hmm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CRC_ERR 0x4000 // AAL5 CRC error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LEN_ERR 0x2000 // overlength frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ABORT_ERR 0x1000 // zero length field in received frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define UNUSED_ERR 0x0800 // buffer returned unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) // Adaptor commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SRB_OPEN_VC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* par_0: dwordswap(VC_number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* flags: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* LANE: 0x0004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* NOT_UBR: 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* ABR: 0x0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* RxPool0: 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* RxPool1: 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* RxPool2: 0x0040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* RxPool3: 0x0060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SRB_CLOSE_VC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* par_0: dwordswap(VC_number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SRB_GET_BIA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* returns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* par_0: dwordswap(half BIA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* par_1: dwordswap(half BIA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SRB_GET_SUNI_STATS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* par_0: dwordswap(physical_host_address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SRB_SET_BITS_8 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SRB_SET_BITS_16 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SRB_SET_BITS_32 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SRB_CLEAR_BITS_8 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SRB_CLEAR_BITS_16 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SRB_CLEAR_BITS_32 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* par_0: dwordswap(ATMizer address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* par_1: dwordswap(mask) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SRB_SET_8 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SRB_SET_16 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SRB_SET_32 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* par_0: dwordswap(ATMizer address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* par_1: dwordswap(data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SRB_GET_32 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* par_0: dwordswap(ATMizer address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* returns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* par_1: dwordswap(ATMizer data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SRB_GET_VERSION 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* returns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* par_0: dwordswap(Major Version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* par_1: dwordswap(Minor Version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SRB_FLUSH_BUFFER_Q 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Only flags to define which buffer pool; all others must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* par_0: dwordswap(flags<<16) or wordswap(flags)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SRB_GET_DMA_SPEEDS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* returns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* par_0: dwordswap(Read speed (bytes/sec)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* par_1: dwordswap(Write speed (bytes/sec)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SRB_MODIFY_VC_RATE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* par_0: dwordswap(VC_number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SRB_MODIFY_VC_FLAGS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* par_0: dwordswap(VC_number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* flags: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* LANE: 0x0004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* NOT_UBR: 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* ABR: 0x0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* RxPool0: 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* RxPool1: 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* RxPool2: 0x0040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* RxPool3: 0x0060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SRB_RATE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SRB_POOL_SHIFT (SRB_FLAGS_SHIFT+5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SRB_FLAGS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SRB_STOP_TASKING 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SRB_START_TASKING 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SRB_SHUT_DOWN 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MAX_SRB 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SRB_COMPLETE 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TX_FRAME 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) // number of types of SRB MUST be a power of two -- why?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define NUM_OF_SRB 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) // number of bits of period info for rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MAX_RATE_BITS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TX_UBR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TX_UBR_CAPPED 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TX_ABR 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TX_FRAME_NOTCAP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TX_FRAME_CAPPED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FP_155_RATE 0x24b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FP_25_RATE 0x1f9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* #define VERSION_NUMBER 0x01000000 // initial release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* #define VERSION_NUMBER 0x01040000 // PLX bug work around version PLUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* remove race conditions on basic interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* indicate to the host that diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* have finished; if failed, how and what */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* fix host memory test to fix PLX bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* allow flash upgrade and BIA upgrade directly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Change in download algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DMA_VALID 0xb728e149 /* completely random */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FLASH_BASE 0xa0c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FLASH_SIZE 0x00020000 /* 128K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define BIA_BASE (FLASH_BASE+0x0001c000) /* Flash Sector 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BIA_ADDRESS ((void *)0xa0c1c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PLX_BASE 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) host_memory_test = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) read_adapter_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) write_adapter_memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) adapter_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) get_version_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) interrupt_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) flash_erase_sector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) adap_download_block = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) adap_erase_flash,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) adap_run_in_iram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) adap_end_download
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } loader_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define BAD_COMMAND (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define COMMAND_IN_PROGRESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define COMMAND_PASSED_TEST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define COMMAND_FAILED_TEST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define COMMAND_READ_DATA_OK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define COMMAND_READ_BAD_ADDRESS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define COMMAND_WRITE_DATA_OK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define COMMAND_WRITE_BAD_ADDRESS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define COMMAND_WRITE_FLASH_FAILURE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define COMMAND_COMPLETE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define COMMAND_FLASH_ERASE_FAILURE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define COMMAND_WRITE_BAD_DATA 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* bit fields for mailbox[0] return values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GPINT_TST_FAILURE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SUNI_DATA_PATTERN_FAILURE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SUNI_DATA_BITS_FAILURE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SUNI_UTOPIA_FAILURE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SUNI_FIFO_FAILURE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SRAM_FAILURE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SELF_TEST_FAILURE 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* mailbox[1] = 0 in progress, -1 on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* mailbox[4],mailbox[5],mailbox[6] random failure values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* PLX/etc. memory map including command structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* These registers may also be memory mapped in PCI memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define UNUSED_LOADER_MAILBOXES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 stuff[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 stuff[UNUSED_LOADER_MAILBOXES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } loader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 cmd_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 tx_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 rx_address[NUM_RX_POOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 gen_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } mb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 interrupt_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 reset_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } amb_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* RESET bit, IRQ (card to host) and doorbell (host to card) enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AMB_RESET_BITS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define AMB_INTERRUPT_BITS 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AMB_DOORBELL_BITS 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* loader commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MAX_COMMAND_DATA 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MAX_TRANSFER_DATA 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __be32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __be32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __be32 data[MAX_TRANSFER_DATA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } transfer_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __be32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __be32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) transfer_block transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) __be32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __be32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __be32 data[MAX_COMMAND_DATA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __be32 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } loader_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* command queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Again all data are BIG ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __be32 vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) __be32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) __be32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) } open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) __be32 vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __be32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } modify_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __be32 vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __be32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } modify_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __be32 vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) __be32 lower4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __be32 upper2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } bia;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) __be32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } suni;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __be32 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __be32 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __be32 read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __be32 write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __be32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __be32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __be32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __be32 par[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __be32 request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* transmit queues and associated structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* The hosts transmit structure. All BIG ENDIAN; host address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) restricted to first 1GByte, but address passed to the card must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) have the top MS bit or'ed in. -- check this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* TX is described by 1+ tx_frags followed by a tx_frag_end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __be32 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __be32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } tx_frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* apart from handle the fields here are for the adapter to play with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) and should be set to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u16 vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u16 next_descriptor_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 next_descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #ifdef AMB_NEW_MICROCODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 cpcs_uu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 cpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u16 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } tx_frag_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tx_frag tx_frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tx_frag_end tx_frag_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct sk_buff * skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) } tx_simple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) tx_frag fragment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tx_frag_end end_of_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } tx_descr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* this "points" to the sequence of fragments and trailer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __be16 vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __be16 tx_descr_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) __be32 tx_descr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } tx_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* handle is the handle from tx_in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } tx_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* receive frame structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* All BIG ENDIAN; handle is as passed from host; length is zero for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) aborted frames, and frames with errors. Header is actually VC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) number, lec-id is NOT yet supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __be16 vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __be16 lec_id; // unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __be16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __be16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } rx_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* buffer supply structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __be32 host_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } rx_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* This first structure is the area in host memory where the adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) writes its pointer values. These pointer values are BIG ENDIAN and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) reside in the same 4MB 'page' as this structure. The host gives the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) adapter the address of this block by sending a doorbell interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) to the adapter after downloading the code and setting it going. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) addresses have the top 10 bits set to 1010000010b -- really?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) The host must initialise these before handing the block to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) adapter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __be32 command_start; /* SRB commands completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) __be32 command_end; /* SRB commands completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __be32 tx_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __be32 tx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) __be32 txcom_start; /* tx completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __be32 txcom_end; /* tx completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __be32 buffer_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __be32 buffer_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 buffer_q_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 buffer_q_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 buffer_aptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __be32 rx_start; /* rx completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __be32 rx_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 rx_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __be32 buffer_size; /* size of host buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) } rec_struct[NUM_RX_POOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #ifdef AMB_NEW_MICROCODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 init_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u16 talk_block_spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } adap_talk_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* This structure must be kept in line with the vcr image in sarmain.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) This is the structure in the host filled in by the adapter by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GET_SUNI_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 racp_chcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 racp_uhcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u16 spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 racp_rcell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 tacp_tcell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 dropped_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 dropped_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } suni_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } amb_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define NEXTQ(current,start,limit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ( (current)+1 < (limit) ? (current)+1 : (start) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) command * start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) command * in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) command * out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) command * limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } amb_cq_ptrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned int high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int maximum; // size - 1 (q implementation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) amb_cq_ptrs ptrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) } amb_cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned int maximum; // size - 1 (q implementation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) tx_in * start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) tx_in * ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) tx_in * limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) tx_out * start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tx_out * ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) tx_out * limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) } amb_txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned int emptied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int maximum; // size - 1 (q implementation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rx_in * start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rx_in * ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) rx_in * limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) } in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rx_out * start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rx_out * ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) rx_out * limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int buffers_wanted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) } amb_rxq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned long tx_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned long ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned long error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned long badcrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned long toolong;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned long aborted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned long unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) } amb_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) // a single struct pointed to by atm_vcc->dev_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 tx_vc_bits:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 tx_present:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } amb_tx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned char pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } amb_rx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) amb_rx_info rx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u16 tx_frame_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int tx_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int rx_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } amb_vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct amb_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 * membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) amb_cq cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) amb_txq txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) amb_rxq rxq[NUM_RX_POOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct mutex vcc_sf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) amb_tx_info txer[NUM_VCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct atm_vcc * rxer[NUM_VCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned int tx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int rx_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) amb_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct atm_dev * atm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct pci_dev * pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct timer_list housekeeping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) typedef struct amb_dev amb_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* rate rounding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) round_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) round_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) round_nearest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) } rounding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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