^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sata_via.c - VIA Serial ATA controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2003-2004 Jeff Garzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Hardware documentation available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRV_NAME "sata_via"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_VERSION "2.6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * vt8251 is different from other sata controllers of VIA. It has two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * channels, each channel has both Master and Slave slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum board_ids_enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) vt6420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) vt6421,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) vt8251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SATA_INT_GATE = 0x41, /* SATA interrupt gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SATA_NATIVE_MODE = 0x42, /* Native mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SVIA_MISC_3 = 0x46, /* Miscellaneous Control III */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PATA_PIO_TIMING = 0xAB, /* PATA timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PORT0 = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PORT1 = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ALL_PORTS = PORT0 | PORT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SATA_HOTPLUG = (1 << 5), /* enable IRQ on hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct svia_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool wd_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int vt6420_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) module_param_named(vt6420_hotplug, vt6420_hotplug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MODULE_PARM_DESC(vt6420_hotplug, "Enable hot-plug support for VT6420 (0=Don't support, 1=support)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int svia_pci_device_resume(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void svia_noop_freeze(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void vt6420_bmdma_start(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int vt6421_pata_cable_detect(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void vt6421_error_handler(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct pci_device_id svia_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { PCI_VDEVICE(VIA, 0x5337), vt6420 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { PCI_VDEVICE(VIA, 0x5372), vt6420 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { PCI_VDEVICE(VIA, 0x7372), vt6420 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { PCI_VDEVICE(VIA, 0x9000), vt8251 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct pci_driver svia_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .id_table = svia_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .probe = svia_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .resume = svia_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct scsi_host_template svia_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct ata_port_operations svia_base_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .sff_tf_load = svia_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct ata_port_operations vt6420_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .inherits = &svia_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .freeze = svia_noop_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .prereset = vt6420_prereset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .bmdma_start = vt6420_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct ata_port_operations vt6421_pata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .inherits = &svia_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .cable_detect = vt6421_pata_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .set_piomode = vt6421_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .set_dmamode = vt6421_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct ata_port_operations vt6421_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .inherits = &svia_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .scr_read = svia_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .scr_write = svia_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .error_handler = vt6421_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct ata_port_operations vt8251_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .inherits = &svia_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .hardreset = sata_std_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .scr_read = vt8251_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .scr_write = vt8251_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct ata_port_info vt6420_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .flags = ATA_FLAG_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .port_ops = &vt6420_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct ata_port_info vt6421_sport_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .flags = ATA_FLAG_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .port_ops = &vt6421_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct ata_port_info vt6421_pport_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* No MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .port_ops = &vt6421_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct ata_port_info vt8251_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .port_ops = &vt8251_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MODULE_AUTHOR("Jeff Garzik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (sc_reg > SCR_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (sc_reg > SCR_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const u8 ipm_tbl[] = { 1, 2, 6, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int slot = 2 * link->ap->port_no + link->pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) switch (scr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case SCR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_read_config_byte(pdev, 0xA0 + slot, &raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* read the DET field, bit0 and 1 of the config byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) v |= raw & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* read the SPD field, bit4 of the configure byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (raw & (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) v |= 0x02 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) v |= 0x01 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* read the IPM field, bit2 and 3 of the config byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) v |= ipm_tbl[(raw >> 2) & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case SCR_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* devices other than 5287 uses 0xA8 as base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) WARN_ON(pdev->device != 0x5287);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pci_read_config_dword(pdev, 0xB0 + slot * 4, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case SCR_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pci_read_config_byte(pdev, 0xA4 + slot, &raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* read the DET field, bit0 and bit1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) v |= ((raw & 0x02) << 1) | (raw & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* read the IPM field, bit2 and bit3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) v |= ((raw >> 2) & 0x03) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *val = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int slot = 2 * link->ap->port_no + link->pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (scr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case SCR_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* devices other than 5287 uses 0xA8 as base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) WARN_ON(pdev->device != 0x5287);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pci_write_config_dword(pdev, 0xB0 + slot * 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case SCR_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* set the DET field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) v |= ((val & 0x4) >> 1) | (val & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* set the IPM field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) v |= ((val >> 8) & 0x3) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pci_write_config_byte(pdev, 0xA4 + slot, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * svia_tf_load - send taskfile registers to host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @ap: Port to which output is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @tf: ATA taskfile register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Outputs ATA taskfile to standard ATA host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * This is to fix the internal bug of via chipsets, which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * reset the device register after changing the IEN bit on ctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct ata_taskfile ttf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (tf->ctl != ap->last_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ttf = *tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ttf.flags |= ATA_TFLAG_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tf = &ttf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ata_sff_tf_load(ap, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void svia_noop_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Some VIA controllers choke if ATA_NIEN is manipulated in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * certain way. Leave it alone and just clear pending IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ap->ops->sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ata_bmdma_irq_clear(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * vt6420_prereset - prereset for vt6420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @link: target ATA link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * SCR registers on vt6420 are pieces of shit and may hang the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * whole machine completely if accessed with the wrong timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * To avoid such catastrophe, vt6420 doesn't provide generic SCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * access operations, but uses SStatus and SControl only during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * boot probing in controlled way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * As the old (pre EH update) probing code is proven to work, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * strictly follow the access pattern.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Kernel thread context (may sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * 0 on success, -errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct ata_eh_context *ehc = &ap->link.eh_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long timeout = jiffies + (HZ * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 sstatus, scontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* don't do any SCR stuff if we're not loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!(ap->pflags & ATA_PFLAG_LOADING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto skip_scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Resume phy. This is the old SATA resume sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) svia_scr_write(link, SCR_CONTROL, 0x300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* wait for phy to become ready, if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ata_msleep(link->ap, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) svia_scr_read(link, SCR_STATUS, &sstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if ((sstatus & 0xf) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* open code sata_print_link_status() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) svia_scr_read(link, SCR_STATUS, &sstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) svia_scr_read(link, SCR_CONTROL, &scontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) online = (sstatus & 0xf) == 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ata_port_info(ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) online ? "up" : "down", sstatus, scontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* SStatus is read one more time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) svia_scr_read(link, SCR_STATUS, &sstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!online) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* tell EH to bail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ehc->i.action &= ~ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) skip_scr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* wait for !BSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ata_sff_wait_ready(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void vt6420_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if ((qc->tf.command == ATA_CMD_PACKET) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Prevents corruption on some ATAPI burners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ata_sff_pause(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ata_bmdma_start(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int vt6421_pata_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (tmp & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pio_bits[adev->pio_mode - XFER_PIO_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) udma_bits[adev->dma_mode - XFER_UDMA_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const unsigned int svia_bar_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 8, 4, 8, 4, 16, 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const unsigned int vt6421_bar_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 16, 16, 16, 16, 32, 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return addr + (port * 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return addr + (port * 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void vt6421_init_addrs(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) void __iomem * const * iomap = ap->host->iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void __iomem *reg_addr = iomap[ap->port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ioaddr->cmd_addr = reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ioaddr->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ioaddr->ctl_addr = (void __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ioaddr->bmdma_addr = bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ata_sff_std_ports(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ata_port_pbar_desc(ap, ap->port_no, -1, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (vt6420_hotplug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ppi[0]->port_ops->scr_read = svia_scr_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ppi[0]->port_ops->scr_write = svia_scr_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *r_host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) const struct ata_port_info *ppi[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(&pdev->dev, "failed to allocate host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) host->iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (i = 0; i < host->n_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) vt6421_init_addrs(host->ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *r_host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* 8251 hosts four sata ports as M/S of the two channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (i = 0; i < host->n_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ata_slave_link_init(host->ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void svia_wd_fix(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u8 tmp8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pci_read_config_byte(pdev, 0x52, &tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static irqreturn_t vt642x_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) irqreturn_t rc = ata_bmdma_interrupt(irq, dev_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* if the IRQ was not handled, it might be a hotplug IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (rc != IRQ_HANDLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 serror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* check for hotplug on port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) svia_scr_read(&host->ports[0]->link, SCR_ERROR, &serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (serror & SERR_PHYRDY_CHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ata_ehi_hotplugged(&host->ports[0]->link.eh_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ata_port_freeze(host->ports[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rc = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* check for hotplug on port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) svia_scr_read(&host->ports[1]->link, SCR_ERROR, &serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (serror & SERR_PHYRDY_CHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ata_ehi_hotplugged(&host->ports[1]->link.eh_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ata_port_freeze(host->ports[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) rc = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void vt6421_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct svia_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 serror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* see svia_configure() for description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!hpriv->wd_workaround) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) svia_scr_read(&ap->link, SCR_ERROR, &serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (serror == 0x1000500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ata_port_warn(ap, "Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) svia_wd_fix(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hpriv->wd_workaround = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ap->link.eh_context.i.flags |= ATA_EHI_QUIET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ata_sff_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void svia_configure(struct pci_dev *pdev, int board_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct svia_priv *hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 tmp8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_info(&pdev->dev, "routed to hard irq line %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* make sure SATA channels are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) (int)tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) tmp8 |= ALL_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* make sure interrupts for each channel sent to us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) (int) tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) tmp8 |= ALL_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* make sure native mode is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "enabling SATA channel native mode (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) (int) tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tmp8 |= NATIVE_MODE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* enable IRQ on hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pci_read_config_byte(pdev, SVIA_MISC_3, &tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if ((tmp8 & SATA_HOTPLUG) != SATA_HOTPLUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "enabling SATA hotplug (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) (int) tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) tmp8 |= SATA_HOTPLUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pci_write_config_byte(pdev, SVIA_MISC_3, tmp8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * vt6420/1 has problems talking to some drives. The following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * is the fix from Joseph Chan <JosephChan@via.com.tw>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * When host issues HOLD, device may send up to 20DW of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * before acknowledging it with HOLDA and the host should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * able to buffer them in FIFO. Unfortunately, some WD drives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * send up to 40DW before acknowledging HOLD and, in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * default configuration, this ends up overflowing vt6421's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * FIFO, making the controller abort the transaction with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * R_ERR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Rx52[2] is the internal 128DW FIFO Flow control watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * adjusting mechanism enable bit and the default value 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * means host will issue HOLD to device when the left FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * size goes below 32DW. Setting it to 1 makes the watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * 64DW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * https://bugzilla.kernel.org/show_bug.cgi?id=15173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * http://article.gmane.org/gmane.linux.ide/46352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * http://thread.gmane.org/gmane.linux.kernel/1062139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * As the fix slows down data transfer, apply it only if the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * actually appears - see vt6421_error_handler()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Apply the fix always on vt6420 as we don't know if SCR_ERROR can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * read safely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (board_id == vt6420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) svia_wd_fix(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) hpriv->wd_workaround = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct ata_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int board_id = (int) ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) const unsigned *bar_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct svia_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (board_id == vt6421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) bar_sizes = &vt6421_bar_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) bar_sizes = &svia_bar_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if ((pci_resource_start(pdev, i) == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) (pci_resource_len(pdev, i) < bar_sizes[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) (unsigned long long)pci_resource_start(pdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) (unsigned long long)pci_resource_len(pdev, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) switch (board_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case vt6420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) rc = vt6420_prepare_host(pdev, &host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case vt6421:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rc = vt6421_prepare_host(pdev, &host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case vt8251:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rc = vt8251_prepare_host(pdev, &host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) svia_configure(pdev, board_id, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return ata_host_activate(host, pdev->irq, vt642x_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) IRQF_SHARED, &svia_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) IRQF_SHARED, &svia_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int svia_pci_device_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct svia_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (hpriv->wd_workaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) svia_wd_fix(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) module_pci_driver(svia_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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