^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sata_uli.c - ULi Electronics SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Hardware documentation available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "sata_uli"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRV_VERSION "1.3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) uli_5289 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) uli_5287 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) uli_5281 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) uli_max_ports = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* PCI configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ULI5287_BASE = 0x90, /* sata0 phy SCR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ULI5287_OFFS = 0x10, /* offset from sata0->sata1 phy regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ULI5281_BASE = 0x60, /* sata0 phy SCR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ULI5281_OFFS = 0x60, /* offset from sata0->sata1 phy regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct uli_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int scr_cfg_addr[uli_max_ports];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct pci_device_id uli_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { PCI_VDEVICE(AL, 0x5289), uli_5289 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { PCI_VDEVICE(AL, 0x5287), uli_5287 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { PCI_VDEVICE(AL, 0x5281), uli_5281 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct pci_driver uli_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .id_table = uli_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .probe = uli_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct scsi_host_template uli_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct ata_port_operations uli_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .scr_read = uli_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .scr_write = uli_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .hardreset = ATA_OP_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct ata_port_info uli_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .flags = ATA_FLAG_SATA | ATA_FLAG_IGN_SIMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .port_ops = &uli_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_AUTHOR("Peer Chen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_DESCRIPTION("low-level driver for ULi Electronics SATA controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_DEVICE_TABLE(pci, uli_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct uli_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static u32 uli_scr_cfg_read(struct ata_link *link, unsigned int sc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pci_read_config_dword(pdev, cfg_addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void uli_scr_cfg_write(struct ata_link *link, unsigned int scr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int cfg_addr = get_scr_cfg_addr(link->ap, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pci_write_config_dword(pdev, cfg_addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int uli_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (sc_reg > SCR_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *val = uli_scr_cfg_read(link, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int uli_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uli_scr_cfg_write(link, sc_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int uli_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct ata_port_info *ppi[] = { &uli_port_info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int board_idx = (unsigned int) ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct uli_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem * const *iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct ata_ioports *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int n_ports, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) n_ports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (board_idx == uli_5287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) n_ports = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* allocate the host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* the first two ports are standard SFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rc = ata_pci_sff_init_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ata_pci_bmdma_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) iomap = host->iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (board_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case uli_5287:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* If there are four, the last two live right after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * the standard SFF ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) hpriv->scr_cfg_addr[0] = ULI5287_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ioaddr = &host->ports[2]->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ioaddr->cmd_addr = iomap[0] + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ioaddr->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ioaddr->ctl_addr = (void __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ioaddr->bmdma_addr = iomap[4] + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ata_sff_std_ports(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ata_port_desc(host->ports[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "cmd 0x%llx ctl 0x%llx bmdma 0x%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (unsigned long long)pci_resource_start(pdev, 0) + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ((unsigned long long)pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS) + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (unsigned long long)pci_resource_start(pdev, 4) + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ioaddr = &host->ports[3]->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ioaddr->cmd_addr = iomap[2] + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ioaddr->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ioaddr->ctl_addr = (void __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ioaddr->bmdma_addr = iomap[4] + 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ata_sff_std_ports(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ata_port_desc(host->ports[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "cmd 0x%llx ctl 0x%llx bmdma 0x%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (unsigned long long)pci_resource_start(pdev, 2) + 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ((unsigned long long)pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS) + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (unsigned long long)pci_resource_start(pdev, 4) + 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case uli_5289:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hpriv->scr_cfg_addr[0] = ULI5287_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case uli_5281:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) hpriv->scr_cfg_addr[0] = ULI5281_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) hpriv->scr_cfg_addr[1] = ULI5281_BASE + ULI5281_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pci_intx(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IRQF_SHARED, &uli_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) module_pci_driver(uli_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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