^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sata_sx4.c - Promise SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2003-2004 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Hardware documentation available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Theory of operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) engine, DIMM memory, and four ATA engines (one per SATA port).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Data is copied to/from DIMM memory by the HDMA engine, before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) handing off to one (or more) of the ATA engines. The ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) engines operate solely on DIMM memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) The SX4 behaves like a PATA chip, with no SATA controls or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) knowledge whatsoever, leading to the presumption that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PATA<->SATA bridges exist on SX4 boards, external to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PDC20621 chip itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) The chip is quite capable, supporting an XOR engine and linked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) hardware commands (permits a string to transactions to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) submitted and waited-on as a single unit), and an optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) microprocessor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The limiting factor is largely software. This Linux driver was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) written to multiplex the single HDMA engine to copy disk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) transactions into a fixed DIMM memory space, from where an ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) engine takes over. As a result, each WRITE looks like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) submit HDMA packet to hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) hardware copies data from system memory to DIMM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) hardware raises interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) submit ATA packet to hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) hardware executes ATA WRITE command, w/ data in DIMM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) hardware raises interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) and each READ looks like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) submit ATA packet to hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) hardware executes ATA READ command, w/ data in DIMM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) hardware raises interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) submit HDMA packet to hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) hardware copies data from DIMM to system memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) hardware raises interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) This is a very slow, lock-step way of doing things that can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) certainly be improved by motivated kernel hackers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include "sata_promise.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DRV_NAME "sata_sx4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DRV_VERSION "0.12"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PDC_MMIO_BAR = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PDC_DIMM_BAR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PDC_CTLSTAT = 0x60, /* IDEn control / status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PDC_20621_SEQCTL = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PDC_20621_SEQMASK = 0x480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PDC_20621_GENERAL_CTL = 0x484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PDC_20621_PAGE_SIZE = (32 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* chosen, not constant, values; we design our own DIMM mem map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PDC_20621_DIMM_BASE = 0x00200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PDC_20621_DIMM_DATA = (64 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PDC_DIMM_DATA_STEP = (256 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PDC_DIMM_WINDOW_STEP = (8 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PDC_DIMM_HOST_PRD = (6 * 1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PDC_DIMM_HOST_PKT = (128 * 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PDC_DIMM_HPKT_PRD = (128 * 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PDC_DIMM_ATA_PKT = (128 * 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PDC_DIMM_APKT_PRD = (128 * 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PDC_PAGE_WINDOW = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PDC_PAGE_DATA = PDC_PAGE_WINDOW +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (1<<23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) board_20621 = 0, /* FastTrak S150 SX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PDC_RESET = (1 << 11), /* HDMA/ATA reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PDC_MAX_HDMA = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PDC_I2C_CONTROL = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PDC_I2C_ADDR_DATA = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PDC_DIMM0_CONTROL = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PDC_DIMM1_CONTROL = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PDC_SDRAM_CONTROL = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PDC_I2C_WRITE = 0, /* master -> slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PDC_I2C_READ = (1 << 6), /* master <- slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PDC_I2C_START = (1 << 7), /* start I2C proto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PDC_DIMM_SPD_ROW_NUM = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PDC_DIMM_SPD_COLUMN_NUM = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PDC_DIMM_SPD_MODULE_ROW = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PDC_DIMM_SPD_TYPE = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PDC_DIMM_SPD_FRESH_RATE = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PDC_DIMM_SPD_BANK_NUM = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PDC_DIMM_SPD_CAS_LATENCY = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PDC_DIMM_SPD_ATTRIBUTE = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PDC_DIMM_SPD_SYSTEM_FREQ = 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PDC_CTL_STATUS = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PDC_DIMM_WINDOW_CTLR = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PDC_TIME_CONTROL = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PDC_TIME_PERIOD = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PDC_TIME_COUNTER = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PDC_GENERAL_CTLR = 0x484,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PCI_PLL_INIT = 0x8A531824,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PCI_X_TCOUNT = 0xEE1E5CFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* PDC_TIME_CONTROL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PDC_TIMER_BUZZER = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PDC_TIMER_ENABLE = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PDC_TIMER_MASK_INT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PDC_TIMER_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PDC_TIMER_MASK_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ECC_ERASE_BUF_SZ (128 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct pdc_port_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dma_addr_t pkt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct pdc_host_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int doing_hdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int hdma_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int hdma_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long pkt_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } hdma[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void pdc_error_handler(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void pdc_freeze(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void pdc_thaw(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int pdc_port_start(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static enum ata_completion_errors pdc20621_qc_prep(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static unsigned int pdc20621_dimm_init(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int pdc20621_detect_dimm(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static unsigned int pdc20621_i2c_read(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 device, u32 subaddr, u32 *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int pdc20621_prog_dimm0(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #ifdef ATA_VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void pdc20621_get_from_dimm(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void *psource, u32 offset, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void pdc20621_put_to_dimm(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void *psource, u32 offset, u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void pdc20621_irq_clear(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int pdc_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct scsi_host_template pdc_sata_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ATA_BASE_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .sg_tablesize = LIBATA_MAX_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .dma_boundary = ATA_DMA_BOUNDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* TODO: inherit from base port_ops after converting to new EH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct ata_port_operations pdc_20621_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .check_atapi_dma = pdc_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .qc_prep = pdc20621_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .qc_issue = pdc20621_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .freeze = pdc_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .thaw = pdc_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .softreset = pdc_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .error_handler = pdc_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .lost_interrupt = ATA_OP_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .post_internal_cmd = pdc_post_internal_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .port_start = pdc_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .sff_tf_load = pdc_tf_load_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .sff_exec_command = pdc_exec_command_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .sff_irq_clear = pdc20621_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct ata_port_info pdc_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* board_20621 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .flags = ATA_FLAG_SATA | ATA_FLAG_NO_ATAPI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ATA_FLAG_PIO_POLLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .port_ops = &pdc_20621_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct pci_device_id pdc_sata_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct pci_driver pdc_sata_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .id_table = pdc_sata_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .probe = pdc_sata_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int pdc_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct pdc_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!pp->pkt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ap->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static inline void pdc20621_ata_sg(u8 *buf, unsigned int portno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int total_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __le32 *buf32 = (__le32 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* output ATA packet S/G table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (PDC_DIMM_DATA_STEP * portno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) buf32[dw] = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PDC_20621_DIMM_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (PDC_DIMM_WINDOW_STEP * portno) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PDC_DIMM_APKT_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) buf32[dw], buf32[dw + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline void pdc20621_host_sg(u8 *buf, unsigned int portno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int total_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __le32 *buf32 = (__le32 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* output Host DMA packet S/G table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) (PDC_DIMM_DATA_STEP * portno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) buf32[dw] = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PDC_20621_DIMM_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (PDC_DIMM_WINDOW_STEP * portno) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PDC_DIMM_HPKT_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) buf32[dw], buf32[dw + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int devno, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int portno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int i, dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __le32 *buf32 = (__le32 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 dev_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int dimm_sg = PDC_20621_DIMM_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (PDC_DIMM_WINDOW_STEP * portno) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PDC_DIMM_APKT_PRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) i = PDC_DIMM_ATA_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Set up ATA packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) buf[i++] = PDC_PKT_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else if (tf->protocol == ATA_PROT_NODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) buf[i++] = PDC_PKT_NODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) buf[i++] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) buf[i++] = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) buf[i++] = portno + 1; /* seq. id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) buf[i++] = 0xff; /* delay seq. id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* dimm dma S/G, and next-pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dw = i >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (tf->protocol == ATA_PROT_NODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) buf32[dw] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) buf32[dw] = cpu_to_le32(dimm_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) buf32[dw + 1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) i += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (devno == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_reg = ATA_DEVICE_OBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* select device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) buf[i++] = dev_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* device control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) buf[i++] = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int portno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) __le32 *buf32 = (__le32 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int host_sg = PDC_20621_DIMM_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (PDC_DIMM_WINDOW_STEP * portno) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PDC_DIMM_HOST_PRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int dimm_sg = PDC_20621_DIMM_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (PDC_DIMM_WINDOW_STEP * portno) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PDC_DIMM_HPKT_PRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dw = PDC_DIMM_HOST_PKT >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Set up Host DMA packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tmp = PDC_PKT_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tmp |= ((portno + 1 + 4) << 16); /* seq. id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tmp |= (0xff << 24); /* delay seq. id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) buf32[dw + 0] = cpu_to_le32(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) buf32[dw + 1] = cpu_to_le32(host_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) buf32[dw + 2] = cpu_to_le32(dimm_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) buf32[dw + 3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PDC_DIMM_HOST_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) buf32[dw + 0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) buf32[dw + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) buf32[dw + 2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) buf32[dw + 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct pdc_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int portno = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int i, si, idx, total_len = 0, sgt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __le32 *buf = (__le32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) VPRINTK("ata%u: ENTER\n", ap->print_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Build S/G table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) buf[idx++] = cpu_to_le32(sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) buf[idx++] = cpu_to_le32(sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) total_len += sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sgt_len = idx * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Build ATA, host DMA packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pdc20621_host_sg(&pp->dimm_buf[0], portno, total_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pdc20621_ata_sg(&pp->dimm_buf[0], portno, total_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (qc->tf.flags & ATA_TFLAG_LBA48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* copy three S/G tables and two packets to DIMM MMIO window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PDC_DIMM_HOST_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* force host FIFO dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) readl(dimm_mmio); /* MMIO PCI posting flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct pdc_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int portno = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) VPRINTK("ata%u: ENTER\n", ap->print_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (qc->tf.flags & ATA_TFLAG_LBA48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* copy three S/G tables and two packets to DIMM MMIO window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* force host FIFO dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) readl(dimm_mmio); /* MMIO PCI posting flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static enum ata_completion_errors pdc20621_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) switch (qc->tf.protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case ATA_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pdc20621_dma_prep(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case ATA_PROT_NODATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pdc20621_nodata_prep(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned int seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 pkt_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct ata_host *host = ap->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 pkt_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct pdc_host_priv *pp = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!pp->doing_hdma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __pdc20621_push_hdma(qc, seq, pkt_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pp->doing_hdma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pp->hdma[idx].qc = qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pp->hdma[idx].seq = seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pp->hdma[idx].pkt_ofs = pkt_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pp->hdma_prod++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct pdc_host_priv *pp = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* if nothing on queue, we're done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (pp->hdma_prod == pp->hdma_cons) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pp->doing_hdma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pp->hdma[idx].pkt_ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pp->hdma_cons++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #ifdef ATA_VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int port_no = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dimm_mmio += PDC_DIMM_HOST_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #endif /* ATA_VERBOSE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void pdc20621_packet_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct ata_host *host = ap->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned int port_no = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u8 seq = (u8) (port_no + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned int port_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) VPRINTK("ata%u: ENTER\n", ap->print_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) wmb(); /* flush PRD, pkt writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (rw && qc->tf.protocol == ATA_PROT_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) seq += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pdc20621_dump_hdma(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) VPRINTK("queued ofs 0x%x (%u), seq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) port_ofs + PDC_DIMM_HOST_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) port_ofs + PDC_DIMM_HOST_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) writel(port_ofs + PDC_DIMM_ATA_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) port_ofs + PDC_DIMM_ATA_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) port_ofs + PDC_DIMM_ATA_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) switch (qc->tf.protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case ATA_PROT_NODATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (qc->tf.flags & ATA_TFLAG_POLLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case ATA_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pdc20621_packet_start(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case ATAPI_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned int doing_hdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) void __iomem *mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned int port_no = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned int port_ofs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* step two - DMA from DIMM to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (doing_hdma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* get drive status; clear intr; complete txn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ata_qc_complete(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pdc20621_pop_hdma(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* step one - exec ATA command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 seq = (u8) (port_no + 1 + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* submit hdma pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pdc20621_dump_hdma(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pdc20621_push_hdma(qc, seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) port_ofs + PDC_DIMM_HOST_PKT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* step one - DMA from host to DIMM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (doing_hdma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 seq = (u8) (port_no + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* submit ata pkt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) readl(mmio + PDC_20621_SEQCTL + (seq * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) writel(port_ofs + PDC_DIMM_ATA_PKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* step two - execute ATA command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* get drive status; clear intr; complete txn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ata_qc_complete(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pdc20621_pop_hdma(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* command completion, but no data xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) } else if (qc->tf.protocol == ATA_PROT_NODATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) qc->err_mask |= ac_err_mask(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ata_qc_complete(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ap->stats.idle_irq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void pdc20621_irq_clear(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ioread8(ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned int i, tmp, port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) unsigned int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!host || !host->iomap[PDC_MMIO_BAR]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) VPRINTK("QUICK EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mmio_base = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* reading should also clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mmio_base += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mask = readl(mmio_base + PDC_20621_SEQMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) VPRINTK("mask == 0x%x\n", mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (mask == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) VPRINTK("QUICK EXIT 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mask &= 0xffff; /* only 16 tags possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) VPRINTK("QUICK EXIT 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) for (i = 1; i < 9; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) port_no = i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (port_no > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) port_no -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (port_no >= host->n_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ap = host->ports[port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) tmp = mask & (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (tmp && ap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) qc = ata_qc_from_tag(ap, ap->link.active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) handled += pdc20621_host_intr(ap, qc, (i > 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) VPRINTK("mask == 0x%x\n", mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) VPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static void pdc_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) void __iomem *mmio = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) tmp = readl(mmio + PDC_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) tmp |= PDC_MASK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) tmp &= ~PDC_DMA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) writel(tmp, mmio + PDC_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) readl(mmio + PDC_CTLSTAT); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static void pdc_thaw(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) void __iomem *mmio = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* FIXME: start HDMA engine, if zero ATA engines running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ioread8(ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* turn IRQ back on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) tmp = readl(mmio + PDC_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) tmp &= ~PDC_MASK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) writel(tmp, mmio + PDC_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) readl(mmio + PDC_CTLSTAT); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static void pdc_reset_port(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* FIXME: handle HDMA copy engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) for (i = 11; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) tmp = readl(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (tmp & PDC_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) tmp |= PDC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) writel(tmp, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) tmp &= ~PDC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) writel(tmp, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) readl(mmio); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int pdc_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pdc_reset_port(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ata_sff_softreset(link, class, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static void pdc_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (!(ap->pflags & ATA_PFLAG_FROZEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pdc_reset_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ata_sff_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* make DMA engine forget about the failed command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (qc->flags & ATA_QCFLAG_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) pdc_reset_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u8 *scsicmd = qc->scsicmd->cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int pio = 1; /* atapi dma off by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Whitelist commands that may use DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) switch (scsicmd[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case WRITE_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case WRITE_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case WRITE_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) case READ_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) case READ_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case READ_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case 0xad: /* READ_DVD_STRUCTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case 0xbe: /* READ_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (scsicmd[0] == WRITE_10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) unsigned int lba =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) (scsicmd[2] << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) (scsicmd[3] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) (scsicmd[4] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) scsicmd[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (lba >= 0xFFFF4FA2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) pio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) WARN_ON(tf->protocol == ATA_PROT_DMA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) tf->protocol == ATAPI_PROT_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ata_sff_tf_load(ap, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) WARN_ON(tf->protocol == ATA_PROT_DMA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) tf->protocol == ATAPI_PROT_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ata_sff_exec_command(ap, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) port->cmd_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) port->data_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) port->feature_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) port->error_addr = base + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) port->nsect_addr = base + 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) port->lbal_addr = base + 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) port->lbam_addr = base + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) port->lbah_addr = base + 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) port->device_addr = base + 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) port->command_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) port->status_addr = base + 0x1c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) port->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) port->ctl_addr = base + 0x38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #ifdef ATA_VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u32 offset, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u32 window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u16 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u8 page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) long dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) page_mask = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) window_size = 0x2000 * 4; /* 32K byte uchar size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) idx = (u16) (offset / window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) writel(0x01, mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) readl(mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) readl(mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) offset -= (idx * window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dist = ((long) (window_size - (offset + size))) >= 0 ? size :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) (long) (window_size - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) memcpy_fromio(psource, dimm_mmio + offset / 4, dist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) psource += dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) size -= dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) for (; (long) size >= (long) window_size ;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) writel(0x01, mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) readl(mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) readl(mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) memcpy_fromio(psource, dimm_mmio, window_size / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) psource += window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) size -= window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) writel(0x01, mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) readl(mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) readl(mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) memcpy_fromio(psource, dimm_mmio, size / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) u32 offset, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) u32 window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u16 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) u8 page_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) long dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) page_mask = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) window_size = 0x2000 * 4; /* 32K byte uchar size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) idx = (u16) (offset / window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) readl(mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) offset -= (idx * window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) (long) (window_size - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) memcpy_toio(dimm_mmio + offset / 4, psource, dist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) writel(0x01, mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) readl(mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) psource += dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) size -= dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) for (; (long) size >= (long) window_size ;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) readl(mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) memcpy_toio(dimm_mmio, psource, window_size / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) writel(0x01, mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) readl(mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) psource += window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) size -= window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) readl(mmio + PDC_DIMM_WINDOW_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) memcpy_toio(dimm_mmio, psource, size / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) writel(0x01, mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) readl(mmio + PDC_GENERAL_CTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u32 subaddr, u32 *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 i2creg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) i2creg |= device << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) i2creg |= subaddr << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Set the device and subaddress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) readl(mmio + PDC_I2C_ADDR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Write Control to perform read operation, mask int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) mmio + PDC_I2C_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) for (count = 0; count <= 1000; count ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) status = readl(mmio + PDC_I2C_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (status & PDC_I2C_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) status = readl(mmio + PDC_I2C_ADDR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } else if (count == 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) *pdata = (status >> 8) & 0x000000ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static int pdc20621_detect_dimm(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (data == 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (data <= 0x75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return 133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int pdc20621_prog_dimm0(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) u32 spd0[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int size, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u8 bdimmsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) unsigned int ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) } pdc_i2c_read_data [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) { PDC_DIMM_SPD_TYPE, 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) { PDC_DIMM_SPD_FRESH_RATE, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) { PDC_DIMM_SPD_COLUMN_NUM, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) { PDC_DIMM_SPD_ATTRIBUTE, 21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) { PDC_DIMM_SPD_ROW_NUM, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) { PDC_DIMM_SPD_BANK_NUM, 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) { PDC_DIMM_SPD_MODULE_ROW, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) { PDC_DIMM_SPD_CAS_LATENCY, 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) pdc_i2c_read_data[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) &spd0[pdc_i2c_read_data[i].ofs]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ((((spd0[27] + 9) / 10) - 1) << 8) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) data |= (((((spd0[29] > spd0[28])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (spd0[18] & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) data |= ((0x03) << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) else if (spd0[18] & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) data |= ((0x02) << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) else if (spd0[18] & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) data |= ((0x01) << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) data |= (0 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) Calculate the size of bDIMMSize (power of 2) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) merge the DIMM size by program start/end address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) data |= (((size / 16) - 1) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) data |= (0 << 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) data |= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) writel(data, mmio + PDC_DIMM0_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) readl(mmio + PDC_DIMM0_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) u32 data, spd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int error, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) Set To Default : DIMM Module Global Control Register (0x022259F1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) DIMM Arbitration Disable (bit 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) DIMM Data/Control Output Driving Selection (bit12 - bit15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) Refresh Enable (bit 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) data = 0x022259F1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) writel(data, mmio + PDC_SDRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) readl(mmio + PDC_SDRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Turn on for ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PDC_DIMM_SPD_TYPE, &spd0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) pr_err("Failed in i2c read: device=%#x, subaddr=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (spd0 == 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) data |= (0x01 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) writel(data, mmio + PDC_SDRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) readl(mmio + PDC_SDRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) printk(KERN_ERR "Local DIMM ECC Enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* DIMM Initialization Select/Enable (bit 18/19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) data &= (~(1<<18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) data |= (1<<19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) writel(data, mmio + PDC_SDRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) for (i = 1; i <= 10; i++) { /* polling ~5 secs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) data = readl(mmio + PDC_SDRAM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (!(data & (1<<19))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) msleep(i*100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static unsigned int pdc20621_dimm_init(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) int speed, size, length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) u32 addr, spd0, pci_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) u32 time_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) u32 tcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u32 ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u32 clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) u32 fparam = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Initialize PLL based upon PCI Bus Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* Initialize Time Period Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) writel(0xffffffff, mmio + PDC_TIME_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) time_period = readl(mmio + PDC_TIME_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Enable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) readl(mmio + PDC_TIME_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* Wait 3 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) msleep(3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) When timer is enabled, counter is decreased every internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) tcount = readl(mmio + PDC_TIME_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) If SX4 is on PCI-X bus, after 3 seconds, the timer counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) register should be >= (0xffffffff - 3x10^8).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (tcount >= PCI_X_TCOUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ticks = (time_period - tcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) clock = (ticks / 300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) clock = (clock * 33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* PLL F Param (bit 22:16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) fparam = (1400000 / clock) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) pci_status = (0x8a001824 | (fparam << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) pci_status = PCI_PLL_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* Initialize PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) VPRINTK("pci_status: 0x%x\n", pci_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) writel(pci_status, mmio + PDC_CTL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) readl(mmio + PDC_CTL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) Read SPD of DIMM by I2C interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) and program the DIMM Module Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (!(speed = pdc20621_detect_dimm(host))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) printk(KERN_ERR "Detect Local DIMM Fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return 1; /* DIMM error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) VPRINTK("Local DIMM Speed = %d\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Programming DIMM0 Module Control Register (index_CID0:80h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) size = pdc20621_prog_dimm0(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) VPRINTK("Local DIMM Size = %dMB\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* Programming DIMM Module Global Control Register (index_CID0:88h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (pdc20621_prog_dimm_global(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #ifdef ATA_VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) u8 test_parttern1[40] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {0x55,0xAA,'P','r','o','m','i','s','e',' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) 'N','o','t',' ','Y','e','t',' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) 'D','e','f','i','n','e','d',' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) '1','.','1','0',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) '9','8','0','3','1','6','1','2',0,0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) u8 test_parttern2[40] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) test_parttern2[1], &(test_parttern2[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) test_parttern2[1], &(test_parttern2[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) test_parttern2[1], &(test_parttern2[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* ECC initiliazation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PDC_DIMM_SPD_TYPE, &spd0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pr_err("Failed in i2c read: device=%#x, subaddr=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (spd0 == 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) VPRINTK("Start ECC initialization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) length = size * 1024 * 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) buf = kzalloc(ECC_ERASE_BUF_SZ, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) while (addr < length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) pdc20621_put_to_dimm(host, buf, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ECC_ERASE_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) addr += ECC_ERASE_BUF_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) VPRINTK("Finish ECC initialization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static void pdc_20621_init(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* hard-code chip #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) mmio += PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * Select page 0x40 for our 32k DIMM window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * Reset Host DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) tmp = readl(mmio + PDC_HDMA_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) tmp |= PDC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) writel(tmp, mmio + PDC_HDMA_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) tmp = readl(mmio + PDC_HDMA_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) tmp &= ~PDC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) writel(tmp, mmio + PDC_HDMA_CTLSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static int pdc_sata_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) const struct ata_port_info *ppi[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) { &pdc_port_info[ent->driver_data], NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct pdc_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (!host || !hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* acquire resources and fill host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (rc == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pcim_pin_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) host->iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) unsigned int offset = 0x200 + i * 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pdc_sata_setup_port(&ap->ioaddr, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ata_port_pbar_desc(ap, PDC_DIMM_BAR, -1, "dimm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ata_port_pbar_desc(ap, PDC_MMIO_BAR, offset, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* configure and activate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (pdc20621_dimm_init(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) pdc_20621_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) IRQF_SHARED, &pdc_sata_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) module_pci_driver(pdc_sata_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) MODULE_AUTHOR("Jeff Garzik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) MODULE_DESCRIPTION("Promise SATA low-level driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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