^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sata_svw.c - ServerWorks / Apple K2 SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jeff Garzik <jgarzik@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Bits from Jeff Garzik, Copyright RedHat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This driver probably works with non-Apple versions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Broadcom chipset...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Hardware documentation available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_NAME "sata_svw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRV_VERSION "2.3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ap->flags bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) K2_FLAG_SATA_8_PORTS = (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) K2_FLAG_NO_ATAPI_DMA = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) K2_FLAG_BAR_POS_3 = (1 << 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Taskfile registers offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) K2_SATA_TF_CMD_OFFSET = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) K2_SATA_TF_DATA_OFFSET = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) K2_SATA_TF_ERROR_OFFSET = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) K2_SATA_TF_NSECT_OFFSET = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) K2_SATA_TF_LBAL_OFFSET = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) K2_SATA_TF_LBAM_OFFSET = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) K2_SATA_TF_LBAH_OFFSET = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) K2_SATA_TF_DEVICE_OFFSET = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) K2_SATA_TF_CTL_OFFSET = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* DMA base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) K2_SATA_DMA_CMD_OFFSET = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* SCRs base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) K2_SATA_SCR_STATUS_OFFSET = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) K2_SATA_SCR_ERROR_OFFSET = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) K2_SATA_SCR_CONTROL_OFFSET = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) K2_SATA_SICR1_OFFSET = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) K2_SATA_SICR2_OFFSET = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) K2_SATA_SIM_OFFSET = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Port stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) K2_SATA_PORT_OFFSET = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) chip_svw4 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) chip_svw8 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) chip_svw42 = 2, /* bar 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) chip_svw43 = 3, /* bar 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static u8 k2_stat_check_status(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 cmnd = qc->scsicmd->cmnd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -1; /* ATAPI DMA not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (cmnd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case READ_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case READ_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case READ_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case WRITE_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case WRITE_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case WRITE_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int k2_sata_scr_read(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (sc_reg > SCR_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int k2_sata_scr_write(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (sc_reg > SCR_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int k2_sata_softreset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int *class, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dmactl = readb(mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Clear the start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (dmactl & ATA_DMA_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dmactl &= ~ATA_DMA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writeb(dmactl, mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ata_sff_softreset(link, class, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int k2_sata_hardreset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int *class, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dmactl = readb(mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Clear the start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (dmactl & ATA_DMA_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dmactl &= ~ATA_DMA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writeb(dmactl, mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return sata_sff_hardreset(link, class, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (tf->ctl != ap->last_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writeb(tf->ctl, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writew(tf->feature | (((u16)tf->hob_feature) << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ioaddr->feature_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } else if (is_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writew(tf->feature, ioaddr->feature_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writew(tf->nsect, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writew(tf->lbal, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writew(tf->lbam, ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writew(tf->lbah, ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (tf->flags & ATA_TFLAG_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writeb(tf->device, ioaddr->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u16 nsect, lbal, lbam, lbah, feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) tf->command = k2_stat_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tf->device = readw(ioaddr->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) feature = readw(ioaddr->error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) nsect = readw(ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) lbal = readw(ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) lbam = readw(ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) lbah = readw(ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tf->feature = feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tf->nsect = nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tf->lbal = lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tf->lbam = lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tf->lbah = lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (tf->flags & ATA_TFLAG_LBA48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tf->hob_feature = feature >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tf->hob_nsect = nsect >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tf->hob_lbal = lbal >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tf->hob_lbam = lbam >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tf->hob_lbah = lbah >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @qc: Info associated with this ATA transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * spin_lock_irqsave(host lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void __iomem *mmio = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* load PRD table addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mb(); /* make sure PRD table writes are visible to controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* specify data direction, triple-check start bit is clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dmactl = readb(mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dmactl |= ATA_DMA_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writeb(dmactl, mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* issue r/w command if this is not a ATA DMA command*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (qc->tf.protocol != ATA_PROT_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ap->ops->sff_exec_command(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @qc: Info associated with this ATA transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * spin_lock_irqsave(host lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void __iomem *mmio = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* start host DMA transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dmactl = readb(mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* This works around possible data corruption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) On certain SATA controllers that can be seen when the r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) command is given to the controller before the host DMA is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) On a Read command, the controller would initiate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) command to the drive even before it sees the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) start. When there are very fast drives connected to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) controller, or when the data request hits in the drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cache, there is the possibility that the drive returns a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) part or all of the requested data to the controller before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) the DMA start is issued. In this case, the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) would become confused as to what to do with the data. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) the worst case when all the data is returned back to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) controller, the controller could hang. In other cases it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) could return partial data returning in data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) corruption. This problem has been seen in PPC systems and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) can also appear on an system with very fast disks, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) the SATA controller is sitting behind a number of bridges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) and hence there is significant latency between the r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) command and the start command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* issue r/w command if the access is to ATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (qc->tf.protocol == ATA_PROT_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ap->ops->sff_exec_command(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static u8 k2_stat_check_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return readl(ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Find the ata_port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ap = ata_shost_to_port(shost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ap == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Find the OF node for the PCI device proper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (np == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Match it to a port node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) index = (ap == ap->host->ports[0]) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) for (np = np->child; np != NULL; np = np->sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) const u32 *reg = of_get_property(np, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (index == *reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) seq_printf(m, "devspec: %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct scsi_host_template k2_sata_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .show_info = k2_sata_show_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct ata_port_operations k2_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .softreset = k2_sata_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .hardreset = k2_sata_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .sff_tf_load = k2_sata_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .sff_tf_read = k2_sata_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .sff_check_status = k2_stat_check_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .check_atapi_dma = k2_sata_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .bmdma_setup = k2_bmdma_setup_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .bmdma_start = k2_bmdma_start_mmio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .scr_read = k2_sata_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .scr_write = k2_sata_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct ata_port_info k2_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* chip_svw4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .port_ops = &k2_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* chip_svw8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) K2_FLAG_SATA_8_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .port_ops = &k2_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* chip_svw42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .flags = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .port_ops = &k2_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* chip_svw43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .flags = ATA_FLAG_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .port_ops = &k2_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) port->feature_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) port->command_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) port->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const struct ata_port_info *ppi[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { &k2_port_info[ent->driver_data], NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int n_ports, i, rc, bar_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) n_ports = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) n_ports = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) bar_pos = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) bar_pos = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * If this driver happens to only be useful on Apple's K2, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * we should check that here as it has a normal Serverworks ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Check if we have resources mapped at all (second function may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * have been disabled by firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (pci_resource_len(pdev, bar_pos) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* In IDE mode we need to pin the device to ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pcim_release does not clear the busmaster bit in config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) space, clearing causes busmaster DMA to fail on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ports 3 & 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pcim_pin_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Request and iomap PCI regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (rc == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pcim_pin_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) host->iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mmio_base = host->iomap[bar_pos];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* different controllers have different number of ports - currently 4 or 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* All ports are on the same function. Multi-function device is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * longer available. This should not be seen in any system. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int offset = i * K2_SATA_PORT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ata_port_pbar_desc(ap, 5, -1, "mmio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ata_port_pbar_desc(ap, 5, offset, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Clear a magic bit in SCR1 according to Darwin, those help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * some funky seagate drives (though so far, those were already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * set by the firmware on the machines I had access to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) mmio_base + K2_SATA_SICR1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Clear SATA error & interrupts we don't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) IRQF_SHARED, &k2_sata_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* 0x240 is device ID for Apple K2 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * 0x241 is device ID for Serverworks Frodo4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * 0x242 is device ID for Serverworks Frodo8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct pci_device_id k2_sata_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct pci_driver k2_sata_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .id_table = k2_sata_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .probe = k2_sata_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) module_pci_driver(k2_sata_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_AUTHOR("Benjamin Herrenschmidt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags