Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  sata_sis.c - Silicon Integrated Systems SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Maintained by:  Uwe Koziolek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  		    Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *		    on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Copyright 2004 Uwe Koziolek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  Hardware documentation available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "sis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRV_NAME	"sata_sis"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRV_VERSION	"1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	sis_180			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	SIS_SCR_PCI_BAR		= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	/* PCI configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	SIS_GENCTL		= 0x54, /* IDE General Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	SIS180_SATA1_OFS	= 0x10, /* offset from sata0->sata1 phy regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	SIS182_SATA1_OFS	= 0x20, /* offset from sata0->sata1 phy regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	SIS_PMR			= 0x90, /* port mapping register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	SIS_PMR_COMBINED	= 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/* random bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const struct pci_device_id sis_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ PCI_VDEVICE(SI, 0x0180), sis_180 },	/* SiS 964/180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ PCI_VDEVICE(SI, 0x0181), sis_180 },	/* SiS 964/180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ PCI_VDEVICE(SI, 0x0182), sis_180 },	/* SiS 965/965L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ PCI_VDEVICE(SI, 0x0183), sis_180 },	/* SiS 965/965L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ PCI_VDEVICE(SI, 0x1182), sis_180 },	/* SiS 966/680 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ PCI_VDEVICE(SI, 0x1183), sis_180 },	/* SiS 966/966L/968/680 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ }	/* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct pci_driver sis_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.name			= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.id_table		= sis_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.probe			= sis_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.remove			= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.suspend		= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.resume			= ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static struct scsi_host_template sis_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct ata_port_operations sis_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.inherits		= &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.scr_read		= sis_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.scr_write		= sis_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static const struct ata_port_info sis_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.flags		= ATA_FLAG_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.udma_mask	= ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.port_ops	= &sis_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) MODULE_AUTHOR("Uwe Koziolek");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 pmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (ap->port_no)  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		case 0x0180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		case 0x0181:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			pci_read_config_byte(pdev, SIS_PMR, &pmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			if ((pmr & SIS_PMR_COMBINED) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				addr += SIS180_SATA1_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		case 0x0182:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		case 0x0183:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		case 0x1182:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			addr += SIS182_SATA1_OFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (link->pmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		addr += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static u32 sis_scr_cfg_read(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			    unsigned int sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	pci_read_config_dword(pdev, cfg_addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int sis_scr_cfg_write(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			     unsigned int sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	pci_write_config_dword(pdev, cfg_addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (sc_reg > SCR_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (ap->flags & SIS_FLAG_CFGSCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return sis_scr_cfg_read(link, sc_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	*val = ioread32(base + sc_reg * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (sc_reg > SCR_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ap->flags & SIS_FLAG_CFGSCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return sis_scr_cfg_write(link, sc_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	iowrite32(val, base + (sc_reg * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct ata_port_info pi = sis_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	const struct ata_port_info *ppi[] = { &pi, &pi };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u32 genctl, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u8 pmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u8 port2_start = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* check and see if the SCRs are in IO space or PCI cfg space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		pi.flags |= SIS_FLAG_CFGSCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* if hardware thinks SCRs are in IO space, but there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * no IO resources assigned, change to PCI cfg space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		genctl &= ~GENCTL_IOMAPPED_SCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		pi.flags |= SIS_FLAG_CFGSCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	pci_read_config_byte(pdev, SIS_PMR, &pmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	switch (ent->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	case 0x0180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case 0x0181:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		/* The PATA-handling is provided by pata_sis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		switch (pmr & 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			ppi[1] = &sis_info133_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		case 0x30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			ppi[0] = &sis_info133_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if ((pmr & SIS_PMR_COMBINED) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				 "Detected SiS 180/181/964 chipset in SATA mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			port2_start = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				 "Detected SiS 180/181 chipset in combined mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			port2_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			pi.flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	case 0x0182:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	case 0x0183:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		pci_read_config_dword(pdev, 0x6C, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		if (val & (1L << 31)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			pi.flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	case 0x1182:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			 "Detected SiS 1182/966/680 SATA controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		pi.flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	case 0x1183:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ppi[0] = &sis_info133_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ppi[1] = &sis_info133_for_sata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		if (ap->flags & ATA_FLAG_SATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		    ap->flags & ATA_FLAG_SLAVE_POSS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			rc = ata_slave_link_init(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		mmio = host->iomap[SIS_SCR_PCI_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		host->ports[0]->ioaddr.scr_addr = mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	pci_intx(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				 IRQF_SHARED, &sis_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) module_pci_driver(sis_pci_driver);