^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005 Tejun Heo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on preview driver from Silicon Image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRV_NAME "sata_sil24"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_VERSION "1.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Port request block (PRB) 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct sil24_prb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __le16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __le16 prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __le32 rx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 fis[6 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Scatter gather entry (SGE) 16 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sil24_sge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __le64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __le32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __le32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SIL24_HOST_BAR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SIL24_PORT_BAR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* sil24 fetches in chunks of 64bytes. The first block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * contains the PRB and two SGEs. From the second block, it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * consisted of four SGEs and called SGT. Calculate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * number of SGTs that fit into one page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SIL24_PRB_SZ = sizeof(struct sil24_prb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) + 2 * sizeof(struct sil24_sge),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) / (4 * sizeof(struct sil24_sge)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* This will give us one unused SGEs for ATA. This extra SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * will be used to store CDB for ATAPI devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Global controller registers (128 bytes @ BAR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* 32 bit regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) HOST_CTRL = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) HOST_IRQ_STAT = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) HOST_PHY_CFG = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) HOST_BIST_CTRL = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) HOST_BIST_PTRN = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HOST_BIST_STAT = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) HOST_MEM_BIST_STAT = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) HOST_FLASH_CMD = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* 8 bit regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) HOST_FLASH_DATA = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) HOST_TRANSITION_DETECT = 0x75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) HOST_GPIO_CTRL = 0x76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) HOST_I2C_ADDR = 0x78, /* 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) HOST_I2C_DATA = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) HOST_I2C_XFER_CNT = 0x7e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) HOST_I2C_CTRL = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* HOST_SLOT_STAT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) HOST_SSTAT_ATTN = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* HOST_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Port registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PORT_REGS_SIZE = 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PORT_PMP_STATUS = 0x0000, /* port device status offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* 32 bit regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PORT_ACTIVATE_UPPER_ADDR= 0x101c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PORT_CMD_ERR = 0x1024, /* command error number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PORT_FIS_CFG = 0x1028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PORT_FIFO_THRES = 0x102c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* 16 bit regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PORT_DECODE_ERR_CNT = 0x1040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PORT_DECODE_ERR_THRESH = 0x1042,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PORT_CRC_ERR_CNT = 0x1044,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PORT_CRC_ERR_THRESH = 0x1046,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PORT_HSHK_ERR_CNT = 0x1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PORT_HSHK_ERR_THRESH = 0x104a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 32 bit regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PORT_PHY_CFG = 0x1050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PORT_SLOT_STAT = 0x1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PORT_CONTEXT = 0x1e04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PORT_SCONTROL = 0x1f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PORT_SSTATUS = 0x1f04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PORT_SERROR = 0x1f08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PORT_SACTIVE = 0x1f0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* PORT_CTRL_STAT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PORT_CS_PORT_RST = (1 << 0), /* port reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PORT_CS_DEV_RST = (1 << 1), /* device reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PORT_CS_INIT = (1 << 2), /* port initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* PORT_IRQ_STAT/ENABLE_SET/CLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* bits[11:0] are masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PORT_IRQ_ERROR = (1 << 1), /* command execution error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* bits[27:16] are unmasked (raw) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PORT_IRQ_RAW_SHIFT = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PORT_IRQ_MASKED_MASK = 0x7ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PORT_IRQ_STEER_SHIFT = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* PORT_CMD_ERR constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* bits of PRB control field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* PRB protocol field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PRB_PROT_PACKET = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PRB_PROT_TCQ = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PRB_PROT_NCQ = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PRB_PROT_READ = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PRB_PROT_WRITE = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PRB_PROT_TRANSPARENT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Other constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SGE_TRM = (1 << 31), /* Last SGE in chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SGE_LNK = (1 << 30), /* linked list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) Points to SGT, not SGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SGE_DRD = (1 << 29), /* discard data read (/dev/null)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) data address ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SIL24_MAX_CMDS = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* board id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BID_SIL3124 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) BID_SIL3132 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) BID_SIL3131 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* host flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ATA_FLAG_AN | ATA_FLAG_PMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IRQ_STAT_4PORTS = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct sil24_ata_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct sil24_prb prb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct sil24_sge sge[SIL24_MAX_SGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct sil24_atapi_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct sil24_prb prb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 cdb[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct sil24_sge sge[SIL24_MAX_SGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) union sil24_cmd_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct sil24_ata_block ata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct sil24_atapi_block atapi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct sil24_cerr_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int err_mask, action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) const char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } sil24_cerr_db[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [0] = { AC_ERR_DEV, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "device error" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "device error via D2H FIS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "device error via SDB FIS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "error in data FIS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "failed to transmit command FIS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "protocol mismatch" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "data direction mismatch" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "ran out of SGEs while writing" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "ran out of SGEs while reading" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "invalid data direction for ATAPI CDB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "SGT not on qword boundary" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "PCI target abort while fetching SGT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "PCI master abort while fetching SGT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "PCI parity error while fetching SGT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "PRB not on qword boundary" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "PCI target abort while fetching PRB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "PCI master abort while fetching PRB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "PCI parity error while fetching PRB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "undefined error while transferring data" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "PCI target abort while transferring data" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "PCI master abort while transferring data" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "PCI parity error while transferring data" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "FIS received while sending service FIS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * ap->private_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * The preview driver always returned 0 for status. We emulate it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * here from the previous interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct sil24_port_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dma_addr_t cmd_block_dma; /* DMA base addr for them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int do_port_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void sil24_dev_config(struct ata_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int sil24_qc_defer(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void sil24_pmp_attach(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void sil24_pmp_detach(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void sil24_freeze(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void sil24_thaw(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int sil24_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int sil24_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void sil24_error_handler(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int sil24_port_start(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int sil24_pci_device_resume(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int sil24_port_resume(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct pci_device_id sil24_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct pci_driver sil24_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .id_table = sil24_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .probe = sil24_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .resume = sil24_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct scsi_host_template sil24_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ATA_NCQ_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .can_queue = SIL24_MAX_CMDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .sg_tablesize = SIL24_MAX_SGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .dma_boundary = ATA_DMA_BOUNDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .tag_alloc_policy = BLK_TAG_ALLOC_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct ata_port_operations sil24_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .inherits = &sata_pmp_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .qc_defer = sil24_qc_defer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .qc_prep = sil24_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .qc_issue = sil24_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .qc_fill_rtf = sil24_qc_fill_rtf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .freeze = sil24_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .thaw = sil24_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .softreset = sil24_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .hardreset = sil24_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .pmp_softreset = sil24_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .pmp_hardreset = sil24_pmp_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .error_handler = sil24_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .post_internal_cmd = sil24_post_internal_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .dev_config = sil24_dev_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .scr_read = sil24_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .scr_write = sil24_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .pmp_attach = sil24_pmp_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .pmp_detach = sil24_pmp_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .port_start = sil24_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .port_resume = sil24_port_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static bool sata_sil24_msi; /* Disable MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Use bits 30-31 of port_flags to encode available port numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Current maxium is 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct ata_port_info sil24_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* sil_3124 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SIL24_FLAG_PCIX_IRQ_WOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .port_ops = &sil24_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* sil_3132 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .port_ops = &sil24_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* sil_3131/sil_3531 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .port_ops = &sil24_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int sil24_tag(int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (unlikely(ata_tag_internal(tag)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static unsigned long sil24_port_offset(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ap->port_no * PORT_REGS_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void __iomem *sil24_port_base(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void sil24_dev_config(struct ata_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) void __iomem *port = sil24_port_base(dev->link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (dev->cdb_len == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct sil24_prb __iomem *prb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 fis[6 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) memcpy_fromio(fis, prb->fis, sizeof(fis));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ata_tf_from_fis(fis, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int sil24_scr_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [SCR_CONTROL] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [SCR_STATUS] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [SCR_ERROR] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [SCR_ACTIVE] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void sil24_config_port(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* configure IRQ WoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* zero error counters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writew(0x8000, port + PORT_DECODE_ERR_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) writew(0x8000, port + PORT_CRC_ERR_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) writew(0x8000, port + PORT_HSHK_ERR_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) writew(0x0000, port + PORT_DECODE_ERR_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) writew(0x0000, port + PORT_CRC_ERR_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writew(0x0000, port + PORT_HSHK_ERR_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* always use 64bit activation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* clear port multiplier enable and resume bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void sil24_config_pmp(struct ata_port *ap, int attached)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (attached)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void sil24_clear_pmp(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) writel(0, pmp_base + PORT_PMP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) writel(0, pmp_base + PORT_PMP_QACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int sil24_init_port(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct sil24_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* clear PMP error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (sata_pmp_attached(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sil24_clear_pmp(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ata_wait_register(ap, port + PORT_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PORT_CS_INIT, PORT_CS_INIT, 10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PORT_CS_RDY, 0, 10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pp->do_port_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ap->link.eh_context.i.action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) const struct ata_taskfile *tf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int is_cmd, u32 ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned long timeout_msec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct sil24_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dma_addr_t paddr = pp->cmd_block_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 irq_enabled, irq_mask, irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) prb->ctrl = cpu_to_le16(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* temporarily plug completion and error interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * The barrier is required to ensure that writes to cmd_block reach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * the memory before the write to PORT_CMD_ACTIVATE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) writel((u32)paddr, port + PORT_CMD_ACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 10, timeout_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) irq_stat >>= PORT_IRQ_RAW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (irq_stat & PORT_IRQ_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* force port into known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sil24_init_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (irq_stat & PORT_IRQ_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rc = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* restore IRQ enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int sil24_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned long timeout_msec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) const char *reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* put the port into known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (sil24_init_port(ap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) reason = "port not ready";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* do SRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (time_after(deadline, jiffies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) timeout_msec = jiffies_to_msecs(deadline - jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ata_tf_init(link->device, &tf); /* doesn't really matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) timeout_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (rc == -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) reason = "timeout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } else if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) reason = "SRST command error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) sil24_read_tf(ap, 0, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *class = ata_dev_classify(&tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) DPRINTK("EXIT, class=%u\n", *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ata_link_err(link, "softreset failed (%s)\n", reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int sil24_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct sil24_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int did_port_rst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const char *reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int tout_msec, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Sometimes, DEV_RST is not enough to recover the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * This happens often after PM DMA CS errata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (pp->do_port_rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ata_port_warn(ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "controller in dubious state, performing PORT_RST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ata_msleep(ap, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 10, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* restore port configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) sil24_config_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sil24_config_pmp(ap, ap->nr_pmp_links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pp->do_port_rst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) did_port_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* sil24 does the right thing(tm) without any protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) sata_set_spd(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) tout_msec = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ata_link_online(link))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) tout_msec = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tout_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* SStatus oscillates between zero and valid status after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * DEV_RST, debounce it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) reason = "PHY debouncing failed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (tmp & PORT_CS_DEV_RST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ata_link_offline(link))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) reason = "link not ready";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Sil24 doesn't store signature FIS after hardreset, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * can't wait for BSY to clear. Some devices take a long time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * to get ready and those devices will choke if we don't wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * for BSY clearance here. Tell libata to perform follow-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * softreset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!did_port_rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) pp->do_port_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ata_link_err(link, "hardreset failed (%s)\n", reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct sil24_sge *sge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct sil24_sge *last_sge = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned int si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) sge->addr = cpu_to_le64(sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) sge->cnt = cpu_to_le32(sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) sge->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) last_sge = sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) sge++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) last_sge->flags = cpu_to_le32(SGE_TRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int sil24_qc_defer(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct ata_link *link = qc->dev->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u8 prot = qc->tf.protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * There is a bug in the chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Port LRAM Causes the PRB/SGT Data to be Corrupted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * If the host issues a read request for LRAM and SActive registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * while active commands are available in the port, PRB/SGT data in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * the LRAM can become corrupted. This issue applies only when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * reading from, but not writing to, the LRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * Therefore, reading LRAM when there is no particular error [and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * other commands may be outstanding] is prohibited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * To avoid this bug there are two situations where a command must run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * exclusive of any other commands on the port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * - ATAPI commands which check the sense data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int is_excl = (ata_is_atapi(prot) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) (qc->flags & ATA_QCFLAG_RESULT_TF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (unlikely(ap->excl_link)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (link == ap->excl_link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (ap->nr_active_links)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ATA_DEFER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ATA_DEFER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else if (unlikely(is_excl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ap->excl_link = link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ap->nr_active_links)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ATA_DEFER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ata_std_qc_defer(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct sil24_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) union sil24_cmd_block *cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct sil24_prb *prb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct sil24_sge *sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u16 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) cb = &pp->cmd_block[sil24_tag(qc->hw_tag)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!ata_is_atapi(qc->tf.protocol)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) prb = &cb->ata.prb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) sge = cb->ata.sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ata_is_data(qc->tf.protocol)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u16 prot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ctrl = PRB_CTRL_PROTOCOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (ata_is_ncq(qc->tf.protocol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) prot |= PRB_PROT_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (qc->tf.flags & ATA_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) prot |= PRB_PROT_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) prot |= PRB_PROT_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) prb->prot = cpu_to_le16(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) prb = &cb->atapi.prb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) sge = cb->atapi.sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (ata_is_data(qc->tf.protocol)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (qc->tf.flags & ATA_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ctrl = PRB_CTRL_PACKET_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ctrl = PRB_CTRL_PACKET_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) prb->ctrl = cpu_to_le16(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (qc->flags & ATA_QCFLAG_DMAMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) sil24_fill_sg(qc, sge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct sil24_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) unsigned int tag = sil24_tag(qc->hw_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) void __iomem *activate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) activate = port + PORT_CMD_ACTIVATE + tag * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * The barrier is required to ensure that writes to cmd_block reach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * the memory before the write to PORT_CMD_ACTIVATE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) writel((u32)paddr, activate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) writel((u64)paddr >> 32, activate + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) sil24_read_tf(qc->ap, qc->hw_tag, &qc->result_tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static void sil24_pmp_attach(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u32 *gscr = ap->link.device->gscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) sil24_config_pmp(ap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) sil24_init_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) sata_pmp_gscr_devid(gscr) == 0x4140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ata_port_info(ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "disabling NCQ support due to sil24-mv4140 quirk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ap->flags &= ~ATA_FLAG_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static void sil24_pmp_detach(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) sil24_init_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) sil24_config_pmp(ap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ap->flags |= ATA_FLAG_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) rc = sil24_init_port(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ata_link_err(link, "hardreset failed (port not ready)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return sata_std_hardreset(link, class, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void sil24_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * PORT_IRQ_ENABLE instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static void sil24_thaw(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) tmp = readl(port + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) writel(tmp, port + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* turn IRQ back on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static void sil24_error_intr(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct sil24_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct ata_queued_cmd *qc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct ata_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct ata_eh_info *ehi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int abort = 0, freeze = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* on error, we need to clear IRQ explicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) irq_stat = readl(port + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) writel(irq_stat, port + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* first, analyze and record host port events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) link = &ap->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ehi = &link->eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ata_ehi_clear_desc(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ata_ehi_push_desc(ehi, "SDB notify");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) sata_async_notification(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ata_ehi_hotplugged(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ata_ehi_push_desc(ehi, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) irq_stat & PORT_IRQ_PHYRDY_CHG ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "PHY RDY changed" : "device exchanged");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (irq_stat & PORT_IRQ_UNK_FIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ehi->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ata_ehi_push_desc(ehi, "unknown FIS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* deal with command error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (irq_stat & PORT_IRQ_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) const struct sil24_cerr_info *ci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned int err_mask = 0, action = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u32 context, cerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int pmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* DMA Context Switch Failure in Port Multiplier Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * errata. If we have active commands to 3 or more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * devices, any error condition on active devices can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * corrupt DMA context switching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (ap->nr_active_links >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ehi->err_mask |= AC_ERR_OTHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ata_ehi_push_desc(ehi, "PMP DMA CS errata");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pp->do_port_rst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* find out the offending link and qc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (sata_pmp_attached(ap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) context = readl(port + PORT_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) pmp = (context >> 5) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (pmp < ap->nr_pmp_links) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) link = &ap->pmp_link[pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ehi = &link->eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) qc = ata_qc_from_tag(ap, link->active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ata_ehi_clear_desc(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) qc = ata_qc_from_tag(ap, link->active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* analyze CMD_ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) cerr = readl(port + PORT_CMD_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (cerr < ARRAY_SIZE(sil24_cerr_db))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ci = &sil24_cerr_db[cerr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (ci && ci->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) err_mask |= ci->err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) action |= ci->action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (action & ATA_EH_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ata_ehi_push_desc(ehi, "%s", ci->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) err_mask |= AC_ERR_OTHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ata_ehi_push_desc(ehi, "unknown command error %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) cerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* record error info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) qc->err_mask |= err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ehi->err_mask |= err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ehi->action |= action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* if PMP, resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (sata_pmp_attached(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* freeze or abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (freeze)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) else if (abort) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ata_link_abort(qc->dev->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ata_port_abort(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static inline void sil24_host_intr(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) u32 slot_stat, qc_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* If PCIX_IRQ_WOC, there's an inherent race window between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * clearing IRQ pending status and reading PORT_SLOT_STAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * which may cause spurious interrupts afterwards. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * unavoidable and much better than losing interrupts which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * happens if IRQ pending is cleared after reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * PORT_SLOT_STAT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) slot_stat = readl(port + PORT_SLOT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) sil24_error_intr(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) qc_active = slot_stat & ~HOST_SSTAT_ATTN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) rc = ata_qc_complete_multiple(ap, qc_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (rc > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ehi->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ehi->action |= ATA_EH_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* spurious interrupts are expected if PCIX_IRQ_WOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ata_port_info(ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) slot_stat, ap->link.active_tag, ap->link.sactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) status = readl(host_base + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (status == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dev_err(host->dev, "IRQ status == 0xffffffff, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "PCI fault or device removal?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (!(status & IRQ_STAT_4PORTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) for (i = 0; i < host->n_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (status & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) sil24_host_intr(host->ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void sil24_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct sil24_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (sil24_init_port(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ata_eh_freeze_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) sata_pmp_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pp->do_port_rst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* make DMA engine forget about the failed command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ata_eh_freeze_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static int sil24_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct sil24_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) union sil24_cmd_block *cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dma_addr_t cb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (!cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) pp->cmd_block = cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pp->cmd_block_dma = cb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ap->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static void sil24_init_controller(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* GPIO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) writel(0, host_base + HOST_FLASH_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* clear global reset & mask interrupts during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) writel(0, host_base + HOST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* init ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) void __iomem *port = sil24_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* Initial PHY setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) writel(0x20c, port + PORT_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* Clear port RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) tmp = readl(port + PORT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (tmp & PORT_CS_PORT_RST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PORT_CS_PORT_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PORT_CS_PORT_RST, 10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (tmp & PORT_CS_PORT_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev_err(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "failed to clear port RST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* configure port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) sil24_config_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /* Turn on interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct ata_port_info pi = sil24_port_info[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) const struct ata_port_info *ppi[] = { &pi, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) void __iomem * const *iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* cause link error if sil24_cmd_block is sized wrongly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* acquire resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) rc = pcim_iomap_regions(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* apply workaround for completion IRQ loss on PCI-X errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) "Applying completion IRQ loss on PCI-X errata fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* allocate and fill host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) host = ata_host_alloc_pinfo(&pdev->dev, ppi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) SIL24_FLAG2NPORTS(ppi[0]->flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) host->iomap = iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* configure and activate the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dev_err(&pdev->dev, "DMA enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Set max read request size to 4096. This slightly increases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * write throughput for pci-e variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) pcie_set_readrq(pdev, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) sil24_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (sata_sil24_msi && !pci_enable_msi(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev_info(&pdev->dev, "Using MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) pci_intx(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) &sil24_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static int sil24_pci_device_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) sil24_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static int sil24_port_resume(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) sil24_config_pmp(ap, ap->nr_pmp_links);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) module_pci_driver(sil24_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) MODULE_AUTHOR("Tejun Heo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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