^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sata_sil.c - Silicon Image SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please ALWAYS copy linux-ide@vger.kernel.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on emails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2003-2005 Red Hat, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright 2003 Benjamin Herrenschmidt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Documentation for SiI 3112:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Other errata and documentation available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRV_NAME "sata_sil"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRV_VERSION "2.4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIL_DMA_BOUNDARY 0x7fffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SIL_MMIO_BAR = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * host flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SIL_FLAG_NO_SATA_IRQ = (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SIL_FLAG_MOD15WRITE = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Controller IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) sil_3112 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sil_3112_no_sata_irq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) sil_3512 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) sil_3114 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SIL_SYSCFG = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* SYSCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SIL_MASK_IDE0_INT = (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SIL_MASK_IDE1_INT = (1 << 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SIL_MASK_IDE2_INT = (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SIL_MASK_IDE3_INT = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SIL_MASK_4PORT = SIL_MASK_2PORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* BMDMA/BMDMA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SIL_INTR_STEERING = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* SIEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SIL_QUIRK_MOD15WRITE = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SIL_QUIRK_UDMA5MAX = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int sil_pci_device_resume(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void sil_dev_config(struct ata_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static enum ata_completion_errors sil_qc_prep(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void sil_bmdma_setup(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void sil_bmdma_start(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void sil_bmdma_stop(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void sil_freeze(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void sil_thaw(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct pci_device_id sil_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* TODO firmware versions should be added - eric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct sil_drivelist {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const char *product;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } sil_blacklist [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { "ST320012AS", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { "ST330013AS", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { "ST340017AS", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { "ST360015AS", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { "ST380023AS", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { "TOSHIBA MK2561GSYN", SIL_QUIRK_MOD15WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct pci_driver sil_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .id_table = sil_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .probe = sil_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .resume = sil_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct scsi_host_template sil_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ATA_BASE_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /** These controllers support Large Block Transfer which allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) transfer chunks up to 2GB and which cross 64KB boundaries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) therefore the DMA limits are more relaxed than standard ATA SFF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .dma_boundary = SIL_DMA_BOUNDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .sg_tablesize = ATA_MAX_PRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct ata_port_operations sil_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .inherits = &ata_bmdma32_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .dev_config = sil_dev_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .set_mode = sil_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .bmdma_setup = sil_bmdma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .bmdma_start = sil_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .bmdma_stop = sil_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .qc_prep = sil_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .freeze = sil_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .thaw = sil_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .scr_read = sil_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .scr_write = sil_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct ata_port_info sil_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* sil_3112 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .port_ops = &sil_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* sil_3112_no_sata_irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SIL_FLAG_NO_SATA_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .port_ops = &sil_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* sil_3512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .port_ops = &sil_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* sil_3114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .port_ops = &sil_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* per-port register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* TODO: we can probably calculate rather than use a table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long tf; /* ATA taskfile register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long ctl; /* ATA control/altstatus register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long bmdma; /* DMA register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long bmdma2; /* DMA register block #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long scr; /* SATA control register block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long sien; /* SATA Interrupt Enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long xfer_mode;/* data transfer mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long sfis_cfg; /* SATA FIS reception config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } sil_port[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* port 0 ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* ... port 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MODULE_AUTHOR("Jeff Garzik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int slow_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) module_param(slow_down, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void sil_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* clear start/stop bit - can safely always write 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) iowrite8(0, bmdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ata_sff_dma_pause(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void sil_bmdma_setup(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void __iomem *bmdma = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* load PRD table addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) iowrite32(ap->bmdma_prd_dma, bmdma + ATA_DMA_TABLE_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* issue r/w command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ap->ops->sff_exec_command(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void sil_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 dmactl = ATA_DMA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* set transfer direction, start host DMA transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) Note: For Large Block Transfer to work, the DMA must be started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) using the bmdma2 register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dmactl |= ATA_DMA_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) iowrite8(dmactl, bmdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* The way God intended PCI IDE scatter/gather lists to look and behave... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void sil_fill_sg(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct ata_bmdma_prd *prd, *last_prd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) prd = &ap->bmdma_prd[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Note h/w doesn't support 64-bit, so we unconditionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * truncate dma_addr_t to u32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 addr = (u32) sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 sg_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) prd->addr = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) prd->flags_len = cpu_to_le32(sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) last_prd = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) prd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (likely(last_prd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) last_prd->flags_len |= cpu_to_le32(ATA_PRD_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static enum ata_completion_errors sil_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!(qc->flags & ATA_QCFLAG_DMAMAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sil_fill_sg(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 cache_line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return cache_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * sil_set_mode - wrap set_mode functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @link: link to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @r_failed: returned device when we fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Wrap the libata method for device setup as after the setup we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * to inspect the results and do some configuration work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 tmp, dev_mode[2] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rc = ata_do_set_mode(link, r_failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ata_for_each_dev(dev, link, ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!ata_dev_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_mode[dev->devno] = 0; /* PIO0/1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else if (dev->flags & ATA_DFLAG_PIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_mode[dev->devno] = 1; /* PIO3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_mode[dev->devno] = 3; /* UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* value 2 indicates MDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tmp = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tmp |= dev_mode[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tmp |= (dev_mode[1] << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel(tmp, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) readl(addr); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline void __iomem *sil_scr_addr(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int sc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) void __iomem *offset = ap->ioaddr.scr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (sc_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case SCR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return offset + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case SCR_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return offset + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case SCR_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *val = readl(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void __iomem *mmio = sil_scr_addr(link->ap, sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writel(val, mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 serror = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* SIEN doesn't mask SATA IRQs on some 3112s. Those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * controllers continue to assert IRQ as long as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * SError bits are pending. Clear SError immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) sil_scr_read(&ap->link, SCR_ERROR, &serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sil_scr_write(&ap->link, SCR_ERROR, serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Sometimes spurious interrupts occur, double check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * it's PHYRDY CHG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (serror & SERR_PHYRDY_CHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ap->link.eh_info.serror |= serror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) goto freeze;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!(bmdma2 & SIL_DMA_COMPLETE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* this sometimes happens, just clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ap->ops->sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Check whether we are expecting interrupt in this state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) switch (ap->hsm_task_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case HSM_ST_FIRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Some pre-ATAPI-4 devices assert INTRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * at this state when ready to receive CDB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * The flag was turned on only for atapi devices. No
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * need to check ata_is_atapi(qc->tf.protocol) again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto err_hsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case HSM_ST_LAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ata_is_dma(qc->tf.protocol)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* clear DMA-Start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ap->ops->bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (bmdma2 & SIL_DMA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) qc->err_mask |= AC_ERR_HOST_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ap->hsm_task_state = HSM_ST_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case HSM_ST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto err_hsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* check main status, clearing INTRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) status = ap->ops->sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (unlikely(status & ATA_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto err_hsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* ack bmdma irq events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ata_bmdma_irq_clear(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* kick HSM in the ass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ata_sff_hsm_move(ap, qc, status, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err_hsm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) qc->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) freeze:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static irqreturn_t sil_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* turn off SATA_IRQ if not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bmdma2 &= ~SIL_DMA_SATA_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (bmdma2 == 0xffffffff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) sil_host_intr(ap, bmdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void sil_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) writel(0, mmio_base + sil_port[ap->port_no].sien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* plug IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tmp = readl(mmio_base + SIL_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) tmp |= SIL_MASK_IDE0_INT << ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writel(tmp, mmio_base + SIL_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) readl(mmio_base + SIL_SYSCFG); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Ensure DMA_ENABLE is off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * This is because the controller will not give us access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * taskfile registers while a DMA is in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ap->ioaddr.bmdma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* According to ata_bmdma_stop, an HDMA transition requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * on PIO cycle. But we can't read a taskfile register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ioread8(ap->ioaddr.bmdma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void sil_thaw(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ap->ops->sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ata_bmdma_irq_clear(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* turn on SATA IRQ if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* turn on IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tmp = readl(mmio_base + SIL_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writel(tmp, mmio_base + SIL_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * sil_dev_config - Apply device/host-specific errata fixups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * @dev: Device to be examined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * After the IDENTIFY [PACKET] DEVICE step is complete, and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * device is known to be present, this function is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * We apply two errata fixups which are specific to Silicon Image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * a Seagate and a Maxtor fixup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * For certain Seagate devices, we must limit the maximum sectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * to under 8K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * For certain Maxtor devices, we must not program the drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * beyond udma5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Both fixups are unfairly pessimistic. As soon as I get more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * information on these errata, I will create a more exhaustive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * list, and apply the fixups to only the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * devices/hosts/firmwares that need it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * The Maxtor quirk is in the blacklist, but I'm keeping the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * pessimistic fix for the following reasons...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * - There seems to be less info on it, only one device gleaned off the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * Windows driver, maybe only one is affected. More info would be greatly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * appreciated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * - But then again UDMA5 is hardly anything to complain about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void sil_dev_config(struct ata_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct ata_port *ap = dev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned int n, quirks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* This controller doesn't support trim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev->horkage |= ATA_HORKAGE_NOTRIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) for (n = 0; sil_blacklist[n].product; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!strcmp(sil_blacklist[n].product, model_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) quirks = sil_blacklist[n].quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* limit requests to 15 sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (slow_down ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ((ap->flags & SIL_FLAG_MOD15WRITE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) (quirks & SIL_QUIRK_MOD15WRITE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (print_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ata_dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "applying Seagate errata fix (mod15write workaround)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev->max_sectors = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* limit to udma5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (quirks & SIL_QUIRK_UDMA5MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (print_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ata_dev_info(dev, "applying Maxtor errata fix %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) model_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev->udma_mask &= ATA_UDMA5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void sil_init_controller(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct pci_dev *pdev = to_pci_dev(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u8 cls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Initialize FIFO PCI bus arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) cls = sil_get_device_cache_line(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (cls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) cls >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) cls++; /* cls = (line_size/8)+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) for (i = 0; i < host->n_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writew(cls << 8 | cls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) mmio_base + sil_port[i].fifo_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "cache line size not set. Driver may not function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Apply R_ERR on DMA activate FIS errata workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (i = 0, cnt = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tmp = readl(mmio_base + sil_port[i].sfis_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if ((tmp & 0x3) != 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (!cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "Applying R_ERR on DMA activate FIS errata fix\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (host->n_ports == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* flip the magic "make 4 ports work" bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) tmp = readl(mmio_base + sil_port[2].bmdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if ((tmp & SIL_INTR_STEERING) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) writel(tmp | SIL_INTR_STEERING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mmio_base + sil_port[2].bmdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static bool sil_broken_system_poweroff(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct dmi_system_id broken_systems[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .ident = "HP Compaq nx6325",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* PCI slot number of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .driver_data = (void *)0x12UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (dmi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned long slot = (unsigned long)dmi->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* apply the quirk only to on-board controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return slot == PCI_SLOT(pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int board_id = ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct ata_port_info pi = sil_port_info[board_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) const struct ata_port_info *ppi[] = { &pi, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int n_ports, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) n_ports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (board_id == sil_3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) n_ports = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (sil_broken_system_poweroff(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ATA_FLAG_NO_HIBERNATE_SPINDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "on poweroff and hibernation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* acquire resources and fill host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (rc == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pcim_pin_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) host->iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mmio_base = host->iomap[SIL_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ioaddr->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ioaddr->scr_addr = mmio_base + sil_port[i].scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ata_sff_std_ports(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* initialize and activate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) sil_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) &sil_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int sil_pci_device_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sil_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) module_pci_driver(sil_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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