^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sata_inic162x.c - Driver for Initio 162x SATA controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006 SUSE Linux Products GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006 Tejun Heo <teheo@novell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * **** WARNING ****
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This driver never worked properly and unfortunately data corruption is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * relatively common. There isn't anyone working on the driver and there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * no support from the vendor. Do not use this driver in any production
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * environment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * https://bugzilla.kernel.org/show_bug.cgi?id=60565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * *****************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * This controller is eccentric and easily locks up if something isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * right. Documentation is available at initio's website but it only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * documents registers (not programming model).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This driver has interesting history. The first version was written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * from the documentation and a 2.4 IDE driver posted on a Taiwan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * company, which didn't use any IDMA features and couldn't handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * LBA48. The resulting driver couldn't handle LBA48 devices either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * making it pretty useless.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * After a while, initio picked the driver up, renamed it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * sata_initio162x, updated it to use IDMA for ATA DMA commands and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * posted it on their website. It only used ATA_PROT_DMA for IDMA and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * attaching both devices and issuing IDMA and !IDMA commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * simultaneously broke it due to PIRQ masking interaction but it did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * show how to use the IDMA (ADMA + some initio specific twists)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Then, I picked up their changes again and here's the usable driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * which uses IDMA for everything. Everything works now including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * LBA48, CD/DVD burning, suspend/resume and hotplug. There are some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * issues tho. Result Tf is not resported properly, NCQ isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * supported yet and CD/DVD writing works with DMA assisted PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * protocol (which, for native SATA devices, shouldn't cause any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * noticeable difference).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Anyways, so, here's finally a working driver for inic162x. Enjoy!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * initio: If you guys wanna improve the driver regarding result TF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * access and other stuff, please feel free to contact me. I'll be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * happy to assist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRV_NAME "sata_inic162x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRV_VERSION "0.4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MMIO_BAR_PCI = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MMIO_BAR_CARDBUS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) NR_PORTS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IDMA_CPB_TBL_SIZE = 4 * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) INIC_DMA_BOUNDARY = 0xffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HOST_ACTRL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) HOST_CTL = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) HOST_STAT = 0x7e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) HOST_IRQ_STAT = 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) HOST_IRQ_MASK = 0xbe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PORT_SIZE = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* registers for ATA TF operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PORT_TF_DATA = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PORT_TF_FEATURE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PORT_TF_NSECT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PORT_TF_LBAL = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PORT_TF_LBAM = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PORT_TF_LBAH = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PORT_TF_DEVICE = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PORT_TF_COMMAND = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PORT_TF_ALT_STAT = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PORT_IRQ_STAT = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PORT_IRQ_MASK = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PORT_PRD_CTL = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PORT_PRD_ADDR = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PORT_PRD_XFERLEN = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PORT_CPB_CPBLAR = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PORT_CPB_PTQFIFO = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* IDMA register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PORT_IDMA_CTL = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PORT_IDMA_STAT = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PORT_RPQ_FIFO = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PORT_RPQ_CNT = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PORT_SCR = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* HOST_CTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) HCTL_LEDEN = (1 << 3), /* enable LED operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) HCTL_IRQOFF = (1 << 8), /* global IRQ off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) HCTL_PWRDWN = (1 << 12), /* power down PHYs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) HCTL_RPGSEL = (1 << 15), /* register page select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) HCTL_RPGSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* HOST_IRQ_(STAT|MASK) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) HIRQ_PORT0 = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) HIRQ_PORT1 = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) HIRQ_SOFT = (1 << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) HIRQ_GLOBAL = (1 << 15), /* STAT only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* PORT_IRQ_(STAT|MASK) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PIRQ_OFFLINE = (1 << 0), /* device unplugged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PIRQ_ONLINE = (1 << 1), /* device plugged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PIRQ_FATAL = (1 << 3), /* fatal error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PIRQ_ATA = (1 << 4), /* ATA interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PIRQ_MASK_FREEZE = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* PORT_PRD_CTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PRD_CTL_START = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PRD_CTL_WR = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* PORT_IDMA_CTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* PORT_IDMA_STAT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) IDMA_STAT_DONE = (1 << 7), /* ADMA done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* CPB Control Flags*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CPB_CTL_VALID = (1 << 0), /* CPB valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CPB_CTL_QUEUED = (1 << 1), /* queued command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* CPB Response Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CPB_RESP_DONE = (1 << 0), /* ATA command complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CPB_RESP_REL = (1 << 1), /* ATA release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* PRD Control Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PRD_DRAIN = (1 << 1), /* ignore data excess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PRD_CDB = (1 << 2), /* atapi packet command pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PRD_DMA = (1 << 4), /* data transfer method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PRD_IOM = (1 << 6), /* io/memory transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PRD_END = (1 << 7), /* APRD chain end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Comman Parameter Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct inic_cpb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 resp_flags; /* Response Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 error; /* ATA Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 status; /* ATA Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 ctl_flags; /* Control Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __le32 len; /* Total Transfer Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le32 prd; /* First PRD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 rsvd[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* 16 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 feature; /* ATA Feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 hob_feature; /* ATA Ex. Feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 device; /* ATA Device/Head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 mirctl; /* Mirror Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 nsect; /* ATA Sector Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 hob_nsect; /* ATA Ex. Sector Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 lbal; /* ATA Sector Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 hob_lbal; /* ATA Ex. Sector Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 lbam; /* ATA Cylinder Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 hob_lbam; /* ATA Ex. Cylinder Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 lbah; /* ATA Cylinder High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 hob_lbah; /* ATA Ex. Cylinder High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 command; /* ATA Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 ctl; /* ATA Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 slave_error; /* Slave ATA Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 slave_status; /* Slave ATA Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Physical Region Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct inic_prd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __le32 mad; /* Physical Memory Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __le16 len; /* Transfer Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 flags; /* Control Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct inic_pkt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct inic_cpb cpb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 cdb[ATAPI_CDB_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct inic_host_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 cached_hctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct inic_port_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct inic_pkt *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dma_addr_t pkt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 *cpb_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dma_addr_t cpb_tbl_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct scsi_host_template inic_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ATA_BASE_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * This controller is braindamaged. dma_boundary is 0xffff like others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * but it will lock up the whole machine HARD if 65536 byte PRD entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * is fed. Reduce maximum segment size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .dma_boundary = INIC_DMA_BOUNDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .max_segment_size = 65536 - 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const int scr_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [SCR_STATUS] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [SCR_ERROR] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [SCR_CONTROL] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void __iomem *inic_port_base(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct inic_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return hpriv->mmio_base + ap->port_no * PORT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void inic_reset_port(void __iomem *port_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* stop IDMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) readw(idma_ctl); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* mask IRQ and assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writew(IDMA_CTL_RST_IDMA, idma_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) readw(idma_ctl); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* release reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writew(0, idma_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writeb(0xff, port_base + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *val = readl(scr_addr + scr_map[sc_reg] * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* this controller has stuck DIAG.N, ignore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (sc_reg == SCR_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *val &= ~SERR_PHYRDY_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel(val, scr_addr + scr_map[sc_reg] * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void inic_stop_idma(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) readb(port_base + PORT_RPQ_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) readb(port_base + PORT_RPQ_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writew(0, port_base + PORT_IDMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct inic_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct inic_cpb *cpb = &pp->pkt->cpb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bool freeze = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ata_ehi_clear_desc(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) irq_stat, idma_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) inic_stop_idma(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ata_ehi_push_desc(ehi, "hotplug");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ata_ehi_hotplugged(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) freeze = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (idma_stat & IDMA_STAT_PERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ata_ehi_push_desc(ehi, "PCI error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) freeze = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (idma_stat & IDMA_STAT_CPBERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ata_ehi_push_desc(ehi, "CPB error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (cpb->resp_flags & CPB_RESP_IGNORED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) __ata_ehi_push_desc(ehi, " ignored");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ehi->err_mask |= AC_ERR_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) freeze = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (cpb->resp_flags & CPB_RESP_ATA_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ehi->err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __ata_ehi_push_desc(ehi, " spurious-intr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ehi->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) freeze = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (cpb->resp_flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __ata_ehi_push_desc(ehi, " data-over/underflow");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ehi->err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) freeze = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (freeze)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ata_port_abort(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void inic_host_intr(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u16 idma_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* read and clear IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) irq_stat = readb(port_base + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writeb(irq_stat, port_base + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) idma_stat = readw(port_base + PORT_IDMA_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) inic_host_err_intr(ap, irq_stat, idma_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (unlikely(!qc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto spurious;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (likely(idma_stat & IDMA_STAT_DONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) inic_stop_idma(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Depending on circumstances, device error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * isn't reported by IDMA, check it explicitly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (unlikely(readb(port_base + PORT_TF_COMMAND) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (ATA_DF | ATA_ERR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) qc->err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ata_qc_complete(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) spurious:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static irqreturn_t inic_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct inic_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u16 host_irq_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int i, handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 0; i < NR_PORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (host_irq_stat & (HIRQ_PORT0 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) inic_host_intr(host->ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* For some reason ATAPI_PROT_DMA doesn't work for some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * commands including writes and other misc ops. Use PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * protocol instead, which BTW is driven by the DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * anyway, so it shouldn't make much difference for native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * SATA devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (atapi_cmd_type(qc->cdb[0]) == READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (qc->tf.flags & ATA_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) flags |= PRD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ata_is_dma(qc->tf.protocol))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) flags |= PRD_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) prd->mad = cpu_to_le32(sg_dma_address(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) prd->len = cpu_to_le16(sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) prd->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) prd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) WARN_ON(!si);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) prd[-1].flags |= PRD_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static enum ata_completion_errors inic_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct inic_port_priv *pp = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct inic_pkt *pkt = pp->pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct inic_cpb *cpb = &pkt->cpb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct inic_prd *prd = pkt->prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) bool is_atapi = ata_is_atapi(qc->tf.protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) bool is_data = ata_is_data(qc->tf.protocol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int cdb_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (is_atapi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cdb_len = qc->dev->cdb_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* prepare packet, based on initio driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) memset(pkt, 0, sizeof(struct inic_pkt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (is_atapi || is_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cpb->ctl_flags |= CPB_CTL_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cpb->device = qc->tf.device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cpb->feature = qc->tf.feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cpb->nsect = qc->tf.nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) cpb->lbal = qc->tf.lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cpb->lbam = qc->tf.lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cpb->lbah = qc->tf.lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (qc->tf.flags & ATA_TFLAG_LBA48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cpb->hob_feature = qc->tf.hob_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cpb->hob_nsect = qc->tf.hob_nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) cpb->hob_lbal = qc->tf.hob_lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cpb->hob_lbam = qc->tf.hob_lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cpb->hob_lbah = qc->tf.hob_lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cpb->command = qc->tf.command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* don't load ctl - dunno why. it's like that in the initio driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* setup PRD for CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (is_atapi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) prd->mad = cpu_to_le32(pp->pkt_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) offsetof(struct inic_pkt, cdb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) prd->len = cpu_to_le16(cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) prd->flags = PRD_CDB | PRD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!is_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) prd->flags |= PRD_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) prd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* setup sg table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (is_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) inic_fill_sg(prd, qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pp->cpb_tbl[0] = pp->pkt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* fire up the ADMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writeb(0, port_base + PORT_CPB_PTQFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) tf->feature = readb(port_base + PORT_TF_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) tf->nsect = readb(port_base + PORT_TF_NSECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) tf->lbal = readb(port_base + PORT_TF_LBAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tf->lbam = readb(port_base + PORT_TF_LBAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tf->lbah = readb(port_base + PORT_TF_LBAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tf->device = readb(port_base + PORT_TF_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tf->command = readb(port_base + PORT_TF_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct ata_taskfile *rtf = &qc->result_tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* FIXME: Except for status and error, result TF access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * doesn't work. I tried reading from BAR0/2, CPB and BAR5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * None works regardless of which command interface is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * For now return true iff status indicates device error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * This means that we're reporting bogus sector for RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * failures. Eeekk....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) inic_tf_read(qc->ap, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!(tf.command & ATA_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rtf->command = tf.command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) rtf->feature = tf.feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void inic_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) writeb(0xff, port_base + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void inic_thaw(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) writeb(0xff, port_base + PORT_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int inic_check_ready(struct ata_link *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) void __iomem *port_base = inic_port_base(link->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * SRST and SControl hardreset don't give valid signature on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * controller. Only controller specific hardreset mechanism works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int inic_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* hammer it into sane state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) inic_reset_port(port_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) writew(IDMA_CTL_RST_ATA, idma_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) readw(idma_ctl); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ata_msleep(ap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) writew(0, idma_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rc = sata_link_resume(link, timing, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ata_link_warn(link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "failed to resume link after reset (errno=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *class = ATA_DEV_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ata_link_online(link)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* wait for link to become ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) rc = ata_wait_after_reset(link, deadline, inic_check_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* link occupied, -ENODEV too is an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ata_link_warn(link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) "device not ready after hardreset (errno=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) inic_tf_read(ap, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *class = ata_dev_classify(&tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void inic_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) inic_reset_port(port_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ata_std_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* make DMA engine forget about the failed command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (qc->flags & ATA_QCFLAG_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) inic_reset_port(inic_port_base(qc->ap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static void init_port(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) void __iomem *port_base = inic_port_base(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct inic_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* clear packet and CPB table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) memset(pp->pkt, 0, sizeof(struct inic_pkt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* setup CPB lookup table addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int inic_port_resume(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) init_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int inic_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct inic_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* alloc and initialize private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ap->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Alloc resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) &pp->pkt_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (!pp->pkt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &pp->cpb_tbl_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!pp->cpb_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) init_port(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static struct ata_port_operations inic_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .inherits = &sata_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .check_atapi_dma = inic_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .qc_prep = inic_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .qc_issue = inic_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .qc_fill_rtf = inic_qc_fill_rtf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .freeze = inic_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .thaw = inic_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .hardreset = inic_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .error_handler = inic_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .post_internal_cmd = inic_post_internal_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .scr_read = inic_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .scr_write = inic_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .port_resume = inic_port_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .port_start = inic_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct ata_port_info inic_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .port_ops = &inic_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int init_controller(void __iomem *mmio_base, u16 hctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) hctl &= ~HCTL_KNOWN_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Soft reset whole controller. Spec says reset duration is 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * PCI clocks, be generous and give it 10ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) readw(mmio_base + HOST_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) val = readw(mmio_base + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!(val & HCTL_SOFTRST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (val & HCTL_SOFTRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* mask all interrupts and reset ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) void __iomem *port_base = mmio_base + i * PORT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) writeb(0xff, port_base + PORT_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) inic_reset_port(port_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* port IRQ is masked now, unmask global IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) val = readw(mmio_base + HOST_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writew(val, mmio_base + HOST_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int inic_pci_device_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct inic_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct inic_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) void __iomem * const *iomap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int mmio_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* alloc host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!host || !hpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Acquire resources and fill host. Note that PCI and cardbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * use different BARs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mmio_bar = MMIO_BAR_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mmio_bar = MMIO_BAR_CARDBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) host->iomap = iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) hpriv->mmio_base = iomap[mmio_bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Set dma_mask. This devices doesn't support 64bit addressing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_err(&pdev->dev, "32-bit DMA enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(&pdev->dev, "failed to initialize controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &inic_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const struct pci_device_id inic_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) { PCI_VDEVICE(INIT, 0x1622), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct pci_driver inic_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .id_table = inic_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .resume = inic_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .probe = inic_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) module_pci_driver(inic_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) MODULE_AUTHOR("Tejun Heo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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