^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Calxeda Highbank AHCI SATA platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2012 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ahci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SERDES_CR_CTL 0x80a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SERDES_CR_ADDR 0x80a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SERDES_CR_DATA 0x80a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CR_BUSY 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CR_START 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CR_WR_RDN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CPHY_TX_INPUT_STS 0x2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPHY_RX_INPUT_STS 0x2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CPHY_SATA_TX_OVERRIDE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPHY_SATA_RX_OVERRIDE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPHY_TX_OVERRIDE 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPHY_RX_OVERRIDE 0x2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPHY_LANE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPHY_HALF_RATE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPHY_SATA_DPLL_MODE 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPHY_SATA_DPLL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPHY_SATA_DPLL_RESET (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPHY_SATA_TX_ATTEN 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CPHY_SATA_TX_ATTEN_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CPHY_PHY_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CPHY_LANE_COUNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static DEFINE_SPINLOCK(cphy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * sata ports to their phys and then to their lanes within the phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct phy_lane_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 lane_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 phy_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 tx_atten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct phy_lane_info port_data[CPHY_PORT_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static DEFINE_SPINLOCK(sgpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCLOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLOAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SGPIO_PINS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SGPIO_PORTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct ecx_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 n_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* number of extra clocks that the SGPIO PIC controller expects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 pre_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 post_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct gpio_desc *sgpio_gpiod[SGPIO_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 sgpio_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 port_to_sgpio[SGPIO_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SGPIO_SIGNALS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ECX_ACTIVITY_BITS 0x300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ECX_ACTIVITY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ECX_LOCATE_BITS 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ECX_LOCATE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ECX_FAULT_BITS 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ECX_FAULT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 1 << (3 * pdata->port_to_sgpio[port] + shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (state & ECX_ACTIVITY_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ECX_ACTIVITY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ECX_ACTIVITY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (state & ECX_LOCATE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ECX_LOCATE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ECX_LOCATE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (state & ECX_FAULT_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ECX_FAULT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ECX_FAULT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Tell the LED controller that the signal has changed by raising the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * line for 50 uS and then lowering it for 50 uS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ssize_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ecx_plat_data *pdata = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int pmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct ahci_em_priv *emp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 sgpio_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* get the slot number from the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (pmp < EM_MAX_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) emp = &pp->em_priv[pmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spin_lock_irqsave(&sgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ecx_parse_sgpio(pdata, ap->port_no, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sgpio_out = pdata->sgpio_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (i = 0; i < pdata->pre_clocks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ecx_led_cycle_clock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ecx_led_cycle_clock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * bit-bang out the SGPIO pattern, by consuming a bit and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * clocking it out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) gpiod_set_value(pdata->sgpio_gpiod[SDATA], sgpio_out & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sgpio_out >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ecx_led_cycle_clock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (i = 0; i < pdata->post_clocks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ecx_led_cycle_clock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* save off new led state for port/slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) emp->led_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_unlock_irqrestore(&sgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void highbank_set_em_messages(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ahci_host_priv *hpriv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct ata_port_info *pi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct ecx_plat_data *pdata = hpriv->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 0; i < SGPIO_PINS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) gpiod = devm_gpiod_get_index(dev, "calxeda,sgpio", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(dev, "failed to get GPIO %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) gpiod_set_consumer_name(gpiod, "CX SGPIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pdata->sgpio_gpiod[i] = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) of_property_read_u32_array(np, "calxeda,led-order",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pdata->port_to_sgpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pdata->n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pdata->pre_clocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (of_property_read_u32(np, "calxeda,post-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &pdata->post_clocks))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pdata->post_clocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* store em_loc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hpriv->em_loc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hpriv->em_buf_sz = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) hpriv->em_msg_type = EM_MSG_TYPE_LED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 dev = port_data[sata_port].phy_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_lock(&cphy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_unlock(&cphy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 dev = port_data[sata_port].phy_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_lock(&cphy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) spin_unlock(&cphy_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void combo_phy_wait_for_ready(u8 sata_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static u32 combo_phy_read(u8 sata_port, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) combo_phy_wait_for_ready(sata_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) combo_phy_wait_for_ready(sata_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) combo_phy_wait_for_ready(sata_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void highbank_cphy_disable_overrides(u8 sata_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 lane = port_data[sata_port].lane_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (unlikely(port_data[sata_port].phy_base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tmp &= ~CPHY_SATA_RX_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 lane = port_data[sata_port].lane_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (val & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tmp &= ~CPHY_SATA_TX_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tmp |= CPHY_SATA_TX_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void cphy_override_rx_mode(u8 sata_port, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 lane = port_data[sata_port].lane_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tmp &= ~CPHY_SATA_RX_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tmp |= CPHY_SATA_RX_OVERRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tmp &= ~CPHY_SATA_DPLL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tmp |= val << CPHY_SATA_DPLL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) tmp |= CPHY_SATA_DPLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tmp &= ~CPHY_SATA_DPLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) msleep(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void highbank_cphy_override_lane(u8 sata_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 lane = port_data[sata_port].lane_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 tmp, k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (unlikely(port_data[sata_port].phy_base == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) lane * SPHY_LANE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cphy_override_rx_mode(sata_port, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct device_node *sata_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int phy_count = 0, phy, port = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void __iomem *cphy_base[CPHY_PHY_COUNT] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct device_node *phy_nodes[CPHY_PHY_COUNT] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 tx_atten[CPHY_PORT_COUNT] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct of_phandle_args phy_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (of_parse_phandle_with_args(sata_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "calxeda,port-phys", "#phy-cells",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) port, &phy_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) for (phy = 0; phy < phy_count; phy++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (phy_nodes[phy] == phy_data.np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (phy_nodes[phy] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) phy_nodes[phy] = phy_data.np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (cphy_base[phy] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) phy_count += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) port_data[port].lane_mapping = phy_data.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) port_data[port].phy_devs = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) port_data[port].phy_base = cphy_base[phy];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) of_node_put(phy_data.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) port += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } while (port < CPHY_PORT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) of_property_read_u32_array(sata_node, "calxeda,tx-atten",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) tx_atten, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (i = 0; i < port; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) port_data[i].tx_atten = (u8) tx_atten[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * The Calxeda SATA phy intermittently fails to bring up a link with Gen3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Retrying the phy hard reset can work around the issue, but the drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * may fail again. In less than 150 out of 15000 test runs, it took more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * than 10 tries for the link to be established (but never more than 35).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Triple the maximum observed retry count to provide plenty of margin for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * rare events and to guarantee that the link is established.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Also, the default 2 second time-out on a failed drive is too long in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * this situation. The uboot implementation of the same driver function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * uses a much shorter time-out period and never experiences a time out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * issue. Reducing the time-out to 500ms improves the responsiveness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * The other timing constants were kept the same as the stock AHCI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * This change was also tested 15000 times on 24 drives and none of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * experienced a time out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const unsigned long timing[] = { 5, 100, 500};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct ahci_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ahci_host_priv *hpriv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 sstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int retry = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hpriv->stop_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* clear D2H reception area to properly wait for D2H FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tf.command = ATA_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ata_tf_to_fis(&tf, 0, 0, d2h_fis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) highbank_cphy_disable_overrides(link->ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) highbank_cphy_override_lane(link->ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* If the status is 1, we are connected, but the link did not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * come up. So retry resetting the link again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (sata_scr_read(link, SCR_STATUS, &sstatus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!(sstatus & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } while (!online && retry--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) hpriv->start_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (online)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *class = ahci_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct ata_port_operations ahci_highbank_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .inherits = &ahci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .hardreset = ahci_highbank_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .transmit_led_message = ecx_transmit_led_message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct ata_port_info ahci_highbank_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .flags = AHCI_FLAG_COMMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .port_ops = &ahci_highbank_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct scsi_host_template ahci_highbank_platform_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) AHCI_SHT("sata_highbank"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct of_device_id ahci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .compatible = "calxeda,hb-ahci" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_DEVICE_TABLE(of, ahci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int ahci_highbank_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct ahci_host_priv *hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct ecx_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 n_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct ata_port_info pi = ahci_highbank_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const struct ata_port_info *ppi[] = { &pi, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(dev, "no mmio space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(dev, "no irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!hpriv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(dev, "can't alloc ahci_host_priv\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_err(dev, "can't alloc ecx_plat_data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hpriv->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) hpriv->flags |= (unsigned long)pi.private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!hpriv->mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(dev, "can't map %pR\n", mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) rc = highbank_initialize_phys(dev, hpriv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ahci_save_initial_config(dev, hpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* prepare host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (hpriv->cap & HOST_CAP_NCQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pi.flags |= ATA_FLAG_NCQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (hpriv->cap & HOST_CAP_PMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pi.flags |= ATA_FLAG_PMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (hpriv->cap & HOST_CAP_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* CAP.NP sometimes indicate the index of the last enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * port, at other times, that of the last possible port, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * determining the maximum port number requires looking at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * both CAP.NP and port_map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pdata->n_ports = n_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) hpriv->plat_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) highbank_set_em_messages(dev, hpriv, &pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) host = ata_host_alloc_pinfo(dev, ppi, n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) host->private_data = hpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) host->flags |= ATA_HOST_PARALLEL_SCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ata_port_desc(ap, "mmio %pR", mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* set enclosure management message type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ap->flags & ATA_FLAG_EM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ap->em_message_type = hpriv->em_msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* disabled/not-implemented port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!(hpriv->port_map & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ap->ops = &ata_dummy_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) rc = ahci_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ahci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ahci_print_info(host, "platform");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rc = ahci_host_activate(host, &ahci_highbank_platform_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int ahci_highbank_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct ahci_host_priv *hpriv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) void __iomem *mmio = hpriv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(dev, "firmware update required for suspend/resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * AHCI spec rev1.1 section 8.3.3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Software must disable interrupts prior to requesting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * transition of the HBA to D3 state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ctl = readl(mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ctl &= ~HOST_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) writel(ctl, mmio + HOST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) readl(mmio + HOST_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ata_host_suspend(host, PMSG_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int ahci_highbank_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) rc = ahci_reset_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ahci_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ahci_highbank_suspend, ahci_highbank_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct platform_driver ahci_highbank_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .remove = ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = "highbank-ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .of_match_table = ahci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .pm = &ahci_highbank_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .probe = ahci_highbank_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) module_platform_driver(ahci_highbank_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_ALIAS("sata:highbank");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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