^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "sata_gemini.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "gemini_sata_bridge"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * struct sata_gemini - a state container for a Gemini SATA bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @dev: the containing device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @base: remapped I/O memory base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @muxmode: the current muxing mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @ide_pins: if the device is using the plain IDE interface pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @sata_bridge: if the device enables the SATA bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @sata0_reset: SATA0 reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @sata1_reset: SATA1 reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @sata0_pclk: SATA0 PCLK handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @sata1_pclk: SATA1 PCLK handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct sata_gemini {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum gemini_muxmode muxmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool ide_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool sata_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct reset_control *sata0_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct reset_control *sata1_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk *sata0_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *sata1_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Miscellaneous Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GEMINI_GLOBAL_MISC_CTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Values of IDE IOMUX bits in the misc control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Bits 26:24 are "IDE IO Select", which decides what SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * adapters are connected to which of the two IDE/ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * controllers in the Gemini. We can connect the two IDE blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * to one SATA adapter each, both acting as master, or one IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * blocks to two SATA adapters so the IDE block can act in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * master/slave configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * We also bring out different blocks on the actual IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * pins (not SATA pins) if (and only if) these are muxed in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 111-100 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Mode 0: 000 - ata0 master <-> sata0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * ata1 master <-> sata1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * ata0 slave interface brought out on IDE pads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Mode 1: 001 - ata0 master <-> sata0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * ata1 master <-> sata1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * ata1 slave interface brought out on IDE pads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Mode 2: 010 - ata1 master <-> sata1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * ata1 slave <-> sata0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ata0 master and slave interfaces brought out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * on IDE pads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Mode 3: 011 - ata0 master <-> sata0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * ata1 slave <-> sata1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * ata1 master and slave interfaces brought out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * on IDE pads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GEMINI_IDE_IOMUX_MASK (7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GEMINI_IDE_IOMUX_MODE0 (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GEMINI_IDE_IOMUX_MODE1 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GEMINI_IDE_IOMUX_MODE2 (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GEMINI_IDE_IOMUX_MODE3 (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GEMINI_IDE_IOMUX_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Registers directly controlling the PATA<->SATA adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GEMINI_SATA_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GEMINI_SATA_PHY_ID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GEMINI_SATA0_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GEMINI_SATA1_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GEMINI_SATA0_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GEMINI_SATA1_CTRL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GEMINI_SATA_STATUS_BIST_DONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GEMINI_SATA_STATUS_BIST_OK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GEMINI_SATA_STATUS_PHY_READY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GEMINI_SATA_CTRL_PHY_BIST_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GEMINI_SATA_CTRL_PHY_FORCE_IDLE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GEMINI_SATA_CTRL_PHY_FORCE_READY BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GEMINI_SATA_CTRL_ATAPI_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GEMINI_SATA_CTRL_BUS_WITH_20 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GEMINI_SATA_CTRL_SLAVE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GEMINI_SATA_CTRL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * There is only ever one instance of this bridge on a system,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * so create a singleton so that the FTIDE010 instances can grab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * a reference to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct sata_gemini *sg_singleton;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct sata_gemini *gemini_sata_bridge_get(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (sg_singleton)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return sg_singleton;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXPORT_SYMBOL(gemini_sata_bridge_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!sg->sata_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * In muxmode 2 and 3 one of the ATA controllers is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * actually not connected to any SATA bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if ((sg->muxmode == GEMINI_MUXMODE_2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) !is_ata1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if ((sg->muxmode == GEMINI_MUXMODE_3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) is_ata1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL(gemini_sata_bridge_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return sg->muxmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXPORT_SYMBOL(gemini_sata_get_muxmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int gemini_sata_setup_bridge(struct sata_gemini *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long timeout = jiffies + (HZ * 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool bridge_online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (bridge == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* SATA0 slave mode is only used in muxmode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (sg->muxmode == GEMINI_MUXMODE_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val |= GEMINI_SATA_CTRL_SLAVE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writel(val, sg->base + GEMINI_SATA0_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* SATA1 slave mode is only used in muxmode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (sg->muxmode == GEMINI_MUXMODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= GEMINI_SATA_CTRL_SLAVE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(val, sg->base + GEMINI_SATA1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Vendor code waits 10 ms here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Wait for PHY to become ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (bridge == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val = readl(sg->base + GEMINI_SATA0_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val = readl(sg->base + GEMINI_SATA1_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (val & GEMINI_SATA_STATUS_PHY_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } while (time_before(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bridge_online = !!(val & GEMINI_SATA_STATUS_PHY_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_info(sg->dev, "SATA%d PHY %s\n", bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) bridge_online ? "ready" : "not ready");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return bridge_online ? 0: -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (bridge == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pclk = sg->sata0_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pclk = sg->sata1_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk_enable(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Do not keep clocking a bridge that is not online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = gemini_sata_setup_bridge(sg, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_disable(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EXPORT_SYMBOL(gemini_sata_start_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (bridge == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clk_disable(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else if (bridge == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clk_disable(sg->sata1_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) EXPORT_SYMBOL(gemini_sata_stop_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int gemini_sata_reset_bridge(struct sata_gemini *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (bridge == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) reset_control_reset(sg->sata0_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) reset_control_reset(sg->sata1_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return gemini_sata_setup_bridge(sg, bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) EXPORT_SYMBOL(gemini_sata_reset_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int gemini_sata_bridge_init(struct sata_gemini *sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct device *dev = sg->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 sata_id, sata_phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(sg->sata0_pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dev, "no SATA0 PCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (IS_ERR(sg->sata1_pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(dev, "no SATA1 PCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = clk_prepare_enable(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pr_err("failed to enable SATA0 PCLK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = clk_prepare_enable(sg->sata1_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pr_err("failed to enable SATA1 PCLK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk_disable_unprepare(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (IS_ERR(sg->sata0_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(dev, "no SATA0 reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk_disable_unprepare(sg->sata1_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clk_disable_unprepare(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return PTR_ERR(sg->sata0_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (IS_ERR(sg->sata1_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(dev, "no SATA1 reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clk_disable_unprepare(sg->sata1_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clk_disable_unprepare(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return PTR_ERR(sg->sata1_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) sata_id = readl(sg->base + GEMINI_SATA_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sg->sata_bridge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk_disable(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk_disable(sg->sata1_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_info(dev, "SATA ID %08x, PHY ID: %08x\n", sata_id, sata_phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int gemini_setup_ide_pins(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct pinctrl *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct pinctrl_state *ide_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) p = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (IS_ERR(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return PTR_ERR(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ide_state = pinctrl_lookup_state(p, "ide");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (IS_ERR(ide_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return PTR_ERR(ide_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = pinctrl_select_state(p, ide_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(dev, "could not select IDE state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int gemini_sata_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct sata_gemini *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) enum gemini_muxmode muxmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 gmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 gmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sg->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (IS_ERR(sg->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return PTR_ERR(sg->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) map = syscon_regmap_lookup_by_phandle(np, "syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(dev, "no global syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Set up the SATA bridge if need be */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (of_property_read_bool(np, "cortina,gemini-enable-sata-bridge")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = gemini_sata_bridge_init(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (of_property_read_bool(np, "cortina,gemini-enable-ide-pins"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sg->ide_pins = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!sg->sata_bridge && !sg->ide_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(dev, "neither SATA bridge or IDE output enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) goto out_unprep_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = of_property_read_u32(np, "cortina,gemini-ata-muxmode", &muxmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(dev, "could not parse ATA muxmode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto out_unprep_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (muxmode > GEMINI_MUXMODE_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(dev, "illegal muxmode %d\n", muxmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto out_unprep_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sg->muxmode = muxmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) gmask = GEMINI_IDE_IOMUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) gmode = (muxmode << GEMINI_IDE_IOMUX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, gmask, gmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(dev, "unable to set up IDE muxing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) goto out_unprep_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Route out the IDE pins if desired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * This is done by looking up a special pin control state called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * "ide" that will route out the IDE pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (sg->ide_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = gemini_setup_ide_pins(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_info(dev, "set up the Gemini IDE/SATA nexus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) platform_set_drvdata(pdev, sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sg_singleton = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) out_unprep_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (sg->sata_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk_unprepare(sg->sata1_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) clk_unprepare(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int gemini_sata_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct sata_gemini *sg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (sg->sata_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk_unprepare(sg->sata1_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) clk_unprepare(sg->sata0_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) sg_singleton = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct of_device_id gemini_sata_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .compatible = "cortina,gemini-sata-bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct platform_driver gemini_sata_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .of_match_table = of_match_ptr(gemini_sata_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .probe = gemini_sata_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .remove = gemini_sata_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) module_platform_driver(gemini_sata_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags