^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/ata/sata_fsl.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Freescale 3.0Gbps SATA device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Ashish Kalra <ashish.kalra@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Li Yang <leoli@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static unsigned int intr_coalescing_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) module_param(intr_coalescing_count, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_PARM_DESC(intr_coalescing_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "INT coalescing count threshold (1..31)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned int intr_coalescing_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(intr_coalescing_ticks, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(intr_coalescing_ticks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "INT coalescing timer threshold in AHB ticks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Controller information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SATA_FSL_QUEUE_DEPTH = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SATA_FSL_MAX_PRD = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ATA_FLAG_PMP | ATA_FLAG_NCQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * chained indirect PRDEs up to a max count of 63.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * be setup as an indirect descriptor, pointing to it's next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * (contiguous) PRDE. Though chained indirect PRDE arrays are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * supported,it will be more efficient to use a direct PRDT and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * a single chain/link to indirect PRDE array/PRDT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SATA_FSL_CMD_DESC_CFIS_SZ = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SATA_FSL_CMD_DESC_SFIS_SZ = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SATA_FSL_CMD_DESC_ACMD_SZ = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SATA_FSL_CMD_DESC_RSRVD = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SATA_FSL_CMD_DESC_SFIS_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SATA_FSL_CMD_DESC_ACMD_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SATA_FSL_CMD_DESC_RSRVD +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SATA_FSL_MAX_PRD * 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (SATA_FSL_CMD_DESC_CFIS_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SATA_FSL_CMD_DESC_SFIS_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SATA_FSL_CMD_DESC_ACMD_SZ +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SATA_FSL_CMD_DESC_RSRVD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SATA_FSL_CMD_DESC_AR_SZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * MPC8315 has two SATA controllers, SATA1 & SATA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * (one port per controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * MPC837x has 2/4 controllers, one port per controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SATA_FSL_MAX_PORTS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SATA_FSL_IRQ_FLAG = IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Interrupt Coalescing Control Register bitdefs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ICC_MIN_INT_COUNT_THRESHOLD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ICC_MIN_INT_TICKS_THRESHOLD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ICC_SAFE_INT_TICKS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Host Controller command register set - per port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CQ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CA = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CC = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CE = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DE = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CHBA = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) HSTATUS = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) HCONTROL = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CQPMP = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SIGNATURE = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ICC = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Host Status Register (HStatus) bitdefs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ONLINE = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GOING_OFFLINE = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BIST_ERR = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CLEAR_ERROR = (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FATAL_ERR_HC_MASTER_ERR = (1 << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FATAL_ERR_PARITY_ERR_TX = (1 << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FATAL_ERR_PARITY_ERR_RX = (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FATAL_ERR_DATA_UNDERRUN = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FATAL_ERR_DATA_OVERRUN = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FATAL_ERR_CRC_ERR_TX = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FATAL_ERR_CRC_ERR_RX = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) FATAL_ERR_PARITY_ERR_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FATAL_ERR_PARITY_ERR_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FATAL_ERR_DATA_UNDERRUN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FATAL_ERR_DATA_OVERRUN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FATAL_ERR_CRC_ERR_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FATAL_ERR_CRC_ERR_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) INT_ON_FATAL_ERR = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) INT_ON_PHYRDY_CHG = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) INT_ON_SIGNATURE_UPDATE = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) INT_ON_SNOTIFY_UPDATE = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) INT_ON_SINGL_DEVICE_ERR = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) INT_ON_CMD_COMPLETE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Host Control Register (HControl) bitdefs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) HCONTROL_ONLINE_PHY_RST = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) HCONTROL_FORCE_OFFLINE = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) HCONTROL_LEGACY = (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) HCONTROL_PARITY_PROT_MOD = (1 << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) HCONTROL_DPATH_PARITY = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) HCONTROL_SNOOP_ENABLE = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) HCONTROL_PMP_ATTACHED = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) HCONTROL_COPYOUT_STATFIS = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IE_ON_FATAL_ERR = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IE_ON_PHYRDY_CHG = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IE_ON_SIGNATURE_UPDATE = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IE_ON_SNOTIFY_UPDATE = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IE_ON_SINGL_DEVICE_ERR = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IE_ON_CMD_COMPLETE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DATA_SNOOP_ENABLE_V1 = (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DATA_SNOOP_ENABLE_V2 = (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * SATA Superset Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SSTATUS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SERROR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SCONTROL = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SNOTIFY = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Control Status Register Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) TRANSCFG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TRANSSTATUS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) LINKCFG = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) LINKCFG1 = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) LINKCFG2 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) LINKSTATUS = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) LINKSTATUS1 = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PHYCTRLCFG = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) COMMANDSTAT = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* TRANSCFG (transport-layer) configuration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TRANSCFG_RX_WATER_MARK = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* PHY (link-layer) configuration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PHY_BIST_ENABLE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Command Header Table entry, i.e, command slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 4 Dwords per command slot, command header size == 64 Dwords.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct cmdhdr_tbl_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 cda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 prde_fis_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 ttl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 desc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Description information bitdefs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CMD_DESC_RES = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) VENDOR_SPECIFIC_BIST = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CMD_DESC_SNOOP_ENABLE = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FPDMA_QUEUED_CMD = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SRST_CMD = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) BIST = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ATAPI_CMD = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Command Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct command_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 cfis[8 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 sfis[8 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 acmd[4 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 fill[4 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Physical region table descriptor(PRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct prde {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 dba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 fill[2 * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 ddc_and_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * ata_port private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * This is our per-port instance data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct sata_fsl_port_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct cmdhdr_tbl_entry *cmdslot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dma_addr_t cmdslot_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct command_desc *cmdentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dma_addr_t cmdentry_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * ata_port->host_set private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct sata_fsl_host_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) void __iomem *hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) void __iomem *ssr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __iomem *csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int data_snoop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device_attribute intr_coalescing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct device_attribute rx_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void fsl_sata_set_irq_coalescing(struct ata_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int count, unsigned int ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (count > ICC_MAX_INT_COUNT_THRESHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) count = ICC_MAX_INT_COUNT_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) count = ICC_MIN_INT_COUNT_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ticks = ICC_MAX_INT_TICKS_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (count > ICC_MIN_INT_COUNT_THRESHOLD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ticks = ICC_SAFE_INT_TICKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) iowrite32((count << 24 | ticks), hcr_base + ICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) intr_coalescing_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) intr_coalescing_ticks = ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) intr_coalescing_count, intr_coalescing_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) hcr_base, ioread32(hcr_base + ICC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return sprintf(buf, "%d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) intr_coalescing_count, intr_coalescing_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int coalescing_count, coalescing_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (sscanf(buf, "%d%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) &coalescing_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &coalescing_ticks) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) coalescing_count, coalescing_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return strlen(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int rx_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) void __iomem *csr_base = host_priv->csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) rx_watermark = ioread32(csr_base + TRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) rx_watermark &= 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return sprintf(buf, "%d\n", rx_watermark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int rx_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void __iomem *csr_base = host_priv->csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (sscanf(buf, "%d", &rx_watermark) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) temp = ioread32(csr_base + TRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) temp &= 0xffffffe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return strlen(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static inline unsigned int sata_fsl_tag(unsigned int tag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) void __iomem *hcr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* We let libATA core do actual (queue) tag allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DPRINTK("tag %d invalid : out of range\n", tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DPRINTK("tag %d invalid : in use!!\n", tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int tag, u32 desc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 data_xfer_len, u8 num_prde,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 fis_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dma_addr_t cmd_descriptor_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cmd_descriptor_address = pp->cmdentry_paddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tag * SATA_FSL_CMD_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* NOTE: both data_xfer_len & fis_len are Dword counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pp->cmdslot[tag].prde_fis_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cpu_to_le32((num_prde << 16) | (fis_len << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pp->cmdslot[tag].cda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pp->cmdslot[tag].prde_fis_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 *ttl, dma_addr_t cmd_desc_paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int data_snoop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int num_prde = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 ttl_dwords = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * NOTE : direct & indirect prdt's are contiguously allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct prde *prd = (struct prde *)&((struct command_desc *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cmd_desc)->prdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct prde *prd_ptr_to_indirect_ext = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned indirect_ext_segment_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dma_addr_t indirect_ext_segment_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) indirect_ext_segment_paddr = cmd_desc_paddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dma_addr_t sg_addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 sg_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) (unsigned long long)sg_addr, sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* warn if each s/g element is not dword aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (unlikely(sg_addr & 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) (unsigned long long)sg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (unlikely(sg_len & 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sg_next(sg) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) VPRINTK("setting indirect prde\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) prd_ptr_to_indirect_ext = prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) indirect_ext_segment_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ++prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ++num_prde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ttl_dwords += sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) prd->dba = cpu_to_le32(sg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ttl_dwords, prd->dba, prd->ddc_and_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ++num_prde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ++prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (prd_ptr_to_indirect_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) indirect_ext_segment_sz += sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (prd_ptr_to_indirect_ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* set indirect extension flag along with indirect ext. size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) prd_ptr_to_indirect_ext->ddc_and_ext =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) data_snoop |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) (indirect_ext_segment_sz & ~0x03)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *ttl = ttl_dwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return num_prde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct sata_fsl_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct command_desc *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 num_prde = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 ttl_dwords = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dma_addr_t cd_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cd = (struct command_desc *)pp->cmdentry + tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) cd->cfis[0], cd->cfis[1], cd->cfis[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (qc->tf.protocol == ATA_PROT_NCQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cd->cfis[3], cd->cfis[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ata_is_atapi(qc->tf.protocol)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) desc_info |= ATAPI_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) memset((void *)&cd->acmd, 0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (qc->flags & ATA_QCFLAG_DMAMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) num_prde = sata_fsl_fill_sg(qc, (void *)cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &ttl_dwords, cd_paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) host_priv->data_snoop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (qc->tf.protocol == ATA_PROT_NCQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) desc_info |= FPDMA_QUEUED_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) num_prde, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) desc_info, ttl_dwords, num_prde);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ioread32(CQ + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ioread32(CA + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ioread32(CE + hcr_base), ioread32(CC + hcr_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Simply queue command to the controller/device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) iowrite32(1 << tag, CQ + hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ioread32(CE + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ioread32(DE + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ioread32(CC + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ioread32(COMMANDSTAT + host_priv->csr_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct sata_fsl_port_priv *pp = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct command_desc *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) cd = pp->cmdentry + tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ata_tf_from_fis(cd->sfis, &qc->result_tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int sata_fsl_scr_write(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unsigned int sc_reg_in, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void __iomem *ssr_base = host_priv->ssr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int sc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) switch (sc_reg_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case SCR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case SCR_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case SCR_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case SCR_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) sc_reg = sc_reg_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) iowrite32(val, ssr_base + (sc_reg * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int sata_fsl_scr_read(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned int sc_reg_in, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) void __iomem *ssr_base = host_priv->ssr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned int sc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) switch (sc_reg_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case SCR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) case SCR_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case SCR_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case SCR_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sc_reg = sc_reg_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *val = ioread32(ssr_base + (sc_reg * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static void sata_fsl_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ioread32(CQ + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ioread32(CA + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ioread32(CE + hcr_base), ioread32(DE + hcr_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) VPRINTK("CmdStat = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ioread32(host_priv->csr_base + COMMANDSTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* disable interrupts on the controller/port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void sata_fsl_thaw(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* ack. any pending IRQs for this controller/port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) temp = ioread32(hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (temp & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) iowrite32((temp & 0x3F), hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* enable interrupts on the controller/port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void sata_fsl_pmp_attach(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static void sata_fsl_pmp_detach(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) temp &= ~HCONTROL_PMP_ATTACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) iowrite32(temp, hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* enable interrupts on the controller/port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int sata_fsl_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct sata_fsl_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) void *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dma_addr_t mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pp = kzalloc(sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (!pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) kfree(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pp->cmdslot = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pp->cmdslot_paddr = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mem += SATA_FSL_CMD_SLOT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mem_dma += SATA_FSL_CMD_SLOT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pp->cmdentry = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pp->cmdentry_paddr = mem_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ap->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pp->cmdslot_paddr, pp->cmdentry_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Now, update the CHBA register in host controller cmd register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Now, we can bring the controller on-line & also initiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * the COMINIT sequence, we simply return here and the boot-probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * & device discovery process is re-initiated by libATA using a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Softreset EH (dummy) session. Hence, boot probing and device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * discovey will be part of sata_fsl_softreset() callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void sata_fsl_port_stop(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct sata_fsl_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Force host controller to go off-line, aborting current operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) temp &= ~HCONTROL_ONLINE_PHY_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) temp |= HCONTROL_FORCE_OFFLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) iowrite32(temp, hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Poll for controller to go offline - should happen immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ap->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) pp->cmdslot, pp->cmdslot_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) kfree(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) temp = ioread32(hcr_base + SIGNATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) VPRINTK("raw sig = 0x%x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) tf.lbah = (temp >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) tf.lbam = (temp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) tf.lbal = (temp >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) tf.nsect = temp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ata_dev_classify(&tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned long start_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) DPRINTK("in xx_hardreset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) try_offline_again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * Force host controller to go off-line, aborting current operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) temp &= ~HCONTROL_ONLINE_PHY_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) iowrite32(temp, hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Poll for controller to go offline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (temp & ONLINE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Try to offline controller atleast twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (i == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) goto try_offline_again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) DPRINTK("hardreset, controller off-lined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * PHY reset should remain asserted for atleast 1ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ata_msleep(ap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) sata_set_spd(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * Now, bring the host controller online again, this can take time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * as PHY reset and communication establishment, 1st D2H FIS and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * device signature update is done, on safe side assume 500ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * NOTE : Host online status may be indicated immediately!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) temp |= HCONTROL_PMP_ATTACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) iowrite32(temp, hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!(temp & ONLINE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ata_port_err(ap, "Hardreset failed, not on-lined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) DPRINTK("hardreset, controller off-lined & on-lined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * First, wait for the PHYRDY change to occur before waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * the signature, and also verify if SStatus indicates device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if ((!(temp & 0x10)) || ata_link_offline(link)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) *class = ATA_DEV_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * Wait for the first D2H from device,i.e,signature update notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) start_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) 500, jiffies_to_msecs(deadline - start_jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if ((temp & 0xFF) != 0x18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ata_port_warn(ap, "No Signature Update\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) *class = ATA_DEV_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) goto do_followup_srst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ata_port_info(ap, "Signature Update detected @ %d msecs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) jiffies_to_msecs(jiffies - start_jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *class = sata_fsl_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) do_followup_srst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * request libATA to perform follow-up softreset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct sata_fsl_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int pmp = sata_srst_pmp(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct ata_taskfile tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u8 *cfis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 Serror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DPRINTK("in xx_softreset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ata_link_offline(link)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) DPRINTK("PHY reports no device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) *class = ATA_DEV_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * Send a device reset (SRST) explicitly on command slot #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Check : will the command queue (reg) be cleared during offlining ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * Also we will be online only if Phy commn. has been established
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * and device presence has been detected, therefore if we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * reached here, we can send a command to the target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) DPRINTK("Sending SRST/device reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ata_tf_init(link->device, &tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) cfis = (u8 *) &pp->cmdentry->cfis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* device reset/SRST is a control register update FIS, uses tag0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) sata_fsl_setup_cmd_hdr_entry(pp, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ata_tf_to_fis(&tf, pmp, 0, cfis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) cfis[0], cfis[1], cfis[2], cfis[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * Queue SRST command to the controller/device, ensure that no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * other commands are active on the controller/device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ioread32(CQ + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ioread32(CA + hcr_base), ioread32(CC + hcr_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) iowrite32(0xFFFF, CC + hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (pmp != SATA_PMP_CTRL_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) iowrite32(pmp, CQPMP + hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) iowrite32(1, CQ + hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (temp & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ata_port_warn(ap, "ATA_SRST issue failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ioread32(CQ + hcr_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ioread32(CA + hcr_base), ioread32(CC + hcr_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) DPRINTK("Serror = 0x%x\n", Serror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ata_msleep(ap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * SATA device enters reset state after receiving a Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * FIS with SRST bit asserted and it awaits another H2D Control reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * FIS with SRST bit cleared, then the device does internal diags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * initialization, followed by indicating it's initialization status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * using ATA signature D2H register FIS to the host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) 0, 0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ata_tf_to_fis(&tf, pmp, 0, cfis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (pmp != SATA_PMP_CTRL_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) iowrite32(pmp, CQPMP + hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) iowrite32(1, CQ + hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ata_msleep(ap, 150); /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * The above command would have signalled an interrupt on command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * complete, which needs special handling, by clearing the Nth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * command bit of the CCreg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) DPRINTK("SATA FSL : Now checking device signature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) *class = ATA_DEV_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Verify if SStatus indicates device presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ata_link_online(link)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * if we are here, device presence has been detected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * 1st D2H FIS would have been received, but sfis in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * command desc. is not updated, but signature register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * would have been updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) *class = sata_fsl_dev_classify(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) DPRINTK("class = %d\n", *class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static void sata_fsl_error_handler(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) DPRINTK("in xx_error_handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) sata_pmp_error_handler(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (qc->flags & ATA_QCFLAG_FAILED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) qc->err_mask |= AC_ERR_OTHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (qc->err_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* make DMA engine forget about the failed command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static void sata_fsl_error_intr(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) u32 hstatus, dereg=0, cereg = 0, SError = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) unsigned int err_mask = 0, action = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int freeze = 0, abort=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct ata_link *link = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct ata_queued_cmd *qc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct ata_eh_info *ehi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) hstatus = ioread32(hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) cereg = ioread32(hcr_base + CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* first, analyze and record host port events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) link = &ap->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ehi = &link->eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ata_ehi_clear_desc(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * Handle & Clear SError
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (unlikely(SError & 0xFFFF0000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) hstatus, cereg, ioread32(hcr_base + DE), SError);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* handle fatal errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (hstatus & FATAL_ERROR_DECODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ehi->err_mask |= AC_ERR_ATA_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ehi->action |= ATA_EH_SOFTRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Handle SDB FIS receive & notify update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (hstatus & INT_ON_SNOTIFY_UPDATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) sata_async_notification(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Handle PHYRDY change notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (hstatus & INT_ON_PHYRDY_CHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) DPRINTK("SATA FSL: PHYRDY change indication\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Setup a soft-reset EH action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ata_ehi_hotplugged(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* handle single device errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (cereg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * clear the command error, also clears queue to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * in error, and we can (re)issue commands to this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * When a device is in error all commands queued into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * host controller and at the device are considered aborted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * and the queue for that device is stopped. Now, after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * clearing the device error, we can issue commands to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * device to interrogate it to find the source of the error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ioread32(hcr_base + CE), ioread32(hcr_base + DE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* find out the offending link and qc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (ap->nr_pmp_links) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) unsigned int dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dereg = ioread32(hcr_base + DE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) iowrite32(dereg, hcr_base + DE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) iowrite32(cereg, hcr_base + CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_num = ffs(dereg) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (dev_num < ap->nr_pmp_links && dereg != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) link = &ap->pmp_link[dev_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ehi = &link->eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) qc = ata_qc_from_tag(ap, link->active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * We should consider this as non fatal error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * and TF must be updated as done below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) err_mask |= AC_ERR_HSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) action |= ATA_EH_HARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) freeze = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dereg = ioread32(hcr_base + DE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) iowrite32(dereg, hcr_base + DE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) iowrite32(cereg, hcr_base + CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) qc = ata_qc_from_tag(ap, link->active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * We should consider this as non fatal error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * and TF must be updated as done below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* record error info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) qc->err_mask |= err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ehi->err_mask |= err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ehi->action |= action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* freeze or abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (freeze)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) else if (abort) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ata_link_abort(qc->dev->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ata_port_abort(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static void sata_fsl_host_intr(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct sata_fsl_host_priv *host_priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) u32 hstatus, done_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u32 SError;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) u32 status_mask = INT_ON_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) hstatus = ioread32(hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Read command completed register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) done_mask = ioread32(hcr_base + CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* Workaround for data length mismatch errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ata_qc_for_each_with_internal(ap, qc, tag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (qc && ata_is_atapi(qc->tf.protocol)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) u32 hcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Set HControl[27] to clear error registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) hcontrol = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) iowrite32(hcontrol | CLEAR_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Clear HControl[27] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) iowrite32(hcontrol & ~CLEAR_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* Clear SError[E] bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) sata_fsl_scr_write(&ap->link, SCR_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) SError);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* Ignore fatal error and device error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) | INT_ON_FATAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (unlikely(SError & 0xFFFF0000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) DPRINTK("serror @host_intr : 0x%x\n", SError);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) sata_fsl_error_intr(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (unlikely(hstatus & status_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) DPRINTK("error interrupt!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) sata_fsl_error_intr(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) VPRINTK("Status of all queues :\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) done_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ioread32(hcr_base + CA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ioread32(hcr_base + CE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ioread32(hcr_base + CQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ap->qc_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (done_mask & ap->qc_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* clear CC bit, this will also complete the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) iowrite32(done_mask, hcr_base + CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) DPRINTK("Status of all queues :\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) done_mask, ioread32(hcr_base + CA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ioread32(hcr_base + CE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (done_mask & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) DPRINTK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) i, ioread32(hcr_base + CC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ioread32(hcr_base + CA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) iowrite32(1, hcr_base + CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) DPRINTK("completing non-ncq cmd, CC=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ioread32(hcr_base + CC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (qc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ata_qc_complete(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Spurious Interrupt!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) DPRINTK("spurious interrupt!!, CC = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ioread32(hcr_base + CC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) iowrite32(done_mask, hcr_base + CC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u32 interrupt_enables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) unsigned handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* ack. any pending IRQs for this controller/port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) interrupt_enables = ioread32(hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) interrupt_enables &= 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) DPRINTK("interrupt status 0x%x\n", interrupt_enables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!interrupt_enables)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Assuming one port per host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (ap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sata_fsl_host_intr(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_warn(host->dev, "interrupt on disabled port 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) iowrite32(interrupt_enables, hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * Multiple ports are represented by multiple SATA controllers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * one port per controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int sata_fsl_init_controller(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * NOTE : We cannot bring the controller online before setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * the CHBA, hence main controller initialization is done as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * part of the port_start() callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* sata controller to operate in enterprise mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* ack. any pending IRQs for this controller/port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) temp = ioread32(hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (temp & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) iowrite32((temp & 0x3F), hcr_base + HSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Keep interrupts disabled on the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) temp = ioread32(hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* Disable interrupt coalescing control(icc), for the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) iowrite32(0x01000000, hcr_base + ICC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* clear error registers, SError is cleared by libATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) iowrite32(0x00000FFFF, hcr_base + CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) iowrite32(0x00000FFFF, hcr_base + DE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * reset the number of command complete bits which will cause the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * interrupt to be signaled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) intr_coalescing_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * host controller will be brought on-line, during xx_port_start()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * callback, that should also initiate the OOB, COMINIT sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static void sata_fsl_host_stop(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) iounmap(host_priv->hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) kfree(host_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * scsi mid-layer and libata interface structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static struct scsi_host_template sata_fsl_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ATA_NCQ_SHT("sata_fsl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .can_queue = SATA_FSL_QUEUE_DEPTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .dma_boundary = ATA_DMA_BOUNDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static struct ata_port_operations sata_fsl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .inherits = &sata_pmp_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .qc_defer = ata_std_qc_defer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .qc_prep = sata_fsl_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .qc_issue = sata_fsl_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .qc_fill_rtf = sata_fsl_qc_fill_rtf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .scr_read = sata_fsl_scr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .scr_write = sata_fsl_scr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .freeze = sata_fsl_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .thaw = sata_fsl_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .softreset = sata_fsl_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .hardreset = sata_fsl_hardreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .pmp_softreset = sata_fsl_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .error_handler = sata_fsl_error_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .post_internal_cmd = sata_fsl_post_internal_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .port_start = sata_fsl_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .port_stop = sata_fsl_port_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .host_stop = sata_fsl_host_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .pmp_attach = sata_fsl_pmp_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .pmp_detach = sata_fsl_pmp_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static const struct ata_port_info sata_fsl_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .flags = SATA_FSL_HOST_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .port_ops = &sata_fsl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static int sata_fsl_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) int retval = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) void __iomem *hcr_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) void __iomem *ssr_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) void __iomem *csr_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct sata_fsl_host_priv *host_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct ata_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct ata_port_info pi = sata_fsl_port_info[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) const struct ata_port_info *ppi[] = { &pi, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) hcr_base = of_iomap(ofdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (!hcr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) goto error_exit_with_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ssr_base = hcr_base + 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) csr_base = hcr_base + 0x140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) temp = ioread32(csr_base + TRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) temp = temp & 0xffffffe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (!host_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) goto error_exit_with_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) host_priv->hcr_base = hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) host_priv->ssr_base = ssr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) host_priv->csr_base = csr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) irq = platform_get_irq(ofdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) retval = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) goto error_exit_with_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) host_priv->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* allocate host structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) goto error_exit_with_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* host->iomap is not used currently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) host->private_data = host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* initialize host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) sata_fsl_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * Now, register with libATA core, this will also initiate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * device discovery process, invoking our port_start() handler &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * error_handler() to execute a dummy Softreset EH session
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) &sata_fsl_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) sysfs_attr_init(&host_priv->intr_coalescing.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) host_priv->intr_coalescing.attr.name = "intr_coalescing";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) retval = device_create_file(host->dev, &host_priv->intr_coalescing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) goto error_exit_with_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) sysfs_attr_init(&host_priv->rx_watermark.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) host_priv->rx_watermark.attr.name = "rx_watermark";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) retval = device_create_file(host->dev, &host_priv->rx_watermark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) goto error_exit_with_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) error_exit_with_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (hcr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) iounmap(hcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) kfree(host_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static int sata_fsl_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) struct ata_host *host = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct ata_host *host = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) return ata_host_suspend(host, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static int sata_fsl_resume(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) struct ata_host *host = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) struct sata_fsl_host_priv *host_priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) void __iomem *hcr_base = host_priv->hcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct ata_port *ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct sata_fsl_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ret = sata_fsl_init_controller(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dev_err(&op->dev, "Error initializing hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /* Recovery the CHBA register in host controller cmd register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) iowrite32((ioread32(hcr_base + HCONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) | HCONTROL_ONLINE_PHY_RST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) | HCONTROL_SNOOP_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) | HCONTROL_PMP_ATTACHED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) hcr_base + HCONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static const struct of_device_id fsl_sata_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .compatible = "fsl,pq-sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .compatible = "fsl,pq-sata-v2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) MODULE_DEVICE_TABLE(of, fsl_sata_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static struct platform_driver fsl_sata_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .name = "fsl-sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .of_match_table = fsl_sata_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .probe = sata_fsl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .remove = sata_fsl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .suspend = sata_fsl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .resume = sata_fsl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) module_platform_driver(fsl_sata_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) MODULE_VERSION("1.10");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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