^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pdc_adma.c - Pacific Digital Corporation ADMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maintained by: Tejun Heo <tj@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2005 Mark Lord
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Supports ATA disks in single-packet ADMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Uses PIO for everything else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TODO: Use ADMA transfers for ATAPI devices, when possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This requires careful attention to a number of quirks of the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_NAME "pdc_adma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRV_VERSION "1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* macro to calculate base address for ATA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* macro to calculate base address for ADMA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* macro to obtain addresses from ata_port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADMA_PORT_REGS(ap) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ADMA_MMIO_BAR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ADMA_PORTS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ADMA_CPB_BYTES = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ADMA_DMA_BOUNDARY = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* global register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ADMA_MODE_LOCK = 0x00c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* per-channel register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ADMA_CONTROL = 0x0000, /* ADMA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ADMA_STATUS = 0x0002, /* ADMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ADMA_CPB_COUNT = 0x0004, /* CPB count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ADMA_CPB_NEXT = 0x000c, /* next CPB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* ADMA_CONTROL register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) aNIEN = (1 << 8), /* irq mask: 1==masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) aGO = (1 << 7), /* packet trigger ("Go!") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) aRSTADM = (1 << 5), /* ADMA logic reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) aPIOMD4 = 0x0003, /* PIO mode 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* ADMA_STATUS register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) aPSD = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) aUIRQ = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) aPERR = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* CPB bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cDONE = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cATERR = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cVLD = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cDAT = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) cIEN = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* PRD bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pORD = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pDIRO = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pEND = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* ATA register flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) rIGN = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) rEND = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* ATA register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ADMA_REGS_CONTROL = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ADMA_REGS_SECTOR_COUNT = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ADMA_REGS_LBA_LOW = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ADMA_REGS_LBA_MID = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ADMA_REGS_LBA_HIGH = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ADMA_REGS_DEVICE = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ADMA_REGS_COMMAND = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PCI device IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) board_1841_idx = 0, /* ADMA 2-port controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct adma_port_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 *pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dma_addr_t pkt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) adma_state_t state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int adma_ata_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int adma_port_start(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void adma_port_stop(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void adma_freeze(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void adma_thaw(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int adma_prereset(struct ata_link *link, unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct scsi_host_template adma_ata_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ATA_BASE_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .sg_tablesize = LIBATA_MAX_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .dma_boundary = ADMA_DMA_BOUNDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct ata_port_operations adma_ata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .lost_interrupt = ATA_OP_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .check_atapi_dma = adma_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .qc_prep = adma_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .qc_issue = adma_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .freeze = adma_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .thaw = adma_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .prereset = adma_prereset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .port_start = adma_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .port_stop = adma_port_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct ata_port_info adma_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* board_1841_idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .pio_mask = ATA_PIO4_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .port_ops = &adma_ata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct pci_device_id adma_ata_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct pci_driver adma_ata_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .id_table = adma_ata_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .probe = adma_ata_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 1; /* ATAPI DMA not yet supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void adma_reset_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void __iomem *chan = ADMA_PORT_REGS(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* reset ADMA to idle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writew(aPIOMD4, chan + ADMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void adma_reinit_engine(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct adma_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __iomem *chan = ADMA_PORT_REGS(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* mask/clear ATA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ata_sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* reset the ADMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) adma_reset_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* set in-FIFO threshold to 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writew(0x100, chan + ADMA_FIFO_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* set CPB pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* set out-FIFO threshold to 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writew(0x100, chan + ADMA_FIFO_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* set CPB count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writew(1, chan + ADMA_CPB_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* read/discard ADMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) readb(chan + ADMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline void adma_enter_reg_mode(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void __iomem *chan = ADMA_PORT_REGS(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writew(aPIOMD4, chan + ADMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) readb(chan + ADMA_STATUS); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void adma_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void __iomem *chan = ADMA_PORT_REGS(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* mask/clear ATA interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ata_sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* reset ADMA to idle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void adma_thaw(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) adma_reinit_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int adma_prereset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct adma_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (pp->state != adma_state_idle) /* healthy paranoia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pp->state = adma_state_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) adma_reinit_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int adma_fill_sg(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct adma_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 *buf = pp->pkt, *last_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int i = (2 + buf[3]) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) addr = (u32)sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *(__le32 *)(buf + i) = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) len = sg_dma_len(sg) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *(__le32 *)(buf + i) = cpu_to_le32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) last_buf = &buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) buf[i++] = pFLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) buf[i++] = qc->dev->dma_mode & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) buf[i++] = 0; /* pPKLW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) buf[i++] = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *(__le32 *)(buf + i) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) i += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (unsigned long)addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (likely(last_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *last_buf |= pEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct adma_port_priv *pp = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 *buf = pp->pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 pkt_dma = (u32)pp->pkt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) adma_enter_reg_mode(qc->ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (qc->tf.protocol != ATA_PROT_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) buf[i++] = 0; /* Response flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) buf[i++] = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) buf[i++] = cVLD | cDAT | cIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) i++; /* cLEN, gets filled in below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) i += 4; /* cNCPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) i += 4; /* cPRD, gets filled in below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) buf[i++] = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) buf[i++] = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) buf[i++] = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) buf[i++] = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* ATA registers; must be a multiple of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) buf[i++] = qc->tf.device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) buf[i++] = ADMA_REGS_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) buf[i++] = qc->tf.hob_nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) buf[i++] = ADMA_REGS_SECTOR_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) buf[i++] = qc->tf.hob_lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) buf[i++] = ADMA_REGS_LBA_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) buf[i++] = qc->tf.hob_lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) buf[i++] = ADMA_REGS_LBA_MID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) buf[i++] = qc->tf.hob_lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) buf[i++] = ADMA_REGS_LBA_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) buf[i++] = qc->tf.nsect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) buf[i++] = ADMA_REGS_SECTOR_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) buf[i++] = qc->tf.lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) buf[i++] = ADMA_REGS_LBA_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) buf[i++] = qc->tf.lbam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) buf[i++] = ADMA_REGS_LBA_MID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) buf[i++] = qc->tf.lbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) buf[i++] = ADMA_REGS_LBA_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) buf[i++] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) buf[i++] = ADMA_REGS_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) buf[i++] = rIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) buf[i++] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) buf[i++] = qc->tf.command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) buf[i++] = ADMA_REGS_COMMAND | rEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) buf[3] = (i >> 3) - 2; /* cLEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) i = adma_fill_sg(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) wmb(); /* flush PRDs and pkt to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* dump out CPB + PRDs for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int j, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static char obuf[2048];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (j = 0; j < i; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) len += sprintf(obuf+len, "%02x ", buf[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if ((j & 7) == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) printk("%s\n", obuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) printk("%s\n", obuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline void adma_packet_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void __iomem *chan = ADMA_PORT_REGS(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) VPRINTK("ENTER, ap %p\n", ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* fire up the ADMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct adma_port_priv *pp = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (qc->tf.protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case ATA_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pp->state = adma_state_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) adma_packet_start(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case ATAPI_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pp->state = adma_state_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static inline unsigned int adma_intr_pkt(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int handled = 0, port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (port_no = 0; port_no < host->n_ports; ++port_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct ata_port *ap = host->ports[port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct adma_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void __iomem *chan = ADMA_PORT_REGS(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u8 status = readb(chan + ADMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) adma_enter_reg_mode(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!pp || pp->state != adma_state_pkt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) qc = ata_qc_from_tag(ap, ap->link.active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (status & aPERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) qc->err_mask |= AC_ERR_HOST_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) else if ((status & (aPSD | aUIRQ)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) qc->err_mask |= AC_ERR_OTHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (pp->pkt[0] & cATERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) qc->err_mask |= AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else if (pp->pkt[0] != cDONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) qc->err_mask |= AC_ERR_OTHER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!qc->err_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ata_qc_complete(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ata_ehi_clear_desc(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ata_ehi_push_desc(ehi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "ADMA-status 0x%02X", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ata_ehi_push_desc(ehi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "pkt[0] 0x%02X", pp->pkt[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (qc->err_mask == AC_ERR_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ata_port_abort(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline unsigned int adma_intr_mmio(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int handled = 0, port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (port_no = 0; port_no < host->n_ports; ++port_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct ata_port *ap = host->ports[port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct adma_port_priv *pp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!pp || pp->state != adma_state_mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) qc = ata_qc_from_tag(ap, ap->link.active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* check main status, clearing INTRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 status = ata_sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if ((status & ATA_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ap->print_id, qc->tf.protocol, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* complete taskfile transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pp->state = adma_state_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) qc->err_mask |= ac_err_mask(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!qc->err_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ata_qc_complete(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ata_ehi_clear_desc(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ata_ehi_push_desc(ehi, "status 0x%02X", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (qc->err_mask == AC_ERR_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ata_port_abort(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static irqreturn_t adma_intr(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) VPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) handled = adma_intr_pkt(host) | adma_intr_mmio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) VPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) port->cmd_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) port->data_addr = base + 0x000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) port->error_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) port->feature_addr = base + 0x004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) port->nsect_addr = base + 0x008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) port->lbal_addr = base + 0x00c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) port->lbam_addr = base + 0x010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) port->lbah_addr = base + 0x014;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) port->device_addr = base + 0x018;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) port->status_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) port->command_addr = base + 0x01c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) port->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) port->ctl_addr = base + 0x038;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int adma_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct device *dev = ap->host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct adma_port_priv *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) adma_enter_reg_mode(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!pp->pkt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* paranoia? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if ((pp->pkt_dma & 7) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) (u32)pp->pkt_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ap->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) adma_reinit_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void adma_port_stop(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) adma_reset_engine(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static void adma_host_init(struct ata_host *host, unsigned int chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned int port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* enable/lock aGO operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* reset the ADMA logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) adma_reset_engine(host->ports[port_no]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int adma_ata_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int board_idx = (unsigned int) ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int rc, port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* alloc host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* acquire resources and fill host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) host->iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mmio_base = host->iomap[ADMA_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_err(&pdev->dev, "32-bit DMA enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct ata_port *ap = host->ports[port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned int offset = port_base - mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) adma_ata_setup_port(&ap->ioaddr, port_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* initialize adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) adma_host_init(host, board_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) &adma_ata_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) module_pci_driver(adma_ata_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MODULE_AUTHOR("Mark Lord");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags