^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_via.c - VIA PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2005-2006 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Most chipset documentation available under NDA only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * VIA version guide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * VIA VT82C561 - early design, uses ata_generic currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * VIA VT82C576 - MWDMA, 33Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * VIA VT82C586 - MWDMA, 33Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * VIA VT82C586a - Added UDMA to 33Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * VIA VT82C586b - UDMA33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * VIA VT82C596a - Nonfunctional UDMA66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * VIA VT82C596b - Working UDMA66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * VIA VT82C686 - Nonfunctional UDMA66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * VIA VT82C686a - Working UDMA66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * VIA VT82C686b - Updated to UDMA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * VIA VT8231 - UDMA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * VIA VT8233 - UDMA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * VIA VT8233a - UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * VIA VT8233c - UDMA100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * VIA VT8235 - UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * VIA VT8237 - UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * VIA VT8237A - UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * VIA VT8237S - UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * VIA VT8251 - UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Most registers remain compatible across chips. Others start reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * and acquire sensible semantics if set to 1 (eg cable detect). A few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * exceptions exist, notably around the FIFO settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * One additional quirk of the VIA design is that like ALi they use few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * PCI IDs for a lot of chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Based heavily on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Version 3.38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * VIA IDE driver for Linux. Supported southbridges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * vt8235, vt8237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Copyright (c) 2000-2002 Vojtech Pavlik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Based on the work of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Michel Aubry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Jeff Garzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Andre Hedrick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRV_NAME "pata_via"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRV_VERSION "0.3.4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) VIA_NO_ENABLES = 0x40, /* Has no enablebits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * VIA SouthBridge chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct via_isa_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 rev_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 rev_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 udma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } via_isa_bridges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct dmi_system_id no_atapi_dma_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .ident = "AVERATEC 3200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DMI_MATCH(DMI_BOARD_VENDOR, "AVERATEC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DMI_MATCH(DMI_BOARD_NAME, "3200"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct via_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 cached_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Cable special cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct dmi_system_id cable_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ident = "Acer Ferrari 3400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int via_cable_override(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Systems by DMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (dmi_check_system(cable_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Arima W730-K8/Targa Visionary 811/... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * via_cable_detect - cable detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Perform cable detection. Actually for the VIA case the BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * already did this for us. We read the values provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * BIOS. If you are using an 8235 in a non-PC configuration you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * may need to update this code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Hotplug also impacts on this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int via_cable_detect(struct ata_port *ap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const struct via_isa_bridge *config = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 ata66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (via_cable_override(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Early chips are 40 wire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (config->udma_mask < ATA_UDMA4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* UDMA 66 chips have only drive side logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else if (config->udma_mask < ATA_UDMA5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ATA_CBL_PATA_UNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* UDMA 100 or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_read_config_dword(pdev, 0x50, &ata66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Check both the drive cable reporting bits, we might not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) two drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ata66 & (0x10100000 >> (16 * ap->port_no)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Check with ACPI so we can spot BIOS reported SATA bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ata_acpi_init_gtm(ap) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int via_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const struct via_isa_bridge *config = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!(config->flags & VIA_NO_ENABLES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct pci_bits via_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x40, 1, 0x02, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x40, 1, 0x01, 0x01 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * via_do_set_mode - set transfer mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @mode: ATA mode being programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @set_ast: Set to program address setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @udma_type: UDMA mode/format of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Program the VIA registers for DMA and PIO modes. Uses the ata timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * support in order to compute modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * FIXME: Hotplug will require we serialize multiple mode changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * on the two channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int mode, int set_ast, int udma_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct ata_device *peer = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct ata_timing t, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int via_clock = 33333; /* Bus clock in kHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long T = 1000000000 / via_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long UT = T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int ut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int offset = 3 - (2*ap->port_no) - adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (udma_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case ATA_UDMA4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) UT = T / 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case ATA_UDMA5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) UT = T / 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case ATA_UDMA6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) UT = T / 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Calculate the timing values we require */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ata_timing_compute(adev, mode, &t, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* We share 8bit timing so we must merge the constraints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (peer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (peer->pio_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Address setup is programmable but breaks on UDMA133 setups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (set_ast) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 setup; /* 2 bits per drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int shift = 2 * offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pci_read_config_byte(pdev, 0x4C, &setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) setup &= ~(3 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) setup |= (clamp_val(t.setup, 1, 4) - 1) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pci_write_config_byte(pdev, 0x4C, setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Load the PIO mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pci_write_config_byte(pdev, 0x4F - ap->port_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pci_write_config_byte(pdev, 0x48 + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Load the UDMA bits according to type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) switch (udma_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case ATA_UDMA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case ATA_UDMA4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case ATA_UDMA5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case ATA_UDMA6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Set UDMA unless device is not UDMA capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (udma_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u8 udma_etc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pci_read_config_byte(pdev, 0x50 + offset, &udma_etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* clear transfer mode bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) udma_etc &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (t.udma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* preserve 80-wire cable detection bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) udma_etc &= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) udma_etc |= ut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pci_write_config_byte(pdev, 0x50 + offset, udma_etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct via_isa_bridge *config = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const struct via_isa_bridge *config = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * via_mode_filter - filter buggy device/mode pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @dev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @mask: Mode bitmask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * We need to apply some minimal filtering for old controllers and at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * one breed of Transcend SSD. Return the updated mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct ata_host *host = dev->link->ap->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const struct via_isa_bridge *config = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (config->id == PCI_DEVICE_ID_VIA_82C586_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (strcmp(model_num, "TS64GSSD25-M") == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ata_dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "disabling UDMA mode due to reported lockups with this device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mask &= ~ ATA_MASK_UDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (dev->class == ATA_DEV_ATAPI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dmi_check_system(no_atapi_dma_dmi_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ata_dev_warn(dev, "controller locks up on ATAPI DMA, forcing PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mask &= ATA_MASK_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * via_tf_load - send taskfile registers to host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * @ap: Port to which output is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * @tf: ATA taskfile register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Outputs ATA taskfile to standard ATA host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Note: This is to fix the internal bug of via chipsets, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * will reset the device register after changing the IEN bit on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * ctl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct via_port *vp = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int newctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (tf->ctl != ap->last_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) iowrite8(tf->ctl, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) newctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (tf->flags & ATA_TFLAG_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) iowrite8(tf->device, ioaddr->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) vp->cached_device = tf->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } else if (newctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) iowrite8(vp->cached_device, ioaddr->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) WARN_ON_ONCE(!ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) iowrite8(tf->hob_feature, ioaddr->feature_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tf->hob_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tf->hob_nsect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tf->hob_lbal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tf->hob_lbam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tf->hob_lbah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (is_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) iowrite8(tf->feature, ioaddr->feature_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) iowrite8(tf->nsect, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) iowrite8(tf->lbal, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) iowrite8(tf->lbam, ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) iowrite8(tf->lbah, ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tf->feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) tf->nsect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tf->lbal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tf->lbam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tf->lbah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int via_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct via_port *vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int ret = ata_bmdma_port_start(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (vp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ap->private_data = vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct scsi_host_template via_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct ata_port_operations via_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .cable_detect = via_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .set_piomode = via_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .set_dmamode = via_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .prereset = via_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .sff_tf_load = via_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .port_start = via_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .mode_filter = via_mode_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct ata_port_operations via_port_ops_noirq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .inherits = &via_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .sff_data_xfer = ata_sff_data_xfer32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * via_config_fifo - set up the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * @pdev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @flags: configuration flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Set the FIFO properties for this device if necessary. Used both on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * set up and on and the resume path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* 0x40 low bits indicate enabled channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pci_read_config_byte(pdev, 0x40 , &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) enable &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (flags & VIA_SET_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pci_read_config_byte(pdev, 0x43, &fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Clear PREQ# until DDACK# for errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (flags & VIA_BAD_PREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fifo &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) fifo &= 0x9f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Turn on FIFO for enabled channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) fifo |= fifo_setting[enable];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pci_write_config_byte(pdev, 0x43, fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void via_fixup(struct pci_dev *pdev, const struct via_isa_bridge *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Initialise the FIFO for the enabled channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) via_config_fifo(pdev, config->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (config->udma_mask == ATA_UDMA4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* The 66 MHz devices require we enable the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pci_read_config_dword(pdev, 0x50, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) timing |= 0x80008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pci_write_config_dword(pdev, 0x50, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (config->flags & VIA_BAD_CLK66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Disable the 66MHz clock on problem devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pci_read_config_dword(pdev, 0x50, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) timing &= ~0x80008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pci_write_config_dword(pdev, 0x50, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * via_init_one - discovery callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @pdev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @id: PCI table info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * A VIA IDE interface has been discovered. Figure out what revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * and perform configuration work before handing it to the ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Early VIA without UDMA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct ata_port_info via_mwdma_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .port_ops = &via_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Ditto with IRQ masking required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct ata_port_info via_mwdma_info_borked = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .port_ops = &via_port_ops_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* VIA UDMA 33 devices (and borked 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct ata_port_info via_udma33_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .port_ops = &via_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* VIA UDMA 66 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct ata_port_info via_udma66_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .port_ops = &via_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* VIA UDMA 100 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct ata_port_info via_udma100_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .port_ops = &via_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* UDMA133 with bad AST (All current 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const struct ata_port_info via_udma133_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .port_ops = &via_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) const struct ata_port_info *ppi[] = { NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct pci_dev *isa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) const struct via_isa_bridge *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u8 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned long flags = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (flags & VIA_IDFLAG_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ppi[1] = &ata_dummy_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* To find out how the IDE will behave and what features we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) actually have to look at the bridge not the IDE controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) config++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) !!(config->flags & VIA_BAD_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) config->id, NULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 rev = isa->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pci_dev_put(isa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if ((id->device == 0x0415 || id->device == 0x3164) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) (config->id != id->device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (rev >= config->rev_min && rev <= config->rev_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!(config->flags & VIA_NO_ENABLES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* 0x40 low bits indicate enabled channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pci_read_config_byte(pdev, 0x40 , &enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) enable &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (enable == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Clock set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) switch (config->udma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (config->flags & VIA_NO_UNMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ppi[0] = &via_mwdma_info_borked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ppi[0] = &via_mwdma_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case ATA_UDMA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ppi[0] = &via_udma33_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case ATA_UDMA4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ppi[0] = &via_udma66_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case ATA_UDMA5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ppi[0] = &via_udma100_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case ATA_UDMA6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ppi[0] = &via_udma133_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) via_fixup(pdev, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* We have established the device type, now fire it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * via_reinit_one - reinit after resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @pdev; PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Called when the VIA PATA device is resumed. We must then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * reconfigure the fifo and other setup we may have altered. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * addition the kernel needs to have the resume methods on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * quirk supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int via_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) via_fixup(pdev, host->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const struct pci_device_id via[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { PCI_VDEVICE(VIA, 0x0415), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { PCI_VDEVICE(VIA, 0x0571), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { PCI_VDEVICE(VIA, 0x0581), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { PCI_VDEVICE(VIA, 0x1571), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) { PCI_VDEVICE(VIA, 0x3164), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { PCI_VDEVICE(VIA, 0x5324), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { PCI_VDEVICE(VIA, 0x9001), VIA_IDFLAG_SINGLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct pci_driver via_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .id_table = via,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .probe = via_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .resume = via_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) module_pci_driver(via_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MODULE_DESCRIPTION("low-level driver for VIA PATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) MODULE_DEVICE_TABLE(pci, via);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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