^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_triflex.c - Compaq PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2005 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * triflex.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * IDE Chipset driver for the Compaq TriFlex IDE controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Known to work with the Compaq Workstation 5x00 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Author: Torben Mathiasen <torben.mathiasen@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Loosely based on the piix & svwks drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Not publicly available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRV_NAME "pata_triflex"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRV_VERSION "0.2.8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * triflex_prereset - probe begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @link: ATA link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Set up cable type and use generic probe init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int triflex_prereset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct pci_bits triflex_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { 0x80, 1, 0x01, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { 0x80, 1, 0x02, 0x02 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * triflex_load_timing - timing configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @adev: Device on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @speed: speed to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * The Triflex has one set of timings per device per channel. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * means we must do some switching. As the PIO and DMA timings don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * match we have to do some reloading unlike PIIX devices where tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * tricks can avoid it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void triflex_load_timing(struct ata_port *ap, struct ata_device *adev, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 timing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 triflex_timing, old_triflex_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int channel_offset = ap->port_no ? 0x74: 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int is_slave = (adev->devno != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pci_read_config_dword(pdev, channel_offset, &old_triflex_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) triflex_timing = old_triflex_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) switch(speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case XFER_MW_DMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) timing = 0x0103;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case XFER_MW_DMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) timing = 0x0203;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case XFER_MW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) timing = 0x0808;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case XFER_SW_DMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case XFER_SW_DMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case XFER_SW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) timing = 0x0F0F;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case XFER_PIO_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) timing = 0x0202;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case XFER_PIO_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) timing = 0x0204;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case XFER_PIO_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) timing = 0x0404;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case XFER_PIO_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) timing = 0x0508;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case XFER_PIO_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) timing = 0x0808;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) triflex_timing &= ~ (0xFFFF << (16 * is_slave));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) triflex_timing |= (timing << (16 * is_slave));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (triflex_timing != old_triflex_timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pci_write_config_dword(pdev, channel_offset, triflex_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * triflex_set_piomode - set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Use the timing loader to set up the PIO mode. We have to do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * because DMA start/stop will only be called once DMA occurs. If there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * has been no DMA then the PIO timings are still needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void triflex_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) triflex_load_timing(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * triflex_dma_start - DMA start callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @qc: Command in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Usually drivers set the DMA timing at the point the set_dmamode call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * is made. Triflex however requires we load new timings on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * transition or keep matching PIO/DMA pairs (ie MWDMA2/PIO4 etc).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * We load the DMA timings just before starting DMA and then restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * the PIO timing when the DMA is finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void triflex_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) triflex_load_timing(qc->ap, qc->dev, qc->dev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ata_bmdma_start(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * triflex_dma_stop - DMA stop callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * We loaded new timings in dma_start, as a result we need to restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * the PIO timings in dma_stop so that the next command issue gets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * right clock values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void triflex_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ata_bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) triflex_load_timing(qc->ap, qc->dev, qc->dev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct scsi_host_template triflex_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct ata_port_operations triflex_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .bmdma_start = triflex_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .bmdma_stop = triflex_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .set_piomode = triflex_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .prereset = triflex_prereset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int triflex_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .port_ops = &triflex_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ata_print_version_once(&dev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ata_pci_bmdma_init_one(dev, ppi, &triflex_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct pci_device_id triflex[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { PCI_VDEVICE(COMPAQ, PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int triflex_ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rc = ata_host_suspend(host, mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * We must not disable or powerdown the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * APM bios refuses to suspend if IDE is not accessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct pci_driver triflex_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .id_table = triflex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .probe = triflex_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .suspend = triflex_ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .resume = ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) module_pci_driver(triflex_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DESCRIPTION("low-level driver for Compaq Triflex");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(pci, triflex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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