^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_sis.c - SiS ATA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) 2005 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) 2007,2009 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based upon linux/drivers/ide/pci/sis5513.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SiS Taiwan : for direct support and hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Daniela Engert : for initial ATA100 advices and numerous others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * for checking code correctness, providing patches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Original tests and design on the SiS620 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ATA100 tests and design on the SiS735 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ATA16/33 support from specs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * More Testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "sis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRV_NAME "pata_sis"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRV_VERSION "0.5.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct sis_chipset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u16 device; /* PCI host ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const struct ata_port_info *info; /* Info block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Probably add family, cable detect type etc here to clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) up code later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct sis_laptop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u16 subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u16 subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct sis_laptop sis_laptop[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* devid, subvendor, subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int sis_short_ata40(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const struct sis_laptop *lap = &sis_laptop[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) while (lap->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (lap->device == dev->device &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) lap->subvendor == dev->subsystem_vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) lap->subdevice == dev->subsystem_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) lap++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * sis_old_port_base - return PCI configuration base for dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @adev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Returns the base of the PCI configuration registers for this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int sis_old_port_base(struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * sis_port_base - return PCI configuration base for dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @adev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Returns the base of the PCI configuration registers for this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int sis_port_base(struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ata_port *ap = adev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int port = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 reg54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pci_read_config_dword(pdev, 0x54, ®54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (reg54 & 0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) port = 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return port + (8 * ap->port_no) + (4 * adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * sis_133_cable_detect - check for 40/80 pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @ap: Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Perform cable detection for the later UDMA133 capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * SiS chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int sis_133_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* The top bit of this register is the cable detect bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((tmp & 0x8000) && !sis_short_ata40(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * sis_66_cable_detect - check for 40/80 pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @ap: Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * SiS IDE controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int sis_66_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci_read_config_byte(pdev, 0x48, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tmp >>= ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if ((tmp & 0x10) && !sis_short_ata40(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * sis_pre_reset - probe begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @link: ATA link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Set up cable type and use generic probe init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int sis_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct pci_bits sis_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Clear the FIFO settings. We can't enable the FIFO until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) we know we are poking at a disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pci_write_config_byte(pdev, 0x4B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * sis_set_fifo - Set RWP fifo bits for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @ap: Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * SIS chipsets implement prefetch/postwrite bits for each device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * on both channels. This functionality is not ATAPI compatible and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * must be configured according to the class of device present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 fifoctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 mask = 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mask <<= (2 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mask <<= adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* This holds various bits including the FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_read_config_byte(pdev, 0x4B, &fifoctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) fifoctrl &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Enable for ATA (disk) only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) fifoctrl |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_write_config_byte(pdev, 0x4B, fifoctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * sis_old_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @adev: Device we are configuring for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Set PIO mode for device, in host controller PCI config space. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * function handles PIO set up for all chips that are pre ATA100 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * also early ATA100 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int port = sis_old_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 t1, t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int speed = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sis_set_fifo(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pci_read_config_byte(pdev, port, &t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_read_config_byte(pdev, port + 1, &t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) t1 &= ~0x0F; /* Clear active/recovery timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) t2 &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) t1 |= active[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) t2 |= recovery[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pci_write_config_byte(pdev, port, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pci_write_config_byte(pdev, port + 1, t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * sis_100_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @adev: Device we are configuring for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Set PIO mode for device, in host controller PCI config space. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * function handles PIO set up for ATA100 devices and early ATA133.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int port = sis_old_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int speed = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sis_set_fifo(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pci_write_config_byte(pdev, port, actrec[speed]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * sis_133_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @adev: Device we are configuring for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Set PIO mode for device, in host controller PCI config space. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * function handles PIO set up for the later ATA133 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int speed = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const u32 timing133[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x0C266000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x04263000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x0C0A3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x05093000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const u32 timing100[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x091C4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x031C2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x09072000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x04062000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) sis_set_fifo(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) port = sis_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pci_read_config_dword(pdev, port, &t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) t1 &= 0xC0C00FFF; /* Mask out timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (t1 & 0x08) /* 100 or 133 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) t1 |= timing133[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) t1 |= timing100[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pci_write_config_byte(pdev, port, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * sis_old_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Set UDMA/MWDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * the old ide/pci driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int speed = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int drive_pci = sis_old_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pci_read_config_word(pdev, drive_pci, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (adev->dma_mode < XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* bits 3-0 hold recovery timing bits 8-10 active timing and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) the higher bits are dependent on the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) timing &= ~0x870F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) timing |= mwdma_bits[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) speed = adev->dma_mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) timing &= ~0x6000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) timing |= udma_bits[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pci_write_config_word(pdev, drive_pci, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * sis_66_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * @adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Set UDMA/MWDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * the old ide/pci driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int speed = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int drive_pci = sis_old_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u16 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* MWDMA 0-2 and UDMA 0-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pci_read_config_word(pdev, drive_pci, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (adev->dma_mode < XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* bits 3-0 hold recovery timing bits 8-10 active timing and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) the higher bits are dependent on the device, bit 15 udma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) timing &= ~0x870F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) timing |= mwdma_bits[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) speed = adev->dma_mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) timing &= ~0xF000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) timing |= udma_bits[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pci_write_config_word(pdev, drive_pci, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * sis_100_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Set UDMA/MWDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Handles UDMA66 and early UDMA100 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int speed = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int drive_pci = sis_old_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pci_read_config_byte(pdev, drive_pci + 1, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (adev->dma_mode < XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) speed = adev->dma_mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) timing &= ~0x8F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) timing |= udma_bits[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pci_write_config_byte(pdev, drive_pci + 1, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Set UDMA/MWDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Handles early SiS 961 bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int speed = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int drive_pci = sis_old_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Low 4 bits are timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pci_read_config_byte(pdev, drive_pci + 1, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (adev->dma_mode < XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) speed = adev->dma_mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) timing &= ~0x8F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) timing |= udma_bits[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pci_write_config_byte(pdev, drive_pci + 1, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * sis_133_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Set UDMA/MWDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) port = sis_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pci_read_config_dword(pdev, port, &t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (adev->dma_mode < XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int speed = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) t1 &= 0xC0C00FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* disable UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) t1 &= ~0x00000004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (t1 & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) t1 |= timing_u133[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) t1 |= timing_u100[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* bits 4- cycle time 8 - cvs time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int speed = adev->dma_mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) t1 &= ~0x00000FF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* enable UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) t1 |= 0x00000004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (t1 & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) t1 |= timing_u133[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) t1 |= timing_u100[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pci_write_config_dword(pdev, port, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * sis_133_mode_filter - mode selection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Block UDMA6 on devices that do not support it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct ata_port *ap = adev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int port = sis_port_base(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pci_read_config_dword(pdev, port, &t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* if ATA133 is disabled, mask it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!(t1 & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mask &= ~(0xC0 << ATA_SHIFT_UDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct scsi_host_template sis_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct ata_port_operations sis_133_for_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .set_piomode = sis_133_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .set_dmamode = sis_133_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .cable_detect = sis_133_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static struct ata_port_operations sis_base_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .prereset = sis_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct ata_port_operations sis_133_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .inherits = &sis_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .set_piomode = sis_133_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .set_dmamode = sis_133_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .cable_detect = sis_133_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .mode_filter = sis_133_mode_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static struct ata_port_operations sis_133_early_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .inherits = &sis_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .set_piomode = sis_100_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .set_dmamode = sis_133_early_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .cable_detect = sis_66_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static struct ata_port_operations sis_100_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .inherits = &sis_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .set_piomode = sis_100_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .set_dmamode = sis_100_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .cable_detect = sis_66_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static struct ata_port_operations sis_66_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .inherits = &sis_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .set_piomode = sis_old_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .set_dmamode = sis_66_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .cable_detect = sis_66_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct ata_port_operations sis_old_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .inherits = &sis_base_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .set_piomode = sis_old_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .set_dmamode = sis_old_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct ata_port_info sis_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* No UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .port_ops = &sis_old_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct ata_port_info sis_info33 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .port_ops = &sis_old_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const struct ata_port_info sis_info66 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* No MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .udma_mask = ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .port_ops = &sis_66_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const struct ata_port_info sis_info100 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* No MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .port_ops = &sis_100_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const struct ata_port_info sis_info100_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* No MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .port_ops = &sis_66_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct ata_port_info sis_info133 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .port_ops = &sis_133_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) const struct ata_port_info sis_info133_for_sata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* No MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .port_ops = &sis_133_for_sata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const struct ata_port_info sis_info133_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* No MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .port_ops = &sis_133_early_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Privately shared with the SiS180 SATA driver, not for use elsewhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) EXPORT_SYMBOL_GPL(sis_info133_for_sata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u16 regw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (sis->info == &sis_info133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pci_read_config_word(pdev, 0x50, ®w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (regw & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pci_write_config_word(pdev, 0x50, regw & ~0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pci_read_config_word(pdev, 0x52, ®w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (regw & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) pci_write_config_word(pdev, 0x52, regw & ~0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Fix up latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Set compatibility bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pci_read_config_byte(pdev, 0x49, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!(reg & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pci_write_config_byte(pdev, 0x49, reg | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Fix up latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Set compatibility bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pci_read_config_byte(pdev, 0x52, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!(reg & 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pci_write_config_byte(pdev, 0x52, reg | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (sis->info == &sis_info33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pci_read_config_byte(pdev, PCI_CLASS_PROG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (( reg & 0x0F ) != 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Fall through to ATA16 fixup below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (sis->info == &sis_info || sis->info == &sis_info33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* force per drive recovery and active timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) needed on ATA_33 and below chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pci_read_config_byte(pdev, 0x52, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!(reg & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pci_write_config_byte(pdev, 0x52, reg|0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * sis_init_one - Register SiS ATA PCI device with kernel services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * @pdev: PCI device to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * @ent: Entry in sis_pci_tbl matching with @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * Called from kernel PCI layer. We probe for combined mode (sigh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * and then hand over control to libata, for it to do the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * Inherited from PCI layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * Zero on success, or -ERRNO value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) const struct ata_port_info *ppi[] = { NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct pci_dev *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct sis_chipset *chipset = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct sis_chipset *sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static struct sis_chipset sis_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { 0x0968, &sis_info133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { 0x0966, &sis_info133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { 0x0965, &sis_info133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { 0x0745, &sis_info100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { 0x0735, &sis_info100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { 0x0733, &sis_info100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { 0x0635, &sis_info100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { 0x0633, &sis_info100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) { 0x0640, &sis_info66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { 0x0630, &sis_info66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { 0x0620, &sis_info66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { 0x0540, &sis_info66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { 0x0530, &sis_info66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { 0x5600, &sis_info33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { 0x5598, &sis_info33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { 0x5597, &sis_info33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { 0x5591, &sis_info33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { 0x5582, &sis_info33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { 0x5581, &sis_info33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { 0x5596, &sis_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { 0x5571, &sis_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { 0x5517, &sis_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { 0x5511, &sis_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static struct sis_chipset sis133_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 0x0, &sis_info133_early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static struct sis_chipset sis133 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 0x0, &sis_info133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static struct sis_chipset sis100_early = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 0x0, &sis_info100_early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static struct sis_chipset sis100 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 0x0, &sis_info100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* We have to find the bridge first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) for (sets = &sis_chipsets[0]; sets->device; sets++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (host != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) chipset = sets; /* Match found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (sets->device == 0x630) { /* SIS630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (host->revision >= 0x30) /* 630 ET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) chipset = &sis100_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Look for concealed bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (chipset == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Second check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 idemisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u16 trueid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Disable ID masking and register remapping then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) see what the real ID is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pci_read_config_dword(pdev, 0x54, &idemisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pci_write_config_dword(pdev, 0x54, idemisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) switch(trueid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case 0x5518: /* SIS 962/963 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "SiS 962/963 MuTIOL IDE UDMA133 controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) chipset = &sis133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if ((idemisc & 0x40000000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "Switching to 5513 register mapping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case 0x0180: /* SIS 965/965L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) chipset = &sis133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case 0x1180: /* SIS 966/966L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) chipset = &sis133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Further check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (chipset == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct pci_dev *lpc_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u16 trueid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 prefctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u8 idecfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* Try the second unmasking technique */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) pci_read_config_byte(pdev, 0x4a, &idecfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pci_write_config_byte(pdev, 0x4a, idecfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) switch(trueid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case 0x5517:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (lpc_bridge == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pci_read_config_byte(pdev, 0x49, &prefctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pci_dev_put(lpc_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) chipset = &sis133_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) chipset = &sis100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pci_dev_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* No chipset info, no support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (chipset == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ppi[0] = chipset->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) sis_fixup(pdev, chipset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int sis_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) sis_fixup(pdev, host->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const struct pci_device_id sis_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static struct pci_driver sis_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .id_table = sis_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .probe = sis_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .resume = sis_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) module_pci_driver(sis_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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