^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_sch.c - Intel SCH PATA controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Alek Du <alek.du@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Intel SCH (AF82US15W, AF82US15L, AF82UL11L) chipsets -- see spec at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * http://download.intel.com/design/chipsets/embedded/datashts/319537.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_NAME "pata_sch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_VERSION "0.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* see SCH datasheet page 351 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) D0TIM = 0x80, /* Device 0 Timing Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) D1TIM = 0x84, /* Device 1 Timing Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PM = 0x07, /* PIO Mode Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MDM = (0x03 << 8), /* Multi-word DMA Mode Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) UDM = (0x07 << 16), /* Ultra DMA Mode Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PPE = (1 << 30), /* Prefetch/Post Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) USD = (1 << 31), /* Use Synchronous DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int sch_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void sch_set_piomode(struct ata_port *ap, struct ata_device *adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void sch_set_dmamode(struct ata_port *ap, struct ata_device *adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct pci_device_id sch_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Intel SCH PATA Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SCH_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct pci_driver sch_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .id_table = sch_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .probe = sch_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .resume = ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct scsi_host_template sch_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct ata_port_operations sch_pata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .cable_detect = ata_cable_unknown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .set_piomode = sch_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .set_dmamode = sch_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct ata_port_info sch_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .port_ops = &sch_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_AUTHOR("Alek Du <alek.du@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_DESCRIPTION("SCSI low-level driver for Intel SCH PATA controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_DEVICE_TABLE(pci, sch_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * sch_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Set PIO mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void sch_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pci_dev *dev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int port = adev->devno ? D1TIM : D0TIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci_read_config_dword(dev, port, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* see SCH datasheet page 351 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* set PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) data &= ~(PM | PPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) data |= pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* enable PPE for block device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) data |= PPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_write_config_dword(dev, port, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * sch_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Set MW/UDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void sch_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int dma_mode = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pci_dev *dev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int port = adev->devno ? D1TIM : D0TIM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pci_read_config_dword(dev, port, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* see SCH datasheet page 351 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (dma_mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* enable Synchronous DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) data |= USD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) data &= ~UDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) data |= (dma_mode - XFER_UDMA_0) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } else { /* must be MWDMA mode, since we masked SWDMA already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) data &= ~(USD | MDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) data |= (dma_mode - XFER_MW_DMA_0) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pci_write_config_dword(dev, port, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * sch_init_one - Register SCH ATA PCI device with kernel services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @pdev: PCI device to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @ent: Entry in sch_pci_tbl matching with @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Inherited from PCI layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Zero on success, or -ERRNO value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int sch_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct ata_port_info *ppi[] = { &sch_port_info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ata_pci_bmdma_init_one(pdev, ppi, &sch_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) module_pci_driver(sch_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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