Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * New ATA layer SC1200 driver		Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * TODO: Mode selection filtering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * TODO: Needs custom DMA cleanup code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Based very heavily on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * linux/drivers/ide/pci/sc1200.c		Version 0.91	28-Jan-2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Copyright (C) 2000-2002		Mark Lord <mlord@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Development of this chipset driver was funded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * by the nice folks at National Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DRV_NAME	"pata_sc1200"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRV_VERSION	"0.2.6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SC1200_REV_A	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SC1200_REV_B1	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SC1200_REV_B3	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SC1200_REV_C1	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SC1200_REV_D1	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *	sc1200_clock	-	PCI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *	Return the PCI bus clocking for the SC1200 chipset configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *	in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int sc1200_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* Magic registers that give us the chipset data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u8 chip_id = inb(0x903C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u8 silicon_rev = inb(0x903D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u16 pci_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (chip_id == 0x04 && silicon_rev < SC1200_REV_B1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return 0;	/* 33 MHz mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* Clock generator configuration 0x901E its 8/9 are the PCI clocking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	   0/3 is 33Mhz 1 is 48 2 is 66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	pci_clock = inw(0x901E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	pci_clock >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	pci_clock &= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (pci_clock == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		pci_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return pci_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *	sc1200_set_piomode		-	PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *	@adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *	Set our PIO requirements. This is fairly simple on the SC1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void sc1200_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	static const u32 pio_timings[4][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		/* format0, 33Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		{ 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		/* format1, 33Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		{ 0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		/* format1, 48Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		{ 0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		/* format1, 66Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		{ 0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned int reg = 0x40 + 0x10 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int mode = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	pci_read_config_dword(pdev, reg + 4, &format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	format >>= 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	format += sc1200_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	pci_write_config_dword(pdev, reg + 8 * adev->devno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				pio_timings[format][mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *	sc1200_set_dmamode		-	DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  *	@adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *	We cannot mix MWDMA and UDMA without reloading timings each switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *	master to slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void sc1200_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	static const u32 udma_timing[3][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		{ 0x00921250, 0x00911140, 0x00911030 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		{ 0x00932470, 0x00922260, 0x00922140 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		{ 0x009436A1, 0x00933481, 0x00923261 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	static const u32 mwdma_timing[3][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		{ 0x00077771, 0x00012121, 0x00002020 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		{ 0x000BBBB2, 0x00024241, 0x00013131 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		{ 0x000FFFF3, 0x00035352, 0x00015151 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int clock = sc1200_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int reg = 0x40 + 0x10 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int mode = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (mode >= XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		format = udma_timing[clock][mode - XFER_UDMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		format = mwdma_timing[clock][mode - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (adev->devno == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		u32 timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		pci_read_config_dword(pdev, reg + 4, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		timings &= 0x80000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		timings |= format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		pci_write_config_dword(pdev, reg + 4, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		pci_write_config_dword(pdev, reg + 12, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  *	sc1200_qc_issue		-	command issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  *	@qc: command pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  *	Called when the libata layer is about to issue a command. We wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *	this interface so that we can load the correct ATA timings if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  *	necessary.  Specifically we have a problem that there is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  *	one MWDMA/UDMA bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static unsigned int sc1200_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct ata_device *prev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* See if the DMA settings could be wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (ata_dma_enabled(adev) && adev != prev && prev != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		/* Maybe, but do the channels match MWDMA/UDMA ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if ((ata_using_udma(adev) && !ata_using_udma(prev)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		    (ata_using_udma(prev) && !ata_using_udma(adev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		    	/* Switch the mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		    	sc1200_set_dmamode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return ata_bmdma_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *	sc1200_qc_defer	-	implement serialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  *	@qc: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *	Serialize command issue on this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int sc1200_qc_defer(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct ata_host *host = qc->ap->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* First apply the usual rules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	rc = ata_std_qc_defer(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* Now apply serialization rules. Only allow a command if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	   other channel state machine is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (alt && alt->qc_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return	ATA_DEFER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct scsi_host_template sc1200_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.sg_tablesize	= LIBATA_DUMB_MAX_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct ata_port_operations sc1200_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.inherits	= &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.qc_prep 	= ata_bmdma_dumb_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.qc_issue	= sc1200_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.qc_defer	= sc1200_qc_defer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.cable_detect	= ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.set_piomode	= sc1200_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.set_dmamode	= sc1200_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *	sc1200_init_one		-	Initialise an SC1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  *	@dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  *	@id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *	Just throw the needed data at the libata helper and it does all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  *	our work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.port_ops = &sc1200_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return ata_pci_bmdma_init_one(dev, ppi, &sc1200_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct pci_device_id sc1200[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct pci_driver sc1200_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.name 		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.id_table	= sc1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.probe 		= sc1200_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.resume		= ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) module_pci_driver(sc1200_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_AUTHOR("Alan Cox, Mark Lord");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MODULE_DESCRIPTION("low-level driver for the NS/AMD SC1200");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DEVICE_TABLE(pci, sc1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_VERSION(DRV_VERSION);