^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * PATA driver for Samsung SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Supports CF Interface in True IDE mode. Currently only PIO mode has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * implemented; UDMA support has to be added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * PATA driver for AT91SAM9260 Static Memory Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * PATA driver for Toshiba SCC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/ata-samsung_cf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRV_NAME "pata_samsung_cf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRV_VERSION "0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C_CFATA_REG(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C_CFATA_MUX S3C_CFATA_REG(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C_ATA_CTRL S3C_CFATA_REG(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C_ATA_CMD S3C_CFATA_REG(0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C_ATA_IRQ S3C_CFATA_REG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C_ATA_CFG S3C_CFATA_REG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C_CFATA_MUX_TRUEIDE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C_ATA_CFG_SWAP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S3C_ATA_CFG_IORDYEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum s3c_cpu_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) TYPE_S3C64XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) TYPE_S5PV210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * struct s3c_ide_info - S3C PATA instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @clk: The clock resource for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @ide_addr: The area mapped for the hardware registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @sfr_addr: The area mapped for the special function registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @irq: The IRQ number we are using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @cpu_type: The exact type of this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct s3c_ide_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *ide_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *sfr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum s3c_cpu_type cpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int fifo_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Select true-ide as the internal operating mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) s3c_ide_sfrbase + S3C_CFATA_MUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int t1 = ata->setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int t2 = ata->act8b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int t2i = ata->rec8b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ulong piotime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return piotime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct s3c_ide_info *info = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct ata_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int cycle_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ulong piotime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Enables IORDY if mode requires it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ata_pio_need_iordy(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ata_cfg |= S3C_ATA_CFG_IORDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ata_timing_compute(adev, adev->pio_mode, &timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cycle_time * 1000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) piotime = pata_s3c_setup_timing(info, &timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Waits until the IDE controller is able to perform next read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * operation to the disk. Needed for 64XX series boards only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int wait_for_host_ready(struct s3c_ide_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ulong timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* wait for maximum of 20 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) timeout = jiffies + msecs_to_jiffies(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if ((readl(fifo_reg) >> 28) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Writes to one of the task file registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct s3c_ide_info *info = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) wait_for_host_ready(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writeb(addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Reads from one of the task file registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static u8 ata_inb(struct ata_host *host, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct s3c_ide_info *info = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) wait_for_host_ready(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (void) readb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) wait_for_host_ready(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * pata_s3c_tf_load - send taskfile registers to host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void pata_s3c_tf_load(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (tf->ctl != ap->last_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (is_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (tf->flags & ATA_TFLAG_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ata_outb(ap->host, tf->device, ioaddr->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * pata_s3c_tf_read - input device's ATA taskfile shadow registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tf->feature = ata_inb(ap->host, ioaddr->error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tf->device = ata_inb(ap->host, ioaddr->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (tf->flags & ATA_TFLAG_LBA48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * pata_s3c_exec_command - issue ATA command to host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void pata_s3c_exec_command(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ata_sff_pause(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * pata_s3c_check_status - Read device status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static u8 pata_s3c_check_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ata_inb(ap->host, ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * pata_s3c_check_altstatus - Read alternate device status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static u8 pata_s3c_check_altstatus(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * pata_s3c_data_xfer - Transfer data by PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static unsigned int pata_s3c_data_xfer(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned char *buf, unsigned int buflen, int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct ata_port *ap = qc->dev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct s3c_ide_info *info = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *data_addr = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int words = buflen >> 1, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u16 *data_ptr = (u16 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Requires wait same as in ata_inb/ata_outb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (rw == READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) for (i = 0; i < words; i++, data_ptr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wait_for_host_ready(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (void) readw(data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) wait_for_host_ready(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *data_ptr = readw(info->ide_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) + S3C_ATA_PIO_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < words; i++, data_ptr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) wait_for_host_ready(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writew(*data_ptr, data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (buflen & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(ap->dev, "unexpected trailing data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return words << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * pata_s3c_dev_select - Select device on ATA bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 tmp = ATA_DEVICE_OBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (device != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) tmp |= ATA_DEV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ata_sff_pause(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * pata_s3c_devchk - PATA device presence detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static unsigned int pata_s3c_devchk(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 nsect, lbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pata_s3c_dev_select(ap, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) nsect = ata_inb(ap->host, ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) lbal = ata_inb(ap->host, ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if ((nsect == 0x55) && (lbal == 0xaa))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 1; /* we found a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0; /* nothing found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * pata_s3c_wait_after_reset - wait for devices to become ready after reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int pata_s3c_wait_after_reset(struct ata_link *link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* always check readiness of the master device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rc = ata_sff_wait_ready(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* -ENODEV means the odd clown forgot the D7 pulldown resistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * and TF status is 0xff, bail out on it too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * pata_s3c_bus_softreset - PATA device software reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int pata_s3c_bus_softreset(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* software reset. causes dev0 to be selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ap->last_ctl = ap->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return pata_s3c_wait_after_reset(&ap->link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * pata_s3c_softreset - reset host port via ATA SRST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int devmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* determine if device 0 is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (pata_s3c_devchk(ap, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) devmask |= (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* select device 0 again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pata_s3c_dev_select(ap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* issue bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rc = pata_s3c_bus_softreset(ap, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* if link is occupied, -ENODEV too is an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (rc && rc != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ata_link_err(link, "SRST failed (errno=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* determine by signature whether we have ATA or ATAPI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) classes[0] = ata_sff_dev_classify(&ap->link.device[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) devmask & (1 << 0), &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * pata_s3c_set_devctl - Write device control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct scsi_host_template pata_s3c_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct ata_port_operations pata_s3c_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .sff_check_status = pata_s3c_check_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .sff_check_altstatus = pata_s3c_check_altstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .sff_tf_load = pata_s3c_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .sff_tf_read = pata_s3c_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .sff_data_xfer = pata_s3c_data_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .sff_exec_command = pata_s3c_exec_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .sff_dev_select = pata_s3c_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .sff_set_devctl = pata_s3c_set_devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .softreset = pata_s3c_softreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .set_piomode = pata_s3c_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct ata_port_operations pata_s5p_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .set_piomode = pata_s3c_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static void pata_s3c_enable(void __iomem *s3c_ide_regbase, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) temp = state ? (temp | 1) : (temp & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct s3c_ide_info *info = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) reg = readl(info->ide_addr + S3C_ATA_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) writel(reg, info->ide_addr + S3C_ATA_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ata_sff_interrupt(irq, dev_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void pata_s3c_hwinit(struct s3c_ide_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct s3c_ide_platdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (info->cpu_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case TYPE_S3C64XX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Configure as big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pata_s3c_cfg_mode(info->sfr_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pata_s3c_set_endian(info->ide_addr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pata_s3c_enable(info->ide_addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Remove IRQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case TYPE_S5PV210:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Configure as little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pata_s3c_set_endian(info->ide_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pata_s3c_enable(info->ide_addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Remove IRQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int __init pata_s3c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct s3c_ide_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum s3c_cpu_type cpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) cpu_type = platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) info->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) info->ide_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (IS_ERR(info->ide_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return PTR_ERR(info->ide_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) info->clk = devm_clk_get(&pdev->dev, "cfcon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (IS_ERR(info->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(dev, "failed to get access to cf controller clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) info->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clk_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* init ata host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) host = ata_host_alloc(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(dev, "failed to allocate ide host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto stop_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (cpu_type == TYPE_S3C64XX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ap->ops = &pata_s3c_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) info->sfr_addr = info->ide_addr + 0x1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) info->ide_addr += 0x1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) info->fifo_status_reg = 0x94;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ap->ops = &pata_s5p_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) info->fifo_status_reg = 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) info->cpu_type = cpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (info->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ap->flags |= ATA_FLAG_PIO_POLLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) info->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ata_port_desc(ap, "no IRQ, using PIO polling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ap->ioaddr.cmd_addr = info->ide_addr + S3C_ATA_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ata_port_desc(ap, "mmio cmd 0x%llx ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) (unsigned long long)res->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) host->private_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (pdata && pdata->setup_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pdata->setup_gpio();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Set endianness and enable the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pata_s3c_hwinit(info, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = ata_host_activate(host, info->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) info->irq ? pata_s3c_irq : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0, &pata_s3c_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto stop_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) stop_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) clk_disable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int __exit pata_s3c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct ata_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct s3c_ide_info *info = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) clk_disable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int pata_s3c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ata_host_suspend(host, PMSG_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int pata_s3c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct s3c_ide_platdata *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct s3c_ide_info *info = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pata_s3c_hwinit(info, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct dev_pm_ops pata_s3c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .suspend = pata_s3c_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .resume = pata_s3c_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* driver device registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const struct platform_device_id pata_s3c_driver_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .name = "s3c64xx-pata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .driver_data = TYPE_S3C64XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "s5pv210-pata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .driver_data = TYPE_S5PV210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct platform_driver pata_s3c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .remove = __exit_p(pata_s3c_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .id_table = pata_s3c_driver_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .pm = &pata_s3c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) module_platform_driver_probe(pata_s3c_driver, pata_s3c_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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