^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generic PXA PATA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/ata-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "pata_pxa"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRV_VERSION "0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct pata_pxa_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dma_cookie_t dma_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct completion dma_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DMA interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void pxa_ata_dma_irq(void *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pata_pxa_data *pd = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (status == DMA_ERROR || status == DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) complete(&pd->dma_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Prepare taskfile for submission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static enum ata_completion_errors pxa_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct pata_pxa_data *pd = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!(qc->flags & ATA_QCFLAG_DMAMAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) tx->callback = pxa_ata_dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tx->callback_param = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pd->dma_cookie = dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Configure the DMA controller, load the DMA descriptors, but don't start the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * DMA controller yet. Only issue the ATA command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Execute the DMA transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void pxa_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pata_pxa_data *pd = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) init_completion(&pd->dma_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dma_async_issue_pending(pd->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Wait until the DMA transfer completes, then stop the DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct pata_pxa_data *pd = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (status != DMA_ERROR && status != DMA_COMPLETE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) wait_for_completion_timeout(&pd->dma_done, HZ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dmaengine_terminate_all(pd->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Read DMA status. The bmdma_stop() will take care of properly finishing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * DMA transfer so we always have DMA-complete interrupt here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned char pxa_bmdma_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct pata_pxa_data *pd = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned char ret = ATA_DMA_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (status != DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret |= ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * No IRQ register present so we do nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void pxa_irq_clear(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * unclear why ATAPI has DMA issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct scsi_host_template pxa_ata_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct ata_port_operations pxa_ata_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .bmdma_setup = pxa_bmdma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .bmdma_start = pxa_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .bmdma_stop = pxa_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .bmdma_status = pxa_bmdma_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .check_atapi_dma = pxa_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .sff_irq_clear = pxa_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .qc_prep = pxa_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int pxa_ata_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct pata_pxa_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct resource *cmd_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct resource *ctl_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct resource *dma_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct resource *irq_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Resource validation, three resources are needed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * - CMD port base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * - CTL port base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * - DMA port base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * - IRQ pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (pdev->num_resources != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(&pdev->dev, "invalid number of resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * CMD port base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (unlikely(cmd_res == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * CTL port base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (unlikely(ctl_res == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * DMA port base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (unlikely(dma_res == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * IRQ pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (unlikely(irq_res == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Allocate the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ap->ops = &pxa_ata_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ap->mwdma_mask = ATA_MWDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) resource_size(cmd_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) resource_size(ctl_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) resource_size(dma_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Adjust register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (ATA_REG_DATA << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) (ATA_REG_ERR << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (ATA_REG_FEATURE << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (ATA_REG_NSECT << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (ATA_REG_LBAL << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) (ATA_REG_LBAM << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (ATA_REG_LBAH << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (ATA_REG_DEVICE << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (ATA_REG_STATUS << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (ATA_REG_CMD << pdata->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Allocate and load driver's internal data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ap->private_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) memset(&config, 0, sizeof(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) config.src_addr = dma_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) config.dst_addr = dma_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) config.src_maxburst = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) config.dst_maxburst = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Request the DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) data->dma_chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dma_request_slave_channel(&pdev->dev, "data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!data->dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = dmaengine_slave_config(data->dma_chan, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Activate the ATA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pdata->irq_flags, &pxa_ata_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dma_release_channel(data->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int pxa_ata_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct ata_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct pata_pxa_data *data = host->ports[0]->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dma_release_channel(data->dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct platform_driver pxa_ata_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .probe = pxa_ata_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .remove = pxa_ata_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) module_platform_driver(pxa_ata_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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