^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ported to libata by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Portions Copyright (C) 1999 Promise Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: Frank Tiernan (frankt@promise.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Released under terms of General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * libata documentation is available via 'make {ps|pdf}docs',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * as Documentation/driver-api/libata.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Hardware information only available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <scsi/scsi_cmnd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRV_NAME "pata_pdc2027x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRV_VERSION "1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #undef PDC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifdef PDC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PDPRINTK(fmt, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PDC_MMIO_BAR = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PDC_UDMA_100 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PDC_UDMA_133 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PDC_100_MHZ = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PDC_133_MHZ = 133333333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PDC_SYS_CTL = 0x1100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PDC_ATA_CTL = 0x1104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PDC_GLOBAL_CTL = 0x1108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PDC_CTCR0 = 0x110C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PDC_CTCR1 = 0x1110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PDC_BYTE_COUNT = 0x1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PDC_PLL_CTL = 0x1202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int pdc2027x_reinit_one(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int pdc2027x_cable_detect(struct ata_port *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ATA Timing Tables based on 133MHz controller clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * These tables are only used when the controller is in 133MHz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * If the controller is in 100MHz clock, the ASIC hardware will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * set the timing registers automatically when "set feature" command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * is issued to the device. However, if the controller clock is 133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * the following tables must be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct pdc2027x_pio_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 value0, value1, value2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } pdc2027x_pio_timing_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct pdc2027x_mdma_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 value0, value1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } pdc2027x_mdma_timing_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0xdf, 0x5f }, /* MDMA mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0x6b, 0x27 }, /* MDMA mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 0x69, 0x25 }, /* MDMA mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct pdc2027x_udma_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 value0, value1, value2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } pdc2027x_udma_timing_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct pci_device_id pdc2027x_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct pci_driver pdc2027x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .id_table = pdc2027x_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .probe = pdc2027x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .resume = pdc2027x_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct scsi_host_template pdc2027x_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct ata_port_operations pdc2027x_pata100_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .check_atapi_dma = pdc2027x_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .cable_detect = pdc2027x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .prereset = pdc2027x_prereset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct ata_port_operations pdc2027x_pata133_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .inherits = &pdc2027x_pata100_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .mode_filter = pdc2027x_mode_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .set_piomode = pdc2027x_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .set_dmamode = pdc2027x_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .set_mode = pdc2027x_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct ata_port_info pdc2027x_port_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* PDC_UDMA_100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .port_ops = &pdc2027x_pata100_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* PDC_UDMA_133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .port_ops = &pdc2027x_pata133_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * port_mmio - Get the MMIO address of PDC2027x extended registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @ap: Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @offset: offset from mmio base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * dev_mmio - Get the MMIO address of PDC2027x extended registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @ap: Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @adev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @offset: offset from mmio base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 adj = (adev->devno) ? 0x08 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return port_mmio(ap, offset) + adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * pdc2027x_pata_cable_detect - Probe host controller cable detect info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @ap: Port for which cable detect info is desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Read 80c cable indicator from Promise extended register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * This register is latched when the system is reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int pdc2027x_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 cgcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* check cable detect results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (cgcr & (1 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto cbl40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cbl40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @ap: Port to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline int pdc2027x_port_enabled(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * pdc2027x_prereset - prereset for PATA host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @link: Target link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Probeinit including cable detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Check whether port enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!pdc2027x_port_enabled(link->ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * pdc2720x_mode_filter - mode selection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @mask: list of modes proposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Block UDMA on devices that cause trouble with this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Check for slave of a Maxtor at UDMA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ATA_ID_PROD_LEN + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @ap: Port to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @adev: um
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Set PIO mode for device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 ctcr0, ctcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (pio > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Set the PIO timing registers using value table for 133MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PDPRINTK("Set pio regs... \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ctcr0 &= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (pdc2027x_pio_timing_tbl[pio].value1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ctcr1 &= 0x00ffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PDPRINTK("Set pio regs done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PDPRINTK("Set to pio mode[%u] \n", pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @ap: Port to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * @adev: um
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Set UDMA mode for device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int dma_mode = adev->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 ctcr0, ctcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if ((dma_mode >= XFER_UDMA_0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (dma_mode <= XFER_UDMA_6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Set the UDMA timing registers with value table for 133MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int udma_mode = dma_mode & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (dma_mode == XFER_UDMA_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Turn off tHOLD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * If tHOLD is '1', the hardware will add half clock for data hold time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * This code segment seems to be no effect. tHOLD will be overwritten below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PDPRINTK("Set udma regs... \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ctcr1 &= 0xff000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PDPRINTK("Set udma regs done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PDPRINTK("Set to udma mode[%u] \n", udma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else if ((dma_mode >= XFER_MW_DMA_0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) (dma_mode <= XFER_MW_DMA_2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Set the MDMA timing registers with value table for 133MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int mdma_mode = dma_mode & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PDPRINTK("Set mdma regs... \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ctcr0 &= 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PDPRINTK("Set mdma regs done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * pdc2027x_set_mode - Set the timing registers back to correct values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @link: link to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @r_failed: Returned device for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * This function overwrites the possibly incorrect values set by the hardware to be correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) rc = ata_do_set_mode(link, r_failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ata_for_each_dev(dev, link, ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pdc2027x_set_piomode(ap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Enable prefetch if the device support PIO only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (dev->xfer_shift == ATA_SHIFT_PIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ctcr1 |= (1 << 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PDPRINTK("Turn on prefetch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pdc2027x_set_dmamode(ap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * @qc: Metadata associated with taskfile to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * RETURNS: 0 when ATAPI DMA can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * 1 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct scsi_cmnd *cmd = qc->scsicmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u8 *scsicmd = cmd->cmnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int rc = 1; /* atapi dma off by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * This workaround is from Promise's GPL driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * If ATAPI DMA is used for commands not in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * following white list, say MODE_SENSE and REQUEST_SENSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * pdc2027x might hit the irq lost problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) switch (scsicmd[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case READ_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case WRITE_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case READ_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case WRITE_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case READ_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case WRITE_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case 0xad: /* READ_DVD_STRUCTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case 0xbe: /* READ_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* ATAPI DMA is ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * pdc_read_counter - Read the ctr counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * @host: target ATA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static long pdc_read_counter(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) long counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int retry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 bccrl, bccrh, bccrlv, bccrhv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Read the counter values again for verification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) counter = (bccrh << 15) | bccrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * The 30-bit decreasing counter are read by 2 pieces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Incorrect value may be read when both bccrh and bccrl are changing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PDPRINTK("rereading counter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * adjust_pll - Adjust the PLL input clock in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @pdc_controller: controller specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @host: target ATA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @pll_clock: The input of PLL in HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u16 pll_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) long pll_clock_khz = pll_clock / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) long ratio = pout_required / pll_clock_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int F, R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #ifdef PDC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PDPRINTK("pout_required is %ld\n", pout_required);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Show the current clock value of PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * (maybe already configured by the firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PDPRINTK("pll_ctl[%X]\n", pll_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * Calculate the ratio of F, R and OD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * POUT = (F + 2) / (( R + 2) * NO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ratio < 8600L) { /* 8.6x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Using NO = 0x01, R = 0x0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) R = 0x0d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } else if (ratio < 12900L) { /* 12.9x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Using NO = 0x01, R = 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) R = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) } else if (ratio < 16100L) { /* 16.1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Using NO = 0x01, R = 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) R = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else if (ratio < 64000L) { /* 64x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) R = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Invalid ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) F = (ratio * (R+2)) / 1000 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (unlikely(F < 0 || F > 127)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Invalid F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pll_ctl = (R << 8) | F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ioread16(mmio_base + PDC_PLL_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Wait the PLL circuit to be stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #ifdef PDC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Show the current clock value of PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * (maybe configured by the firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PDPRINTK("pll_ctl[%X]\n", pll_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * detect_pll_input_clock - Detect the PLL input clock in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @host: target ATA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Ex. 16949000 on 33MHz PCI bus for pdc20275.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * Half of the PCI clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static long pdc_detect_pll_input_clock(struct ata_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) long start_count, end_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ktime_t start_time, end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) long pll_clock, usec_elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Start the test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) scr = ioread32(mmio_base + PDC_SYS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PDPRINTK("scr[%X]\n", scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ioread32(mmio_base + PDC_SYS_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Read current counter value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) start_count = pdc_read_counter(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) start_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Let the counter run for 100 ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Read the counter values again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) end_count = pdc_read_counter(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) end_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Stop the test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) scr = ioread32(mmio_base + PDC_SYS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PDPRINTK("scr[%X]\n", scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ioread32(mmio_base + PDC_SYS_CTL); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* calculate the input clock in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) usec_elapsed = (long) ktime_us_delta(end_time, start_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) (100000000 / usec_elapsed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return pll_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * pdc_hardware_init - Initialize the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * @host: target ATA host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * @board_idx: board identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) long pll_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Detect PLL input clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * On some system, where PCI bus is running at non-standard clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pll_clock = pdc_detect_pll_input_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Adjust PLL control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pdc_adjust_pll(host, pll_clock, board_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * pdc_ata_setup_port - setup the mmio address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @port: ata ioports to setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @base: base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) port->cmd_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) port->data_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) port->feature_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) port->error_addr = base + 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) port->nsect_addr = base + 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) port->lbal_addr = base + 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) port->lbam_addr = base + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) port->lbah_addr = base + 0x15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) port->device_addr = base + 0x1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) port->command_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) port->status_addr = base + 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) port->altstatus_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) port->ctl_addr = base + 0x81a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * pdc2027x_init_one - PCI probe function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Called when an instance of PCI adapter is inserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * This function checks whether the hardware is supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * initialize hardware and register an instance of ata_host to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * libata. (implements struct pci_driver.probe() )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * @pdev: instance of pci_dev found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * @ent: matching entry in the id_tbl[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int pdc2027x_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) unsigned int board_idx = (unsigned int) ent->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) const struct ata_port_info *ppi[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { &pdc2027x_port_info[board_idx], NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* alloc host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* acquire resources and fill host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) host->iomap = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) mmio_base = host->iomap[PDC_MMIO_BAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct ata_port *ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) //pci_enable_intx(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* initialize adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pdc_hardware_init(host, board_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) IRQF_SHARED, &pdc2027x_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int pdc2027x_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned int board_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pdev->device == PCI_DEVICE_ID_PROMISE_20270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) board_idx = PDC_UDMA_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) board_idx = PDC_UDMA_133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pdc_hardware_init(host, board_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) module_pci_driver(pdc2027x_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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