^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_optidma.c - Opti DMA PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2006 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * The Opti DMA controllers are related to the older PIO PCI controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * and indeed the VLB ones. The main differences are that the timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * numbers are now based off PCI clocks not VLB and differ, and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * MWDMA is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver should support Viper-N+, FireStar, FireStar Plus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * These devices support virtual DMA for read (aka the CS5520). Later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * chips support UDMA33, but only if the rest of the board logic does,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * so you have to get this right. We don't support the virtual DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * but we do handle UDMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Bits that are worth knowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Most control registers are shadowed into I/O registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Virtual DMA registers *move* between rev 0x02 and rev 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * UDMA requires a 66MHz FSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRV_NAME "pata_optidma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRV_VERSION "0.3.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) READ_REG = 0, /* index of Read cycle timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) WRITE_REG = 1, /* index of Write cycle timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CNTRL_REG = 3, /* index of Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) STRAP_REG = 5, /* index of Strap register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MISC_REG = 6 /* index of Miscellaneous register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int pci_clock; /* 0 = 33 1 = 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * optidma_pre_reset - probe begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @link: ATA link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Set up cable type and use generic probe init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct pci_bits optidma_enable_bits = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x40, 1, 0x08, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * optidma_unlock - unlock control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Unlock the control register block for this adapter. Registers must not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * be unlocked in a situation where libata might look at them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void optidma_unlock(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *regio = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* These 3 unlock the control register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ioread16(regio + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ioread16(regio + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) iowrite8(3, regio + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * optidma_lock - issue temporary relock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Re-lock the configuration register settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void optidma_lock(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *regio = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Relock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) iowrite8(0x83, regio + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * optidma_mode_setup - set mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @mode: Mode to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Called to do the DMA or PIO mode setup. Timing numbers are all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * pre computed to keep the code clean. There are two tables depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * on the hardware clock speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * WARNING: While we do this the IDE registers vanish. If we take an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * IRQ here we depend on the host set locking to avoid catastrophe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int dma = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __iomem *regio = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Address table precomputed with a DCLK of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const u8 addr_timing[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x30, 0x20, 0x20, 0x10, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x20, 0x20, 0x10, 0x10, 0x10 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const u8 data_rec_timing[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x59, 0x46, 0x30, 0x20, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x46, 0x32, 0x20, 0x20, 0x10 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const u8 dma_data_rec_timing[2][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0x76, 0x20, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x54, 0x20, 0x10 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Switch from IDE to control mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) optidma_unlock(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * As with many controllers the address setup time is shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * and must suit both devices if present. FIXME: Check if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * need to look at slowest of PIO/DMA mode of either device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (mode >= XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) addr = addr_timing[pci_clock][pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 pair_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Hardware constraint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (pair->dma_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pair_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (pair_addr > addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) addr = pair_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Commence primary programming sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* First we load the device number into the timing select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) iowrite8(adev->devno, regio + MISC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Now we load the data timings into read data/write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (mode < XFER_MW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else if (mode < XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Finally we load the address setup into the misc register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) iowrite8(addr | adev->devno, regio + MISC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) iowrite8(0x85, regio + CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Switch back to IDE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) optidma_lock(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Note: at this point our programming is incomplete. We are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) not supposed to program PCI 0x43 "things we hacked onto the chip"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) until we've done both sets of PIO/DMA timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * optiplus_mode_setup - DMA setup for Firestar Plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @adev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @mode: desired mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * The Firestar plus has additional UDMA functionality for UDMA0-2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * requires we do some additional work. Because the base work we must do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * is mostly shared we wrap the Firestar setup functionality in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 udcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 udslave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int dev2 = 2 * adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int unit = 2 * ap->port_no + adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int udma = mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pci_read_config_byte(pdev, 0x44, &udcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (mode <= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) udcfg &= ~(1 << unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) optidma_mode_setup(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) udcfg |= (1 << unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ap->port_no) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pci_read_config_byte(pdev, 0x45, &udslave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) udslave &= ~(0x03 << dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) udslave |= (udma << dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pci_write_config_byte(pdev, 0x45, udslave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) udcfg &= ~(0x30 << dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) udcfg |= (udma << dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pci_write_config_byte(pdev, 0x44, udcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * optidma_set_pio_mode - PIO setup callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * The libata core provides separate functions for handling PIO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * DMA programming. The architecture of the Firestar makes it easier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * for us to have a common function so we provide wrappers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) optidma_mode_setup(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * optidma_set_dma_mode - DMA setup callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * The libata core provides separate functions for handling PIO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * DMA programming. The architecture of the Firestar makes it easier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * for us to have a common function so we provide wrappers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) optidma_mode_setup(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * optiplus_set_pio_mode - PIO setup callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * The libata core provides separate functions for handling PIO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * DMA programming. The architecture of the Firestar makes it easier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * for us to have a common function so we provide wrappers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) optiplus_mode_setup(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * optiplus_set_dma_mode - DMA setup callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * The libata core provides separate functions for handling PIO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * DMA programming. The architecture of the Firestar makes it easier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * for us to have a common function so we provide wrappers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) optiplus_mode_setup(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * optidma_make_bits - PCI setup helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Turn the ATA device setup into PCI configuration bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * for register 0x43 and return the two bits needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static u8 optidma_make_bits43(struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const u8 bits43[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0, 0, 0, 1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!ata_dev_enabled(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (adev->dma_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return bits43[adev->pio_mode - XFER_PIO_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * optidma_set_mode - mode setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @link: link to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Use the standard setup to tune the chipset and then finalise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * configuration by writing the nibble of extra bits of data into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int nybble = 4 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int rc = ata_do_set_mode(link, r_failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pci_read_config_byte(pdev, 0x43, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) r &= (0x0F << nybble);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) r |= (optidma_make_bits43(&link->device[0]) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pci_write_config_byte(pdev, 0x43, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct scsi_host_template optidma_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct ata_port_operations optidma_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .set_piomode = optidma_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .set_dmamode = optidma_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .set_mode = optidma_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .prereset = optidma_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct ata_port_operations optiplus_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .inherits = &optidma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .set_piomode = optiplus_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .set_dmamode = optiplus_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * optiplus_with_udma - Look for UDMA capable setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @pdev; ATA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int optiplus_with_udma(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ioport = 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct pci_dev *dev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Find function 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev1 = pci_get_device(0x1045, 0xC701, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (dev1 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Rev must be >= 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pci_read_config_byte(dev1, 0x08, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (r < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto done_nomsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Read the chipset system configuration to check our mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pci_read_config_byte(dev1, 0x5F, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ioport |= (r << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) outb(0x10, ioport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Must be 66Mhz sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if ((inb(ioport + 2) & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Check the ATA arbitration/timing is suitable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pci_read_config_byte(pdev, 0x42, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if ((r & 0x36) != 0x36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pci_read_config_byte(dev1, 0x52, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (r & 0x80) /* IDEDIR disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) printk(KERN_WARNING "UDMA not supported in this configuration.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) done_nomsg: /* Wrong chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pci_dev_put(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct ata_port_info info_82c700 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .port_ops = &optidma_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct ata_port_info info_82c700_udma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .port_ops = &optiplus_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const struct ata_port_info *ppi[] = { &info_82c700, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ata_print_version_once(&dev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rc = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Fixed location chipset magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) inw(0x1F1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) inw(0x1F1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (optiplus_with_udma(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ppi[0] = &info_82c700_udma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct pci_device_id optidma[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct pci_driver optidma_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .id_table = optidma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .probe = optidma_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .resume = ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) module_pci_driver(optidma_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_DEVICE_TABLE(pci, optidma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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