Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * pata_opti.c 	- ATI PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *			  (C) 2005 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  linux/drivers/ide/pci/opti621.c		Version 0.7	Sept 10, 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Jaromir Koutek <miri@punknet.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Jan Harkes <jaharkes@cwi.nl>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Mark Lord <mlord@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Some parts of code are from ali14xx.c and from rz1000.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Also consulted the FreeBSD prototype driver by Kevin Day to try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * and resolve some confusions. Further documentation can be found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Ralf Brown's interrupt list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * If you have other variants of the Opti range (Viper/Vendetta) please
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * try this driver with those PCI idents and report back. For the later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * chips see the pata_optidma driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DRV_NAME "pata_opti"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DRV_VERSION "0.2.9"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	READ_REG	= 0,	/* index of Read cycle timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	WRITE_REG 	= 1,	/* index of Write cycle timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	CNTRL_REG 	= 3,	/* index of Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	STRAP_REG 	= 5,	/* index of Strap register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	MISC_REG 	= 6	/* index of Miscellaneous register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *	opti_pre_reset		-	probe begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *	@link: ATA link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *	@deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *	Set up cable type and use generic probe init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int opti_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	static const struct pci_bits opti_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		{ 0x45, 1, 0x80, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		{ 0x40, 1, 0x08, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *	opti_write_reg		-	control register setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *	@ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *	@value: value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *	@reg: control register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *	The Opti uses magic 'trapdoor' register accesses to do configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *	rather than using PCI space as other controllers do. The double inw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *	on the error register activates configuration mode. We can then write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *	the control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void opti_write_reg(struct ata_port *ap, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	void __iomem *regio = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* These 3 unlock the control register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ioread16(regio + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ioread16(regio + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	iowrite8(3, regio + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* Do the I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	iowrite8(val, regio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Relock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	iowrite8(0x83, regio + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *	opti_set_piomode	-	set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  *	@adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *	Called to do the PIO mode setup. Timing numbers are taken from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *	the FreeBSD driver then pre computed to keep the code clean. There
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  *	are two tables depending on the hardware clock speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void opti_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	void __iomem *regio = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* Address table precomputed with prefetch off and a DCLK of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	static const u8 addr_timing[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		{ 0x30, 0x20, 0x20, 0x10, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		{ 0x20, 0x20, 0x10, 0x10, 0x10 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	static const u8 data_rec_timing[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		{ 0x6B, 0x56, 0x42, 0x32, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		{ 0x58, 0x44, 0x32, 0x22, 0x21 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	iowrite8(0xff, regio + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	clock = ioread16(regio + 5) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  	 *	As with many controllers the address setup time is shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  	 *	and must suit both devices if present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	addr = addr_timing[clock][pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* Hardware constraint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		u8 pair_addr = addr_timing[clock][pair->pio_mode - XFER_PIO_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		if (pair_addr > addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			addr = pair_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Commence primary programming sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	opti_write_reg(ap, adev->devno, MISC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	opti_write_reg(ap, data_rec_timing[clock][pio], READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	opti_write_reg(ap, addr, MISC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* Programming sequence complete, override strapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	opti_write_reg(ap, 0x85, CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct scsi_host_template opti_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct ata_port_operations opti_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.inherits	= &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.cable_detect	= ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.set_piomode	= opti_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.prereset	= opti_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int opti_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.port_ops = &opti_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	ata_print_version_once(&dev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return ata_pci_sff_init_one(dev, ppi, &opti_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct pci_device_id opti[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct pci_driver opti_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.name 		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.id_table	= opti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.probe 		= opti_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.resume		= ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) module_pci_driver(opti_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_DESCRIPTION("low-level driver for Opti 621/621X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_DEVICE_TABLE(pci, opti);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_VERSION(DRV_VERSION);