^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_oldpiix.c - Intel PATA/SATA controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) 2005 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Some parts based on ata_piix.c by Jeff Garzik and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Early PIIX differs significantly from the later PIIX as it lacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * SITRE and the slave timing registers. This means that you have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * set timing per channel, or be clever. Libata tells us whenever it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * does drive selection and we use this to reload the timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Because of these behaviour differences PIIX gets its own driver module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRV_NAME "pata_oldpiix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRV_VERSION "0.5.5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * oldpiix_pre_reset - probe begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @link: ATA link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Set up cable type and use generic probe init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct pci_bits oldpiix_enable_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * oldpiix_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @adev: Device whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Set PIO mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct pci_dev *dev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u16 idetm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * See Intel Document 298600-004 for the timing programing rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * for PIIX/ICH. Note that the early PIIX does not have the slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * timing port at 0x44.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const /* ISP RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 timings[][2] = { { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 2, 3 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (pio > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) control |= 1; /* TIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ata_pio_need_iordy(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) control |= 2; /* IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Intel specifies that the prefetch/posting is for disk only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) control |= 4; /* PPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pci_read_config_word(dev, idetm_port, &idetm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Set PPE, IE and TIME as appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Clear the other drive's timing bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (adev->devno == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) idetm_data &= 0xCCE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) idetm_data |= control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) idetm_data &= 0xCC0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) idetm_data |= (control << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) idetm_data |= (timings[pio][0] << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (timings[pio][1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pci_write_config_word(dev, idetm_port, idetm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Track which port is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ap->private_data = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * oldpiix_set_dmamode - Initialize host controller PATA DMA timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Set MWDMA mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pci_dev *dev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 idetm_port = ap->port_no ? 0x42 : 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 idetm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const /* ISP RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 timings[][2] = { { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 2, 3 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * MWDMA is driven by the PIO timings. We must also enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * IORDY unconditionally along with TIME1. PPE has already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * been set when the PIO timing was set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const unsigned int needed_pio[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int pio = needed_pio[mwdma] - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pci_read_config_word(dev, idetm_port, &idetm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) control = 3; /* IORDY|TIME0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Intel specifies that the PPE functionality is for disk only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) control |= 4; /* PPE enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* If the drive MWDMA is faster than it can do PIO then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) we must force PIO into PIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (adev->pio_mode < needed_pio[mwdma])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Enable DMA timing only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) control |= 8; /* PIO cycles in PIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Mask out the relevant control and timing bits we will load. Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clear the other drive TIME register as a precaution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (adev->devno == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) idetm_data &= 0xCCE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) idetm_data |= control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) idetm_data &= 0xCC0E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) idetm_data |= (control << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pci_write_config_word(dev, idetm_port, idetm_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Track which port is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ap->private_data = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * oldpiix_qc_issue - command issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @qc: command pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Called when the libata layer is about to issue a command. We wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * this interface so that we can load the correct ATA timings if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * necessary. Our logic also clears TIME0/TIME1 for the other device so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * that, even if we get this wrong, cycles to the other device will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * be made PIO0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (adev != ap->private_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) oldpiix_set_piomode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ata_dma_enabled(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) oldpiix_set_dmamode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ata_bmdma_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct scsi_host_template oldpiix_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct ata_port_operations oldpiix_pata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .qc_issue = oldpiix_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .set_piomode = oldpiix_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .set_dmamode = oldpiix_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .prereset = oldpiix_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * oldpiix_init_one - Register PIIX ATA PCI device with kernel services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @pdev: PCI device to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @ent: Entry in oldpiix_pci_tbl matching with @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Called from kernel PCI layer. We probe for combined mode (sigh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * and then hand over control to libata, for it to do the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Inherited from PCI layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Zero on success, or -ERRNO value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .mwdma_mask = ATA_MWDMA12_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .port_ops = &oldpiix_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ata_pci_bmdma_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct pci_device_id oldpiix_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { PCI_VDEVICE(INTEL, 0x1230), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct pci_driver oldpiix_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .id_table = oldpiix_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .probe = oldpiix_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .resume = ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) module_pci_driver(oldpiix_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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