^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the Octeon bootbus compact flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005 - 2012 Cavium Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2008 Wind River Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The Octeon bootbus compact flash interface is connected in at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 3 different configurations on various evaluation boards:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * -- 8 bits no irq, no DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * -- 16 bits no irq, no DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * -- 16 bits True IDE mode with DMA, but no irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * In the last case the DMA engine can generate an interrupt when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * transfer is complete. For the first two cases only PIO is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRV_NAME "pata_octeon_cf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRV_VERSION "2.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Poll interval in nS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OCTEON_CF_BUSY_POLL_INTERVAL 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DMA_CFG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DMA_TIM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMA_INT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DMA_INT_EN 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct octeon_cf_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct hrtimer delayed_finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int dma_finished;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void *c0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int cs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool is_true_ide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u64 dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct scsi_host_template octeon_cf_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int enable_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) module_param(enable_dma, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MODULE_PARM_DESC(enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Convert nanosecond based time to setting used in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * boot bus timing register, based on timing multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Compute # of eclock periods to get desired duration in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * nanoseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 1000 * tim_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) union cvmx_mio_boot_reg_cfgx reg_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int tim_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (multiplier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tim_mult = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tim_mult = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tim_mult = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tim_mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg_cfg.s.sam = 0; /* Don't combine write and output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg_cfg.s.we_ext = 0; /* No write enable extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg_cfg.s.oe_ext = 0; /* No read enable extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg_cfg.s.en = 1; /* Enable this region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg_cfg.s.orbit = 0; /* Don't combine with previous region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg_cfg.s.ale = 0; /* Don't do address multiplexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Called after libata determines the needed PIO mode. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * function programs the Octeon bootbus regions to support the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * timing requirements of the PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @ap: ATA port information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @dev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct octeon_cf_port *cf_port = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) union cvmx_mio_boot_reg_timx reg_tim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct ata_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int use_iordy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int trh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* These names are timing parameters from the ATA spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * A divisor value of four will overflow the timing fields at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * clock rates greater than 800MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (octeon_get_io_clock_rate() <= 800000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) div = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) t2 = timing.active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (t2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) t2--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) trh = ns_to_tim_reg(div, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (trh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) trh--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pause = (int)timing.cycle - (int)timing.active -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (int)timing.setup - trh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (pause < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pause--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (cf_port->is_true_ide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* True IDE mode, program both chip selects. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) use_iordy = ata_pio_need_iordy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Disable page mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) reg_tim.s.pagem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Enable dynamic timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg_tim.s.waitm = use_iordy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Pages are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) reg_tim.s.pages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* We don't use multiplexed address mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg_tim.s.ale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) reg_tim.s.page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Time after IORDY to coninue to assert the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) reg_tim.s.wait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Time to wait to complete the cycle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reg_tim.s.pause = pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* How long to hold after a write to de-assert CE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg_tim.s.wr_hld = trh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* How long to wait after a read to de-assert CE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg_tim.s.rd_hld = trh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* How long write enable is asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reg_tim.s.we = t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* How long read enable is asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg_tim.s.oe = t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Time after CE that read/write starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) reg_tim.s.ce = ns_to_tim_reg(div, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Time before CE that address is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) reg_tim.s.adr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Program the bootbus region timing for the data port chip select. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (cf_port->is_true_ide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* True IDE mode, program both chip selects. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg_tim.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct octeon_cf_port *cf_port = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) union cvmx_mio_boot_pin_defs pin_defs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) union cvmx_mio_boot_dma_timx dma_tim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int oe_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int oe_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int dma_ackh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int dma_arq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int T0, Tkr, Td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int tim_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const struct ata_timing *timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) timing = ata_timing_find_mode(dev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) T0 = timing->cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) Td = timing->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) Tkr = timing->recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dma_ackh = timing->dmack_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dma_tim.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* dma_tim.s.tim_mult = 0 --> 4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tim_mult = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* not spec'ed, value in eclocks, not affected by tim_mult */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dma_arq = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pause = 25 - dma_arq * 1000 /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (octeon_get_io_clock_rate() / 1000000); /* Tz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) oe_a = Td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Tkr from cf spec, lengthened to meet T0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) oe_n = max(T0 - oe_a, Tkr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* DMA channel number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) c = (cf_port->dma_base & 8) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Invert the polarity if the default is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * This is tI, C.F. spec. says 0, but Sony CF card requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * more, we use 20 nS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dma_tim.s.dmarq = dma_arq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dma_tim.s.rd_dly = 0; /* Sample right on edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* writes only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ns_to_tim_reg(tim_mult, 60));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Handle an 8 bit I/O request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @qc: Queued command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * @buffer: Data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @buflen: Length of the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @rw: True to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static unsigned int octeon_cf_data_xfer8(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned char *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct ata_port *ap = qc->dev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void __iomem *data_addr = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) words = buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (rw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) count = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) while (words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) iowrite8(*buffer, data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) buffer++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Every 16 writes do a read so the bootbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * FIFO doesn't fill up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (--count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ioread8(ap->ioaddr.altstatus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) count = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ioread8_rep(data_addr, buffer, words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Handle a 16 bit I/O request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @qc: Queued command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @buffer: Data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * @buflen: Length of the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @rw: True to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static unsigned int octeon_cf_data_xfer16(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned char *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct ata_port *ap = qc->dev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void __iomem *data_addr = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) words = buflen / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (rw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) count = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) while (words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) iowrite16(*(uint16_t *)buffer, data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) buffer += sizeof(uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Every 16 writes do a read so the bootbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * FIFO doesn't fill up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (--count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ioread8(ap->ioaddr.altstatus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) count = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) while (words--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *(uint16_t *)buffer = ioread16(data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buffer += sizeof(uint16_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Transfer trailing 1 byte, if any. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (unlikely(buflen & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __le16 align_buf[1] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (rw == READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) align_buf[0] = cpu_to_le16(ioread16(data_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) memcpy(buffer, align_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) memcpy(align_buf, buffer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) iowrite16(le16_to_cpu(align_buf[0]), data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) words++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Read the taskfile for 16bit non-True IDE only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u16 blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* The base of the registers is at ioaddr.data_addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void __iomem *base = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) blob = __raw_readw(base + 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tf->feature = blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) blob = __raw_readw(base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tf->nsect = blob & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tf->lbal = blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) blob = __raw_readw(base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tf->lbam = blob & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tf->lbah = blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) blob = __raw_readw(base + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) tf->device = blob & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tf->command = blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (tf->flags & ATA_TFLAG_LBA48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (likely(ap->ioaddr.ctl_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) blob = __raw_readw(base + 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tf->hob_feature = blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) blob = __raw_readw(base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tf->hob_nsect = blob & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tf->hob_lbal = blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) blob = __raw_readw(base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tf->hob_lbam = blob & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tf->hob_lbah = blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static u8 octeon_cf_check_status16(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u16 blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void __iomem *base = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) blob = __raw_readw(base + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return blob >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void __iomem *base = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DPRINTK("about to softreset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __raw_writew(ap->ctl, base + 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __raw_writew(ap->ctl | ATA_SRST, base + 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) __raw_writew(ap->ctl, base + 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) rc = ata_sff_wait_after_reset(link, 1, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ata_link_err(link, "SRST failed (errno=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* determine by signature whether we have ATA or ATAPI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Load the taskfile for 16bit non-True IDE only. The device_addr is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * not loaded, we do this as part of octeon_cf_exec_command16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void octeon_cf_tf_load16(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* The base of the registers is at ioaddr.data_addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) void __iomem *base = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (tf->ctl != ap->last_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __raw_writew(tf->hob_feature << 8, base + 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tf->hob_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tf->hob_nsect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tf->hob_lbal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tf->hob_lbam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) tf->hob_lbah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (is_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __raw_writew(tf->feature << 8, base + 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __raw_writew(tf->nsect | tf->lbal << 8, base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __raw_writew(tf->lbam | tf->lbah << 8, base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) tf->feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tf->nsect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tf->lbal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tf->lbam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tf->lbah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* There is only one device, do nothing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Issue ATA command to host controller. The device_addr is also sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * as it must be written in a combined write with the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void octeon_cf_exec_command16(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) const struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* The base of the registers is at ioaddr.data_addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) void __iomem *base = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u16 blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (tf->flags & ATA_TFLAG_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) VPRINTK("device 0x%X\n", tf->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) blob = tf->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) blob = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) blob |= (tf->command << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __raw_writew(blob, base + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void octeon_cf_ata_port_noaction(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct octeon_cf_port *cf_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cf_port = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* issue r/w command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) qc->cursg = qc->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cf_port->dma_finished = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ap->ops->sff_exec_command(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * Start a DMA transfer that was already setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * @qc: Information about the DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct octeon_cf_port *cf_port = qc->ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) union cvmx_mio_boot_dma_intx mio_boot_dma_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) VPRINTK("%d scatterlists\n", qc->n_elem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Get the scatter list entry we need to DMA into */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sg = qc->cursg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) BUG_ON(!sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Clear the DMA complete status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) mio_boot_dma_int.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mio_boot_dma_int.s.done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Enable the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Set the direction of the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mio_boot_dma_cfg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mio_boot_dma_cfg.s.endian = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mio_boot_dma_cfg.s.en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Don't stop the DMA if the device deasserts DMARQ. Many
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * compact flashes deassert DMARQ for a short time between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * sectors. Instead of stopping and restarting the DMA, we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * let the hardware do it. If the DMA is really stopped early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * due to an error condition, a later timeout will force us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mio_boot_dma_cfg.s.clr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Size is specified in 16bit words and minus one notation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* We need to swap the high and low bytes of every 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mio_boot_dma_cfg.s.swap8 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mio_boot_dma_cfg.s.adr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) VPRINTK("%s %d bytes address=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) (void *)(unsigned long)mio_boot_dma_cfg.s.adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * spin_lock_irqsave(host lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct ata_eh_info *ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct octeon_cf_port *cf_port = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) union cvmx_mio_boot_dma_cfgx dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) union cvmx_mio_boot_dma_intx dma_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) VPRINTK("ata%u: protocol %d task_state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ap->print_id, qc->tf.protocol, ap->hsm_task_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ap->hsm_task_state != HSM_ST_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (dma_cfg.s.size != 0xfffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Error, the transfer was not complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) qc->err_mask |= AC_ERR_HOST_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ap->hsm_task_state = HSM_ST_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Stop and clear the dma engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dma_cfg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dma_cfg.s.size = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Disable the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dma_int.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Clear the DMA complete status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dma_int.s.done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) status = ap->ops->sff_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ata_sff_hsm_move(ap, qc, status, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ata_ehi_push_desc(ehi, "DMA stat 0x%x", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Check if any queued commands have more DMAs, if so start the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * transfer, else do end of transfer handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct ata_host *host = dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct octeon_cf_port *cf_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) DPRINTK("ENTER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) for (i = 0; i < host->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) union cvmx_mio_boot_dma_intx dma_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) union cvmx_mio_boot_dma_cfgx dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ap = host->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) cf_port = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) qc = ata_qc_from_tag(ap, ap->link.active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (dma_int.s.done && !dma_cfg.s.en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!sg_is_last(qc->cursg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) qc->cursg = sg_next(qc->cursg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) octeon_cf_dma_start(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) cf_port->dma_finished = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!cf_port->dma_finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) status = ioread8(ap->ioaddr.altstatus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (status & (ATA_BUSY | ATA_DRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * We are busy, try to handle it later. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * is the DMA finished interrupt, and it could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * take a little while for the card to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * ready for more commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Clear DMA irq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dma_int.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dma_int.s.done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cvmx_write_csr(cf_port->dma_base + DMA_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dma_int.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) hrtimer_start_range_ns(&cf_port->delayed_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) OCTEON_CF_BUSY_POLL_INTERVAL / 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) handled |= octeon_cf_dma_finished(ap, qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DPRINTK("EXIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct octeon_cf_port *cf_port = container_of(hrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct octeon_cf_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) delayed_finish);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct ata_port *ap = cf_port->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct ata_host *host = ap->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct ata_queued_cmd *qc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) enum hrtimer_restart rv = HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * If the port is not waiting for completion, it must have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * handled it previously. The hsm_task_state is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * protected by host->lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) status = ioread8(ap->ioaddr.altstatus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (status & (ATA_BUSY | ATA_DRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Still busy, try again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) hrtimer_forward_now(hrt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) rv = HRTIMER_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) qc = ata_qc_from_tag(ap, ap->link.active_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) octeon_cf_dma_finished(ap, qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void octeon_cf_dev_config(struct ata_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * A maximum of 2^20 - 1 16 bit transfers are possible with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * the bootbus DMA. So we need to throttle max_sectors to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * (2^12 - 1 == 4095) to assure that this can never happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev->max_sectors = min(dev->max_sectors, 4095U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * We don't do ATAPI DMA so return 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) switch (qc->tf.protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case ATA_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) octeon_cf_dma_setup(qc); /* set up dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) octeon_cf_dma_start(qc); /* initiate dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ap->hsm_task_state = HSM_ST_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case ATAPI_PROT_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_err(ap->dev, "Error, ATAPI not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static struct ata_port_operations octeon_cf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .check_atapi_dma = octeon_cf_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .qc_prep = ata_noop_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .qc_issue = octeon_cf_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .sff_dev_select = octeon_cf_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .sff_irq_on = octeon_cf_ata_port_noaction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .sff_irq_clear = octeon_cf_ata_port_noaction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .set_piomode = octeon_cf_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .set_dmamode = octeon_cf_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .dev_config = octeon_cf_dev_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int octeon_cf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct resource *res_cs0, *res_cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) bool is_16bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) const __be32 *cs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct property *reg_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int n_addr, n_size, reg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) void __iomem *cs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) void __iomem *cs1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) irq_handler_t irq_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct octeon_cf_port *cf_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int rv = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (node == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!cf_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) is_16bit = (bus_width == 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) is_16bit = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) n_addr = of_n_addr_cells(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) n_size = of_n_size_cells(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) reg_prop = of_find_property(node, "reg", ®_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (!reg_prop || reg_len < sizeof(__be32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) cs_num = reg_prop->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) cf_port->cs0 = be32_to_cpup(cs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (cf_port->is_true_ide) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct device_node *dma_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dma_node = of_parse_phandle(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "cavium,dma-engine-handle", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (dma_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct platform_device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dma_dev = of_find_device_by_node(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (dma_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct resource *res_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!res_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) of_node_put(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) resource_size(res_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!cf_port->dma_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) of_node_put(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) i = platform_get_irq(dma_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (i > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) irq = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) irq_handler = octeon_cf_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) of_node_put(dma_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!res_cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) cs1 = devm_ioremap(&pdev->dev, res_cs1->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) resource_size(res_cs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (reg_len < (n_addr + n_size + 1) * sizeof(__be32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) cs_num += n_addr + n_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) cf_port->cs1 = be32_to_cpup(cs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!res_cs0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cs0 = devm_ioremap(&pdev->dev, res_cs0->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) resource_size(res_cs0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (!cs0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ap->private_data = cf_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) pdev->dev.platform_data = cf_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) cf_port->ap = ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ap->ops = &octeon_cf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ap->pio_mask = ATA_PIO6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!is_16bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) base = cs0 + 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ap->ioaddr.cmd_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ata_sff_std_ports(&ap->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ap->ioaddr.altstatus_addr = base + 0xe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ap->ioaddr.ctl_addr = base + 0xe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) } else if (cf_port->is_true_ide) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) base = cs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ap->mwdma_mask = enable_dma ? ATA_MWDMA4 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* True IDE mode needs a timer to poll for not-busy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) cf_port->delayed_finish.function = octeon_cf_delayed_finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* 16 bit but not True IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) base = cs0 + 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) octeon_cf_ops.softreset = octeon_cf_softreset16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) octeon_cf_ops.sff_check_status = octeon_cf_check_status16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ap->ioaddr.data_addr = base + ATA_REG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ap->ioaddr.nsect_addr = base + ATA_REG_NSECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ap->ioaddr.lbal_addr = base + ATA_REG_LBAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ap->ioaddr.ctl_addr = base + 0xe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ap->ioaddr.altstatus_addr = base + 0xe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) cf_port->c0 = ap->ioaddr.ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (rv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) is_16bit ? 16 : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) cf_port->is_true_ide ? ", True IDE" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return ata_host_activate(host, irq, irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) IRQF_SHARED, &octeon_cf_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static void octeon_cf_shutdown(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) union cvmx_mio_boot_dma_cfgx dma_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) union cvmx_mio_boot_dma_intx dma_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct octeon_cf_port *cf_port = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (cf_port->dma_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Stop and clear the dma engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dma_cfg.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dma_cfg.s.size = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* Disable the interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dma_int.u64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Clear the DMA complete status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dma_int.s.done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) __raw_writeb(0, cf_port->c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) __raw_writeb(ATA_SRST, cf_port->c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) __raw_writeb(0, cf_port->c0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const struct of_device_id octeon_cf_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .compatible = "cavium,ebt3000-compact-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) MODULE_DEVICE_TABLE(of, octeon_cf_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static struct platform_driver octeon_cf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .probe = octeon_cf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .of_match_table = octeon_cf_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .shutdown = octeon_cf_shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int __init octeon_cf_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return platform_driver_register(&octeon_cf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) MODULE_ALIAS("platform:" DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) module_init(octeon_cf_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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