Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *    pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	(C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *    This is a fairly generic MWDMA controller. It has some limitations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *    as it requires timing reloads on PIO/DMA transitions but it is otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *    fairly well designed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *    This driver assumes the firmware has left the chip in a valid ST506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *    compliant state, either legacy IRQ 14/15 or native INTA shared. You
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *    may need to add platform code if your system fails to do this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *    The same cell appears in the 87560 controller used by some PARISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *    systems. This has its own special mountain of errata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *    TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *	Get someone to test on SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *	Implement lazy pio/dma switching for better performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *	8bit shared timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *	See if we need to kill the FIFO for ATAPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DRV_NAME	"pata_ns87415"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DRV_VERSION	"0.0.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *	ns87415_set_mode - Initialize host controller mode timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *	@ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *	@adev: Device whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *	@mode: Mode to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *	Program the mode registers for this controller, channel and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *	device. Because the chip is quite an old design we have to do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *	for PIO/DMA switches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *	LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *	None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int unit		= 2 * ap->port_no + adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int timing		= 0x44 + 2 * unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned long T		= 1000000000 / 33333;	/* PCI clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u16 clocking;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u8 iordy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* Timing register format is 17 - low nybble read timing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	   the high nybble being 16 - x for recovery time in PCI clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ata_timing_compute(adev, adev->pio_mode, &t, T, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	clocking = 17 - clamp_val(t.active, 2, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  	/* Use the same timing for read and write bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	clocking |= (clocking << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	pci_write_config_word(dev, timing, clocking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* Set the IORDY enable versus DMA enable on or off properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	pci_read_config_byte(dev, 0x42, &iordy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	iordy &= ~(1 << (4 + unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		iordy |= (1 << (4 + unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* Paranoia: We shouldn't ever get here with busy write buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	   but if so wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	pci_read_config_byte(dev, 0x43, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	while (status & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		pci_read_config_byte(dev, 0x43, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* Flip the IORDY/DMA bits now we are sure the write buffers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	   clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	pci_write_config_byte(dev, 0x42, iordy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* TODO: Set byte 54 command timing to the best 8bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	   mode shared by all four devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  *	ns87415_set_piomode - Initialize host controller PATA PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *	@ap: Port whose timings we are configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *	@adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *	Set PIO mode for device, in host controller PCI config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *	LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  *	None (inherited from caller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ns87415_set_mode(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *	ns87415_bmdma_setup		-	Set up DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  *	@qc: Command block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *	Set up for bus masterng DMA. We have to do this ourselves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *	rather than use the helper due to a chip erratum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void ns87415_bmdma_setup(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8 dmactl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* load PRD table addr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	mb();	/* make sure PRD table writes are visible to controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* specify data direction, triple-check start bit is clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Due to an erratum we need to write these bits to the wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	   place - which does save us an I/O bizarrely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	dmactl |= ATA_DMA_INTR | ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (!rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		dmactl |= ATA_DMA_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* issue r/w command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ap->ops->sff_exec_command(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  *	ns87415_bmdma_start		-	Begin DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *	@qc: Command block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *	Switch the timings for the chip and set up for a DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  *	before the DMA burst begins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  *	FIXME: We should do lazy switching on bmdma_start versus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *	ata_pio_data_xfer for better performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void ns87415_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ata_bmdma_start(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *	ns87415_bmdma_stop		-	End DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *	@qc: Command block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *	End DMA mode and switch the controller back into PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void ns87415_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ata_bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *	ns87415_irq_clear		-	Clear interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  *	@ap: Channel to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  *	Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  *	error bits) are reset by writing to register 00 or 08.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void ns87415_irq_clear(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	void __iomem *mmio = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			mmio + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  *	ns87415_check_atapi_dma		-	ATAPI DMA filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  *	@qc: Command block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  *	Disable ATAPI DMA (for now). We may be able to do DMA if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *	kill the prefetching. This isn't clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #if defined(CONFIG_SUPERIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * which use the integrated NS87514 cell for CD-ROM support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * i.e we have to support for CD-ROM installs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * See drivers/parisc/superio.c for more gory details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * Workarounds taken from drivers/ide/pci/ns87415.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #include <asm/superio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SUPERIO_IDE_MAX_RETRIES 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  *	ns87560_read_buggy	-	workaround buggy Super I/O chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  *	@port: Port to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  *	Work around chipset problems in the 87560 SuperIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static u8 ns87560_read_buggy(void __iomem *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int retries = SUPERIO_IDE_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		tmp = ioread8(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (tmp != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	} while(retries-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  *	ns87560_check_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  *	@ap: channel to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  *	Return the status of the channel working around the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  *	87560 flaws.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static u8 ns87560_check_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return ns87560_read_buggy(ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  *	ns87560_tf_read - input device's ATA taskfile shadow registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  *	@ap: Port from which input is read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *	@tf: ATA taskfile register set for storing input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  *	Reads ATA taskfile registers for currently-selected device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  *	into @tf. Work around the 87560 bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  *	LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *	Inherited from caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	tf->command = ns87560_check_status(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	tf->feature = ioread8(ioaddr->error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	tf->nsect = ioread8(ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	tf->lbal = ioread8(ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	tf->lbam = ioread8(ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	tf->lbah = ioread8(ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	tf->device = ns87560_read_buggy(ioaddr->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (tf->flags & ATA_TFLAG_LBA48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		tf->hob_feature = ioread8(ioaddr->error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		tf->hob_nsect = ioread8(ioaddr->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		tf->hob_lbal = ioread8(ioaddr->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		tf->hob_lbam = ioread8(ioaddr->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		tf->hob_lbah = ioread8(ioaddr->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		iowrite8(tf->ctl, ioaddr->ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ap->last_ctl = tf->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  *	ns87560_bmdma_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  *	@ap: channel to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  *	Return the DMA status of the channel working around the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  *	87560 flaws.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static u8 ns87560_bmdma_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #endif		/* 87560 SuperIO Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct ata_port_operations ns87415_pata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.inherits		= &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.check_atapi_dma	= ns87415_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.bmdma_setup		= ns87415_bmdma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.bmdma_start		= ns87415_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.bmdma_stop		= ns87415_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.sff_irq_clear		= ns87415_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.cable_detect		= ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.set_piomode		= ns87415_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #if defined(CONFIG_SUPERIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct ata_port_operations ns87560_pata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.inherits		= &ns87415_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.sff_tf_read		= ns87560_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.sff_check_status	= ns87560_check_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.bmdma_status		= ns87560_bmdma_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct scsi_host_template ns87415_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void ns87415_fixup(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/* Select 512 byte sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	pci_write_config_byte(pdev, 0x55, 0xEE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	/* Select PIO0 8bit clocking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	pci_write_config_byte(pdev, 0x54, 0xB7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  *	ns87415_init_one - Register 87415 ATA PCI device with kernel services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  *	@pdev: PCI device to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  *	@ent: Entry in ns87415_pci_tbl matching with @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  *	Called from kernel PCI layer.  We probe for combined mode (sigh),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)  *	and then hand over control to libata, for it to do the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)  *	LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)  *	Inherited from PCI layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)  *	RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)  *	Zero on success, or -ERRNO value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.flags		= ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.port_ops	= &ns87415_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #if defined(CONFIG_SUPERIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	static const struct ata_port_info info87560 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.flags		= ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.port_ops	= &ns87560_pata_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (PCI_SLOT(pdev->devfn) == 0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		ppi[0] = &info87560;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	ns87415_fixup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct pci_device_id ns87415_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	{ }	/* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int ns87415_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	ns87415_fixup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct pci_driver ns87415_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.name			= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.id_table		= ns87415_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.probe			= ns87415_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.remove			= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.suspend		= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.resume			= ns87415_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) module_pci_driver(ns87415_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_VERSION(DRV_VERSION);