Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * pata_ninja32.c 	- Ninja32 PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *			  (C) 2007 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Note: The controller like many controllers has shared timings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * in the dma_stop function. Thus we actually don't need a set_dmamode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * method as the PIO method is always called and will set the right PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * timing parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * driver and the extensive analysis done by the BSD developers, notably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * ITOH Yasufumi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *	Base + 0x00 IRQ Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *	Base + 0x01 IRQ control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *	Base + 0x02 Chipset control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *	Base + 0x03 Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *	Base + 0x04 VDMA and reset control + wait bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *	Base + 0x08 BMIMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *	Base + 0x0C DMA Length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *	Base + 0x10 Taskfile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *	Base + 0x18 BMDMA Status ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *	Base + 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	Base + 0x1D Bus master control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *		bit 0 = enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *		bit 1 = 0 write/1 read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *		bit 2 = 1 sgtable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *		bit 3 = go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *		bit 4-6 wait bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *		bit 7 = done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *	Base + 0x1E AltStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *	Base + 0x1F timing register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DRV_NAME "pata_ninja32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DRV_VERSION "0.1.5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *	ninja32_set_piomode	-	set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *	@adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *	Called to do the PIO mode setup. Our timing registers are shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *	but we want to set the PIO timing by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	static u16 pio_timing[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		0xd6, 0x85, 0x44, 0x33, 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		 ap->ioaddr.bmdma_addr + 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ap->private_data = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct ata_device *adev = &ap->link.device[device];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (ap->private_data != adev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		ata_sff_dev_select(ap, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		ninja32_set_piomode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static struct scsi_host_template ninja32_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct ata_port_operations ninja32_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.inherits	= &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.sff_dev_select = ninja32_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.cable_detect	= ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.set_piomode	= ninja32_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.sff_data_xfer	= ata_sff_data_xfer32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void ninja32_program(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	iowrite8(0x05, base + 0x01);	/* Enable interrupt lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	iowrite8(0xBE, base + 0x02);	/* Burst, ?? setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	iowrite8(0x01, base + 0x03);	/* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	iowrite8(0x20, base + 0x04);	/* WAIT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	iowrite8(0x8f, base + 0x05);	/* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	iowrite8(0xa4, base + 0x1c);	/* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	iowrite8(0x83, base + 0x1d);	/* BMDMA control: WAIT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	host = ata_host_alloc(&dev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* Set up the PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	rc = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (rc == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		pcim_pin_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	host->iomap = pcim_iomap_table(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	rc = dma_set_mask_and_coherent(&dev->dev, ATA_DMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Set up the register mappings. We use the I/O mapping as only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	   older chips also have MMIO on BAR 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	base = host->iomap[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ap->ops = &ninja32_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ap->flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ap->ioaddr.cmd_addr = base + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ap->ioaddr.ctl_addr = base + 0x1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ap->ioaddr.altstatus_addr = base + 0x1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ap->ioaddr.bmdma_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ata_sff_std_ports(&ap->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ninja32_program(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* FIXME: Should we disable them at remove ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				 IRQF_SHARED, &ninja32_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int ninja32_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ninja32_program(host->iomap[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct pci_device_id ninja32[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct pci_driver ninja32_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.name 		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.id_table	= ninja32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.probe 		= ninja32_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.resume		= ninja32_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) module_pci_driver(ninja32_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_DEVICE_TABLE(pci, ninja32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_VERSION(DRV_VERSION);