Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * pata_mpiix.c 	- Intel MPIIX PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *			  (C) 2005-2006 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * The MPIIX is different enough to the PIIX4 and friends that we give it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * a separate driver. The old ide/pci code handles this by just not tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * MPIIX at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * The MPIIX also differs in another important way from the majority of PIIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * devices. The chip is a bridge (pardon the pun) between the old world of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * IDE controller is not decoded in PCI space and the chip does not claim to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * be IDE class PCI. This requires slightly non-standard probe logic compared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * with PCI IDE and also that we do not disable the device when our driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * unloaded (as it has many other functions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * The driver consciously keeps this logic internally to avoid pushing quirky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * PATA history into the clean libata layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * hard disk present this driver will not detect it. This is not a bug. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * configuration the secondary port of the MPIIX is disabled and the addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * to operate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DRV_NAME "pata_mpiix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DRV_VERSION "0.7.7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	IDETIM = 0x6C,		/* IDE control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	IORDY = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	PPE = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	FTIM = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	ENABLED = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	SECONDARY = (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *	mpiix_set_piomode	-	set initial PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *	@ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *	@adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *	Called to do the PIO mode setup. The MPIIX allows us to program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *	IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *	prefetching or IORDY are used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *	This would get very ugly because we can only program timing for one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *	device at a time, the other gets PIO0. Fortunately libata calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *	our qc_issue command before a command is issued so we can flip the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *	timings back and forth to reduce the pain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u16 idetim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	static const	 /* ISP  RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8 timings[][2]	= { { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			    { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			    { 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			    { 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			    { 2, 3 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	pci_read_config_word(pdev, IDETIM, &idetim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* Mask the IORDY/TIME/PPE for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (adev->class == ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		control |= PPE;		/* Enable prefetch/posting for disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (ata_pio_need_iordy(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		control |= IORDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (pio > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		control |= FTIM;	/* This drive is on the fast timing bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Mask out timing and clear both TIME bank selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	idetim &= 0xCCEE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	idetim &= ~(0x07  << (4 * adev->devno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	idetim |= control << (4 * adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	pci_write_config_word(pdev, IDETIM, idetim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* We use ap->private_data as a pointer to the device currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	   loaded for timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ap->private_data = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *	mpiix_qc_issue		-	command issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  *	@qc: command pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *	Called when the libata layer is about to issue a command. We wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *	this interface so that we can load the correct ATA timings if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *	necessary. Our logic also clears TIME0/TIME1 for the other device so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *	that, even if we get this wrong, cycles to the other device will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *	be made PIO0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* If modes have been configured and the channel data is not loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	   then load it. We have to check if pio_mode is set as the core code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	   does not set adev->pio_mode to XFER_PIO_0 while probing as would be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	   logical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (adev->pio_mode && adev != ap->private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		mpiix_set_piomode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct scsi_host_template mpiix_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct ata_port_operations mpiix_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.inherits	= &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.qc_issue	= mpiix_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.cable_detect	= ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.set_piomode	= mpiix_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.prereset	= mpiix_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.sff_data_xfer	= ata_sff_data_xfer32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* Single threaded by the PCI probe logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	void __iomem *cmd_addr, *ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u16 idetim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int cmd, ctl, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ata_print_version_once(&dev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	host = ata_host_alloc(&dev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* MPIIX has many functions which can be turned on or off according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	   to other devices present. Make sure IDE is enabled before we try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	   and use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pci_read_config_word(dev, IDETIM, &idetim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!(idetim & ENABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* See if it's primary or secondary channel... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (!(idetim & SECONDARY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		cmd = 0x1F0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		ctl = 0x3F6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		irq = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		cmd = 0x170;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		ctl = 0x376;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		irq = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (!cmd_addr || !ctl_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* We do our own plumbing to avoid leaking special cases for whacko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	   ancient hardware into the core code. There are two issues to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	   worry about.  #1 The chip is a bridge so if in legacy mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	   without BARs set fools the setup.  #2 If you pci_disable_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	   the MPIIX your box goes castors up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	ap->ops = &mpiix_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ap->flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ap->ioaddr.cmd_addr = cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ap->ioaddr.ctl_addr = ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ap->ioaddr.altstatus_addr = ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* Let libata fill in the port details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ata_sff_std_ports(&ap->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* activate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				 &mpiix_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct pci_device_id mpiix[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct pci_driver mpiix_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.name 		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.id_table	= mpiix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.probe 		= mpiix_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.remove		= ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.suspend	= ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.resume		= ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) module_pci_driver(mpiix_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_DEVICE_TABLE(pci, mpiix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_VERSION(DRV_VERSION);