^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/ata/pata_mpc52xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * libata driver for the Freescale MPC52xx on-chip IDE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Domen Puncer and Tim Yamin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mpc52xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/fsl/bestcomm/bestcomm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/fsl/bestcomm/bestcomm_priv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/fsl/bestcomm/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRV_NAME "mpc52xx_ata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Private structures used by the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mpc52xx_ata_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 pio1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 pio2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 mdma1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 mdma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 udma1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 udma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 udma3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 udma4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 udma5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int using_udma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct mpc52xx_ata_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int ipb_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mpc52xx_ata __iomem *ata_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) phys_addr_t ata_regs_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ata_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct mpc52xx_ata_timings timings[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int csel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct bcom_task *dmatsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const struct udmaspec *udmaspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct mdmaspec *mdmaspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int mpc52xx_ata_dma_last_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int waiting_for_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* ATAPI-4 PIO specs (in ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const u16 ataspec_t0[5] = {600, 383, 240, 180, 120};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const u16 ataspec_t1[5] = { 70, 50, 30, 30, 25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const u16 ataspec_t2_8[5] = {290, 290, 290, 80, 70};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const u16 ataspec_t2_16[5] = {165, 125, 100, 80, 70};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const u16 ataspec_t2i[5] = { 0, 0, 0, 70, 25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const u16 ataspec_t4[5] = { 30, 20, 15, 10, 10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const u16 ataspec_ta[5] = { 35, 35, 35, 35, 35};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* ATAPI-4 MDMA specs (in clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mdmaspec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 t0M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 tj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 tkw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 tn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct mdmaspec mdmaspec66[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .t0M = 32, .td = 15, .th = 2, .tj = 2, .tkw = 15, .tm = 4, .tn = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .t0M = 10, .td = 6, .th = 1, .tj = 1, .tkw = 4, .tm = 2, .tn = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .t0M = 8, .td = 5, .th = 1, .tj = 1, .tkw = 2, .tm = 2, .tn = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct mdmaspec mdmaspec132[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .t0M = 64, .td = 29, .th = 3, .tj = 3, .tkw = 29, .tm = 7, .tn = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .t0M = 20, .td = 11, .th = 2, .tj = 1, .tkw = 7, .tm = 4, .tn = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .t0M = 16, .td = 10, .th = 2, .tj = 1, .tkw = 4, .tm = 4, .tn = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* ATAPI-4 UDMA specs (in clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct udmaspec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 tcyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 t2cyc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 tds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 tdh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 tdvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 tdvh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 tfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 tli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 tmli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 taz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 tzah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 tenv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 tsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 trfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 trp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 tack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 tss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct udmaspec udmaspec66[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { .tcyc = 8, .t2cyc = 16, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .tfs = 16, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .tsr = 3, .trfs = 5, .trp = 11, .tack = 2, .tss = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .tcyc = 5, .t2cyc = 11, .tds = 1, .tdh = 1, .tdvs = 4, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .tfs = 14, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .tsr = 2, .trfs = 5, .trp = 9, .tack = 2, .tss = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .tcyc = 4, .t2cyc = 8, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .tfs = 12, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 2, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .tfs = 9, .tli = 7, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .tcyc = 2, .t2cyc = 4, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .tfs = 8, .tli = 8, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .tcyc = 2, .t2cyc = 2, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .tfs = 6, .tli = 5, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .tsr = 2, .trfs = 4, .trp = 6, .tack = 2, .tss = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct udmaspec udmaspec132[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .tcyc = 15, .t2cyc = 31, .tds = 2, .tdh = 1, .tdvs = 10, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .tfs = 30, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .tsr = 7, .trfs = 10, .trp = 22, .tack = 3, .tss = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .tcyc = 10, .t2cyc = 21, .tds = 2, .tdh = 1, .tdvs = 7, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .tfs = 27, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .tsr = 4, .trfs = 10, .trp = 17, .tack = 3, .tss = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .tcyc = 6, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .tfs = 23, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .tcyc = 7, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .tfs = 15, .tli = 13, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .tcyc = 2, .t2cyc = 5, .tds = 0, .tdh = 0, .tdvs = 1, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .tfs = 16, .tli = 14, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .tsr = 2, .trfs = 7, .trp = 13, .tack = 2, .tss = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .tfs = 12, .tli = 10, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .tsr = 3, .trfs = 7, .trp = 12, .tack = 3, .tss = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Bit definitions inside the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MPC52xx_ATA_FIFOSTAT_ERROR 0x40 /* FIFO Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MAX_DMA_BUFFERS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MAX_DMA_BUFFER_SIZE 0x20000u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Structure of the hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mpc52xx_ata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Host interface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 config; /* ATA + 0x00 Host configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 host_status; /* ATA + 0x04 Host controller status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 pio1; /* ATA + 0x08 PIO Timing 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 pio2; /* ATA + 0x0c PIO Timing 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 share_cnt; /* ATA + 0x2c ATA share counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 reserved0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* FIFO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 fifo_data; /* ATA + 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 fifo_status_frame; /* ATA + 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 fifo_status; /* ATA + 0x41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u16 reserved7[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 fifo_control; /* ATA + 0x44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 reserved8[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 fifo_alarm; /* ATA + 0x4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 reserved9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 fifo_rdp; /* ATA + 0x4e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 reserved10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 fifo_wrp; /* ATA + 0x52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 reserved11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 fifo_lfrdp; /* ATA + 0x56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 reserved12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 fifo_lfwrp; /* ATA + 0x5a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Drive TaskFile registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 reserved13[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u16 tf_data; /* ATA + 0x60 TASKFILE Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u16 reserved14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 reserved15[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 reserved16[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 reserved17[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 reserved18[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 reserved19[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 reserved20[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 reserved21[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Aux fns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* MPC52xx low level hw control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct mpc52xx_ata_timings *timing = &priv->timings[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int ipb_period = priv->ipb_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 t0, t1, t2_8, t2_16, t2i, t4, ta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if ((pio < 0) || (pio > 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct mpc52xx_ata_timings *t = &priv->timings[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) const struct mdmaspec *s = &priv->mdmaspec[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (speed < 0 || speed > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) t->mdma1 = ((u32)s->t0M << 24) | ((u32)s->td << 16) | ((u32)s->tkw << 8) | s->tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) t->mdma2 = ((u32)s->th << 24) | ((u32)s->tj << 16) | ((u32)s->tn << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) t->using_udma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct mpc52xx_ata_timings *t = &priv->timings[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const struct udmaspec *s = &priv->udmaspec[speed];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (speed < 0 || speed > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) t->udma1 = ((u32)s->t2cyc << 24) | ((u32)s->tcyc << 16) | ((u32)s->tds << 8) | s->tdh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) t->udma2 = ((u32)s->tdvs << 24) | ((u32)s->tdvh << 16) | ((u32)s->tfs << 8) | s->tli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) t->udma3 = ((u32)s->tmli << 24) | ((u32)s->taz << 16) | ((u32)s->tenv << 8) | s->tsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) t->udma4 = ((u32)s->tss << 24) | ((u32)s->trfs << 16) | ((u32)s->trp << 8) | s->tack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) t->udma5 = (u32)s->tzah << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) t->using_udma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct mpc52xx_ata __iomem *regs = priv->ata_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct mpc52xx_ata_timings *timing = &priv->timings[device];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) out_be32(®s->pio1, timing->pio1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) out_be32(®s->pio2, timing->pio2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) out_be32(®s->mdma1, timing->mdma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) out_be32(®s->mdma2, timing->mdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) out_be32(®s->udma1, timing->udma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) out_be32(®s->udma2, timing->udma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) out_be32(®s->udma3, timing->udma3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) out_be32(®s->udma4, timing->udma4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) out_be32(®s->udma5, timing->udma5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) priv->csel = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct mpc52xx_ata __iomem *regs = priv->ata_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int tslot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Clear share_cnt (all sample code do this ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) out_be32(®s->share_cnt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Configure and reset host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) out_be32(®s->config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MPC52xx_ATA_HOSTCONF_IE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MPC52xx_ATA_HOSTCONF_IORDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MPC52xx_ATA_HOSTCONF_SMR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MPC52xx_ATA_HOSTCONF_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) out_be32(®s->config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MPC52xx_ATA_HOSTCONF_IE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MPC52xx_ATA_HOSTCONF_IORDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Set the time slot to 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) out_be32(®s->share_cnt, tslot << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Init timings to PIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mpc52xx_ata_compute_pio_timings(priv, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mpc52xx_ata_compute_pio_timings(priv, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mpc52xx_ata_apply_timings(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* libata driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int pio, rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(ap->dev, "error: invalid PIO mode: %d\n", pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mpc52xx_ata_apply_timings(priv, adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mpc52xx_ata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (adev->dma_mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int dma = adev->dma_mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rv = mpc52xx_ata_compute_udma_timings(priv, adev->devno, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int dma = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rv = mpc52xx_ata_compute_mdma_timings(priv, adev->devno, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_alert(ap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "Trying to select invalid DMA mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mpc52xx_ata_apply_timings(priv, adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (device != priv->csel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mpc52xx_ata_apply_timings(priv, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ata_sff_dev_select(ap, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mpc52xx_ata_build_dmatable(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct bcom_ata_bd *bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) bcom_ata_rx_prepare(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) bcom_ata_tx_prepare(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dma_addr_t cur_addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 cur_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) while (cur_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int tc = min(cur_len, MAX_DMA_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) bd = (struct bcom_ata_bd *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) bcom_prepare_next_buffer(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) bd->status = tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bd->src_pa = (__force u32) priv->ata_regs_pa +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) offsetof(struct mpc52xx_ata, fifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bd->dst_pa = (__force u32) cur_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bd->status = tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bd->src_pa = (__force u32) cur_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) bd->dst_pa = (__force u32) priv->ata_regs_pa +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) offsetof(struct mpc52xx_ata, fifo_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bcom_submit_next_buffer(priv->dmatsk, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cur_addr += tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cur_len -= tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (count > MAX_DMA_BUFFERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_alert(ap->dev, "dma table"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto use_pio_instead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) use_pio_instead:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) bcom_ata_reset_bd(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mpc52xx_bmdma_setup(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct mpc52xx_ata __iomem *regs = priv->ata_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!mpc52xx_ata_build_dmatable(qc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_alert(ap->dev, "%s: %i, return 1?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Check FIFO is OK... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) __func__, in_8(&priv->ata_regs->fifo_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MPC52xx_ATA_DMAMODE_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Setup FIFO if direction changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (priv->mpc52xx_ata_dma_last_write != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) priv->mpc52xx_ata_dma_last_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Configure FIFO with granularity to 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) out_8(®s->fifo_control, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) out_be16(®s->fifo_alarm, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Set FIFO Reset bit (FR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) out_8(®s->dma_mode, MPC52xx_ATA_DMAMODE_FR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Setup FIFO if direction changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (priv->mpc52xx_ata_dma_last_write != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) priv->mpc52xx_ata_dma_last_write = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Configure FIFO with granularity to 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) out_8(®s->fifo_control, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) out_be16(®s->fifo_alarm, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (priv->timings[qc->dev->devno].using_udma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dma_mode |= MPC52xx_ATA_DMAMODE_UDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) out_8(®s->dma_mode, dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) priv->waiting_for_dma = ATA_DMA_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ap->ops->sff_exec_command(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mpc52xx_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bcom_set_task_auto_start(priv->dmatsk->tasknum, priv->dmatsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) bcom_enable(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mpc52xx_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) bcom_disable(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bcom_ata_reset_bd(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) priv->waiting_for_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Check FIFO is OK... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) __func__, in_8(&priv->ata_regs->fifo_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mpc52xx_bmdma_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct mpc52xx_ata_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Check FIFO is OK... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) __func__, in_8(&priv->ata_regs->fifo_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return priv->waiting_for_dma | ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return priv->waiting_for_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mpc52xx_ata_task_irq(int irq, void *vpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct mpc52xx_ata_priv *priv = vpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) while (bcom_buffer_done(priv->dmatsk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) bcom_retrieve_buffer(priv->dmatsk, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) priv->waiting_for_dma |= ATA_DMA_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct scsi_host_template mpc52xx_ata_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct ata_port_operations mpc52xx_ata_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .sff_dev_select = mpc52xx_ata_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .set_piomode = mpc52xx_ata_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .set_dmamode = mpc52xx_ata_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .bmdma_setup = mpc52xx_bmdma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .bmdma_start = mpc52xx_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .bmdma_stop = mpc52xx_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .bmdma_status = mpc52xx_bmdma_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .qc_prep = ata_noop_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int mpc52xx_ata_init_one(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct mpc52xx_ata_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned long raw_ata_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int mwdma_mask, int udma_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct ata_ioports *aio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) host = ata_host_alloc(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ap->flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ap->mwdma_mask = mwdma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ap->udma_mask = udma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ap->ops = &mpc52xx_ata_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) host->private_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) aio = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) aio->cmd_addr = NULL; /* Don't have a classic reg block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) aio->altstatus_addr = &priv->ata_regs->tf_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) aio->ctl_addr = &priv->ata_regs->tf_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) aio->data_addr = &priv->ata_regs->tf_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) aio->error_addr = &priv->ata_regs->tf_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) aio->feature_addr = &priv->ata_regs->tf_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) aio->nsect_addr = &priv->ata_regs->tf_sec_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) aio->lbal_addr = &priv->ata_regs->tf_sec_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) aio->lbam_addr = &priv->ata_regs->tf_cyl_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) aio->lbah_addr = &priv->ata_regs->tf_cyl_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) aio->device_addr = &priv->ata_regs->tf_dev_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) aio->status_addr = &priv->ata_regs->tf_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) aio->command_addr = &priv->ata_regs->tf_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* activate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ata_host_activate(host, priv->ata_irq, ata_bmdma_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) &mpc52xx_ata_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* OF Platform driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int mpc52xx_ata_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned int ipb_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct resource res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int ata_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct mpc52xx_ata __iomem *ata_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct mpc52xx_ata_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int rv, task_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int mwdma_mask = 0, udma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int proplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct bcom_task *dmatsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Get ipb frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!ipb_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_err(&op->dev, "could not determine IPB bus frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Get device base address from device tree, request the region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * and ioremap it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) rv = of_address_to_resource(op->dev.of_node, 0, &res_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(&op->dev, "could not determine device base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!devm_request_mem_region(&op->dev, res_mem.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) sizeof(*ata_regs), DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(&op->dev, "error requesting register region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ata_regs = devm_ioremap(&op->dev, res_mem.start, sizeof(*ata_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!ata_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(&op->dev, "error mapping device registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * By default, all DMA modes are disabled for the MPC5200. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * boards don't have the required signals routed to make DMA work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Also, the MPC5200B has a silicon bug that causes data corruption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * with UDMA if it is used at the same time as the LocalPlus bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * Instead of trying to guess what modes are usable, check the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * ATA device tree node to find out what DMA modes work on the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * UDMA/MWDMA modes can also be forced by adding "libata.force=<mode>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * to the kernel boot parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * UDMA modes 0, 1 and 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) prop = of_get_property(op->dev.of_node, "mwdma-mode", &proplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if ((prop) && (proplen >= 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) prop = of_get_property(op->dev.of_node, "udma-mode", &proplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if ((prop) && (proplen >= 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ata_irq = irq_of_parse_and_map(op->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ata_irq == NO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_err(&op->dev, "error mapping irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Prepare our private structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rv = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) priv->ipb_period = 1000000000 / (ipb_freq / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) priv->ata_regs = ata_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) priv->ata_regs_pa = res_mem.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) priv->ata_irq = ata_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) priv->csel = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) priv->mpc52xx_ata_dma_last_write = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ipb_freq/1000000 == 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) priv->mdmaspec = mdmaspec66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) priv->udmaspec = udmaspec66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) priv->mdmaspec = mdmaspec132;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) priv->udmaspec = udmaspec132;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Allocate a BestComm task for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dmatsk = bcom_ata_init(MAX_DMA_BUFFERS, MAX_DMA_BUFFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!dmatsk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(&op->dev, "bestcomm initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rv = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) task_irq = bcom_get_task_irq(dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) rv = devm_request_irq(&op->dev, task_irq, &mpc52xx_ata_task_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "ATA task", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(&op->dev, "error requesting DMA IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) priv->dmatsk = dmatsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Init the hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) rv = mpc52xx_ata_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_err(&op->dev, "error initializing hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Register ourselves to libata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mwdma_mask, udma_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_err(&op->dev, "error registering with ATA layer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) irq_dispose_mapping(task_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) bcom_ata_release(dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) irq_dispose_mapping(ata_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mpc52xx_ata_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct ata_host *host = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct mpc52xx_ata_priv *priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int task_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Deregister the ATA interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ata_platform_remove_one(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Clean up DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) task_irq = bcom_get_task_irq(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) irq_dispose_mapping(task_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) bcom_ata_release(priv->dmatsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) irq_dispose_mapping(priv->ata_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct ata_host *host = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return ata_host_suspend(host, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) mpc52xx_ata_resume(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct ata_host *host = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct mpc52xx_ata_priv *priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) rv = mpc52xx_ata_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(host->dev, "error initializing hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct of_device_id mpc52xx_ata_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) { .compatible = "fsl,mpc5200-ata", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) { .compatible = "mpc5200-ata", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static struct platform_driver mpc52xx_ata_of_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .probe = mpc52xx_ata_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .remove = mpc52xx_ata_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .suspend = mpc52xx_ata_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .resume = mpc52xx_ata_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .of_match_table = mpc52xx_ata_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) module_platform_driver(mpc52xx_ata_of_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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