^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Libata based driver for Apple "macio" family of PATA controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some bits and pieces from drivers/ide/ppc/pmac.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #undef DEBUG_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/adb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <scsi/scsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <scsi/scsi_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/macio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/dbdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/pmac_feature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mediabay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef DEBUG_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define dev_dbgdma(dev, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dev_printk(KERN_DEBUG , dev , format , ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define dev_dbgdma(dev, format, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRV_NAME "pata_macio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRV_VERSION "0.9"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Models of macio ATA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) controller_ohare, /* OHare based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) controller_heathrow, /* Heathrow/Paddington */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) controller_kl_ata3, /* KeyLargo ATA-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) controller_kl_ata4, /* KeyLargo ATA-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) controller_un_ata6, /* UniNorth2 ATA-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) controller_k2_ata6, /* K2 ATA-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) controller_sh_ata6, /* Shasta ATA-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const char* macio_ata_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "OHare ATA", /* OHare based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "Heathrow ATA", /* Heathrow/Paddington */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Extra registers, both 32-bit little-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IDE_TIMING_CONFIG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IDE_INTERRUPT 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Kauai (U2) ATA has different register setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IDE_KAUAI_PIO_CONFIG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IDE_KAUAI_ULTRA_CONFIG 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IDE_KAUAI_POLL_CONFIG 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Timing configuration register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* 133Mhz cell, found in shasta.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * See comments about 100 Mhz Uninorth 2...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * weird and I don't now why .. at this stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TR_133_PIOREG_PIO_MASK 0xff000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TR_133_PIOREG_MDMA_MASK 0x00fff800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TR_133_UDMAREG_UDMA_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * controlled like gem or fw. It appears to be an evolution of keylargo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * ATA4 with a timing register extended to 2x32bits registers (one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * It has it's own local feature control register as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * After scratching my mind over the timing values, at least for PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * and MDMA, I think I've figured the format of the timing register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * though I use pre-calculated tables for UDMA as usual...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TR_100_PIO_ADDRSETUP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TR_100_MDMA_MASK 0x00fff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TR_100_MDMA_RECOVERY_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TR_100_MDMA_ACCESS_MASK 0x0003f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TR_100_MDMA_ACCESS_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TR_100_PIO_MASK 0xff000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TR_100_PIO_RECOVERY_MASK 0x00000fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TR_100_PIO_RECOVERY_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TR_100_PIO_ACCESS_MASK 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TR_100_PIO_ACCESS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TR_100_UDMAREG_UDMA_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 40 connector cable and to 4 on 80 connector one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Clock unit is 15ns (66Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 3 Values can be programmed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * - Write data setup, which appears to match the cycle time. They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * also call it DIOW setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * - Ready to pause time (from spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * - Address setup. That one is weird. I don't see where exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * it fits in UDMA cycles, I got it's name from an obscure piece
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * of commented out code in Darwin. They leave it to 0, we do as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * well, despite a comment that would lead to think it has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * min value of 45ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Apple also add 60ns to the write data setup (or cycle time ?) on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TR_66_UDMA_MASK 0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TR_66_PIO_ADDRSETUP_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TR_66_UDMA_RDY2PAUS_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TR_66_UDMA_WRDATASETUP_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TR_66_MDMA_MASK 0x000ffc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TR_66_MDMA_RECOVERY_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TR_66_MDMA_ACCESS_MASK 0x00007c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TR_66_MDMA_ACCESS_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TR_66_PIO_MASK 0xe00003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TR_66_PIO_RECOVERY_MASK 0x000003e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TR_66_PIO_RECOVERY_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TR_66_PIO_ACCESS_MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TR_66_PIO_ACCESS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * The access time and recovery time can be programmed. Some older
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Darwin code base limit OHare to 150ns cycle time. I decided to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * the same here fore safety against broken old hardware ;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * The HalfTick bit, when set, adds half a clock (15ns) to the access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * time and removes one from recovery. It's not supported on KeyLargo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * implementation afaik. The E bit appears to be set for PIO mode 0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * is used to reach long timings used in this mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TR_33_MDMA_MASK 0x003ff800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TR_33_MDMA_RECOVERY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TR_33_MDMA_ACCESS_MASK 0x0000f800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TR_33_MDMA_ACCESS_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TR_33_MDMA_HALFTICK 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TR_33_PIO_MASK 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TR_33_PIO_E 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TR_33_PIO_RECOVERY_MASK 0x000003e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TR_33_PIO_RECOVERY_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TR_33_PIO_ACCESS_MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TR_33_PIO_ACCESS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Interrupt register definitions. Only present on newer cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * (Keylargo and later afaik) so we don't use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IDE_INTR_DMA 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IDE_INTR_DEVICE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * FCR Register on Kauai. Not sure what bit 0x4 is ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define KAUAI_FCR_UATA_MAGIC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define KAUAI_FCR_UATA_RESET_N 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define KAUAI_FCR_UATA_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Allow up to 256 DBDMA commands per xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MAX_DCMDS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Don't let a DMA segment go all the way to 64K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MAX_DBDMA_SEG 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Wait 1s for disk to answer on IDE bus after a hard reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * of the device (via GPIO/FCR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Some devices seem to "pollute" the bus even after dropping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * the BSY bit (typically some combo drives slave on the UDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * bus) after a hard reset. Since we hard reset all drives on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * KeyLargo ATA66, we have to keep that delay around. I may end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * up not hard resetting anymore on these and keep the delay only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * for older interfaces instead (we have to reset when coming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * from MacOS...) --BenH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IDE_WAKEUP_DELAY_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct pata_macio_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pata_macio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int kind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int aapl_bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int mediabay : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct macio_dev *mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 treg[2][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void __iomem *tfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void __iomem *kauai_fcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct dbdma_cmd * dma_table_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dma_addr_t dma_table_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) const struct pata_macio_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Previous variants of this driver used to calculate timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * for various variants of the chip and use tables for others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Not only was this confusing, but in addition, it isn't clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * whether our calculation code was correct. It didn't entirely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * match the darwin code and whatever documentation I could find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * on these cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * I decided to entirely rely on a table instead for this version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * of the driver. Also, because I don't really care about derated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * modes and really old HW other than making it work, I'm not going
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * to calculate / snoop timing values for something else than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * standard modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct pata_macio_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 reg1; /* Bits to set in first timing reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 reg2; /* Bits to set in second timing reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct pata_macio_timing pata_macio_ohare_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { XFER_PIO_0, 0x00000526, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { XFER_PIO_1, 0x00000085, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { XFER_PIO_2, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { XFER_PIO_3, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { XFER_PIO_4, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { XFER_MW_DMA_0, 0x00074000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { XFER_MW_DMA_1, 0x00221000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { XFER_MW_DMA_2, 0x00211000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { -1, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { XFER_PIO_0, 0x00000526, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { XFER_PIO_1, 0x00000085, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { XFER_PIO_2, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { XFER_PIO_3, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { XFER_PIO_4, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { XFER_MW_DMA_0, 0x00074000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { XFER_MW_DMA_1, 0x00221000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { XFER_MW_DMA_2, 0x00211000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { -1, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct pata_macio_timing pata_macio_kl33_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { XFER_PIO_0, 0x00000526, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { XFER_PIO_1, 0x00000085, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { XFER_PIO_2, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { XFER_PIO_3, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { XFER_PIO_4, 0x00000025, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { XFER_MW_DMA_0, 0x00084000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { XFER_MW_DMA_1, 0x00021800, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { XFER_MW_DMA_2, 0x00011800, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { -1, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct pata_macio_timing pata_macio_kl66_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { XFER_PIO_0, 0x0000038c, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { XFER_PIO_1, 0x0000020a, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { XFER_PIO_2, 0x00000127, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { XFER_PIO_3, 0x000000c6, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { XFER_PIO_4, 0x00000065, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { XFER_MW_DMA_0, 0x00084000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { XFER_MW_DMA_1, 0x00029800, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { XFER_MW_DMA_2, 0x00019400, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { XFER_UDMA_0, 0x19100000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { XFER_UDMA_1, 0x14d00000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { XFER_UDMA_2, 0x10900000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { XFER_UDMA_3, 0x0c700000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { XFER_UDMA_4, 0x0c500000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { -1, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct pata_macio_timing pata_macio_kauai_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { XFER_PIO_0, 0x08000a92, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { XFER_PIO_1, 0x0800060f, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { XFER_PIO_2, 0x0800038b, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { XFER_PIO_3, 0x05000249, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { XFER_PIO_4, 0x04000148, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { XFER_MW_DMA_0, 0x00618000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { XFER_MW_DMA_1, 0x00209000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { XFER_MW_DMA_2, 0x00148000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { XFER_UDMA_0, 0, 0x000070c1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { XFER_UDMA_1, 0, 0x00005d81, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { XFER_UDMA_2, 0, 0x00004a61, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { XFER_UDMA_3, 0, 0x00003a51, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { XFER_UDMA_4, 0, 0x00002a31, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { XFER_UDMA_5, 0, 0x00002921, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { -1, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct pata_macio_timing pata_macio_shasta_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { XFER_PIO_0, 0x0a000c97, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { XFER_PIO_1, 0x07000712, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { XFER_PIO_2, 0x040003cd, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { XFER_PIO_3, 0x0500028b, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { XFER_PIO_4, 0x0400010a, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { XFER_MW_DMA_0, 0x00820800, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { XFER_MW_DMA_1, 0x0028b000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { XFER_MW_DMA_2, 0x001ca000, 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { XFER_UDMA_0, 0, 0x00035901, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { XFER_UDMA_1, 0, 0x000348b1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { XFER_UDMA_2, 0, 0x00033881, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { XFER_UDMA_3, 0, 0x00033861, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { XFER_UDMA_4, 0, 0x00033841, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { XFER_UDMA_5, 0, 0x00033031, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { XFER_UDMA_6, 0, 0x00033021, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { -1, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct pata_macio_timing *pata_macio_find_timing(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct pata_macio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) for (i = 0; priv->timings[i].mode > 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (priv->timings[i].mode == mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return &priv->timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void __iomem *rbase = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (priv->kind == controller_sh_ata6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) priv->kind == controller_un_ata6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) priv->kind == controller_k2_ata6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ata_sff_dev_select(ap, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Apply timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pata_macio_apply_timings(ap, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void pata_macio_set_timings(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) const struct pata_macio_timing *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) adev->devno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) adev->pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) adev->dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* First clear timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Now get the PIO timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) t = pata_macio_find_timing(priv, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (t == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) t = pata_macio_find_timing(priv, XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) BUG_ON(t == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* PIO timings only ever use the first treg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) priv->treg[adev->devno][0] |= t->reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Now get DMA timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) t = pata_macio_find_timing(priv, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) BUG_ON(t == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* DMA timings can use both tregs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) priv->treg[adev->devno][0] |= t->reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) priv->treg[adev->devno][1] |= t->reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_dbg(priv->dev, " -> %08x %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) priv->treg[adev->devno][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) priv->treg[adev->devno][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Apply to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pata_macio_apply_timings(ap, adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Blast some well known "safe" values to the timing registers at init or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * wakeup from sleep time, before we do real calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void pata_macio_default_timings(struct pata_macio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int value, value2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) switch(priv->kind) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case controller_sh_ata6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) value = 0x0a820c97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) value2 = 0x00033031;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case controller_un_ata6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case controller_k2_ata6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) value = 0x08618a92;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) value2 = 0x00002921;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case controller_kl_ata4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) value = 0x0008438c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case controller_kl_ata3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) value = 0x00084526;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case controller_heathrow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case controller_ohare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) value = 0x00074526;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) priv->treg[0][0] = priv->treg[1][0] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) priv->treg[0][1] = priv->treg[1][1] = value2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int pata_macio_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Get cable type from device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (priv->kind == controller_kl_ata4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) priv->kind == controller_un_ata6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) priv->kind == controller_k2_ata6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) priv->kind == controller_sh_ata6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const char* cable = of_get_property(priv->node, "cable-type",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct device_node *root = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) const char *model = of_get_property(root, "model", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) of_node_put(root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (cable && !strncmp(cable, "80-", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Some drives fail to detect 80c cable in PowerBook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * These machine use proprietary short IDE cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!strncmp(model, "PowerBook", 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* G5's seem to have incorrect cable type in device-tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Let's assume they always have a 80 conductor cable, this seem to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * be always the case unless the user mucked around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (of_device_is_compatible(priv->node, "K2-UATA") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) of_device_is_compatible(priv->node, "shasta-ata"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Anything else is 40 connectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static enum ata_completion_errors pata_macio_qc_prep(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct dbdma_cmd *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int si, pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __func__, qc, qc->flags, write, qc->dev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!(qc->flags & ATA_QCFLAG_DMAMAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) table = (struct dbdma_cmd *) priv->dma_table_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) for_each_sg(qc->sg, sg, qc->n_elem, si) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 addr, sg_len, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* determine if physical DMA addr spans 64K boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Note h/w doesn't support 64-bit, so we unconditionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * truncate dma_addr_t to u32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) addr = (u32) sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sg_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) while (sg_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* table overflow should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) BUG_ON (pi++ >= MAX_DCMDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) table->req_count = cpu_to_le16(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) table->phy_addr = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) table->cmd_dep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) table->xfer_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) table->res_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) addr += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sg_len -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ++table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Should never happen according to Tejun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) BUG_ON(!pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Convert the last command to an input/output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) table--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) table++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Add the stop command to the end of the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) memset(table, 0, sizeof(struct dbdma_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) table->command = cpu_to_le16(DBDMA_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return AC_ERR_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void pata_macio_freeze(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (dma_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int timeout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Make sure DMA controller is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) while (--timeout && (readl(&dma_regs->status) & RUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ata_sff_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int dev = qc->dev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Make sure DMA commands updates are visible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) writel(priv->dma_table_dma, &dma_regs->cmdptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * UDMA reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (priv->kind == controller_kl_ata4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (priv->treg[dev][0] & TR_66_UDMA_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) void __iomem *rbase = ap->ioaddr.cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 reg = priv->treg[dev][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (!(qc->tf.flags & ATA_TFLAG_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) reg += 0x00800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) writel(reg, rbase + IDE_TIMING_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* issue r/w command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ap->ops->sff_exec_command(ap, &qc->tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) writel((RUN << 16) | RUN, &dma_regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Make sure it gets to the controller right now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) (void)readl(&dma_regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned int timeout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Stop the DMA engine and wait for it to full halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) while (--timeout && (readl(&dma_regs->status) & RUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static u8 pata_macio_bmdma_status(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 dstat, rstat = ATA_DMA_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned long timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dstat = readl(&dma_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* We have two things to deal with here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * - The dbdma won't stop if the command was started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * but completed with an error without transferring all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * datas. This happens when bad blocks are met during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * a multi-block transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * - The dbdma fifo hasn't yet finished flushing to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * to system memory when the disk interrupt occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* First check for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if ((dstat & (RUN|DEAD)) != RUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) rstat |= ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* If ACTIVE is cleared, the STOP command has been hit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * the transfer is complete. If not, we have to flush the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if ((dstat & ACTIVE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return rstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* If dbdma didn't execute the STOP command yet, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * active bit is still set. We consider that we aren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * sharing interrupts (which is hopefully the case with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * those controllers) and so we just try to flush the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * channel for pending data in the fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel((FLUSH << 16) | FLUSH, &dma_regs->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dstat = readl(&dma_regs->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if ((dstat & FLUSH) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (++timeout > 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_warn(priv->dev, "timeout flushing DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) rstat |= ATA_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return rstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* port_start is when we allocate the DMA command list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int pata_macio_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (ap->ioaddr.bmdma_addr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Allocate space for the DBDMA commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * The +2 is +1 for the stop command and +1 to allow for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * aligning the start address to a multiple of 16 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) priv->dma_table_cpu =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dmam_alloc_coherent(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) &priv->dma_table_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (priv->dma_table_cpu == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_err(priv->dev, "Unable to allocate DMA command list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ap->ioaddr.bmdma_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ap->mwdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ap->udma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static void pata_macio_irq_clear(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Nothing to do here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_dbgdma(priv->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(priv->dev, "Enabling & resetting... \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (priv->mediabay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (priv->kind == controller_ohare && !resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* The code below is having trouble on some ohare machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * (timing related ?). Until I can put my hand on one of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * units, I keep the old way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Reset and enable controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) priv->node, priv->aapl_bus_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) priv->node, priv->aapl_bus_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Only bother waiting if there's a reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ppc_md.feature_call(PMAC_FTR_IDE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) priv->node, priv->aapl_bus_id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) msleep(IDE_WAKEUP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* If resuming a PCI device, restore the config space here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (priv->pdev && resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pci_restore_state(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) rc = pcim_enable_device(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_err(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "Failed to enable device after resume (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pci_set_master(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * seem necessary and speeds up the boot process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (priv->kauai_fcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) writel(KAUAI_FCR_UATA_MAGIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) KAUAI_FCR_UATA_RESET_N |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Hook the standard slave config to fixup some HW related alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * restrictions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int pata_macio_slave_config(struct scsi_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct ata_port *ap = ata_shost_to_port(sdev->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct pata_macio_priv *priv = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* First call original */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rc = ata_scsi_slave_config(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* This is lifted from sata_nv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev = &ap->link.device[sdev->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* OHare has issues with non cache aligned DMA on some chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (priv->kind == controller_ohare) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) blk_queue_update_dma_alignment(sdev->request_queue, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) blk_queue_update_dma_pad(sdev->request_queue, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Tell the world about it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ata_dev_info(dev, "OHare alignment limits applied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* We only have issues with ATAPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (dev->class != ATA_DEV_ATAPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* Shasta and K2 seem to have "issues" with reads ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Allright these are bad, apply restrictions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) blk_queue_update_dma_alignment(sdev->request_queue, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) blk_queue_update_dma_pad(sdev->request_queue, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* We enable MWI and hack cache line size directly here, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * is specific to this chipset and not normal values, we happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * to somewhat know what we are doing here (which is basically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * to do the same Apple does and pray they did not get it wrong :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) BUG_ON(!priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pci_write_config_word(priv->pdev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) cmd | PCI_COMMAND_INVALIDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Tell the world about it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ata_dev_info(dev, "K2/Shasta alignment limits applied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* First, core libata suspend to do most of the work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) rc = ata_host_suspend(priv->host, mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Restore to default timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pata_macio_default_timings(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Mask interrupt. Not strictly necessary but old driver did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * it and I'd rather not change that here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) disable_irq(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* The media bay will handle itself just fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (priv->mediabay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Kauai has bus control FCRs directly here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (priv->kauai_fcr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 fcr = readl(priv->kauai_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) writel(fcr, priv->kauai_fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* For PCI, save state and disable DMA. No need to call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * pci_set_power_state(), the HW doesn't do D states that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * way, the platform code will take care of suspending the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * ASIC properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (priv->pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pci_save_state(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pci_disable_device(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Disable the bus on older machines and the cell on kauai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) priv->aapl_bus_id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int pata_macio_do_resume(struct pata_macio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Reset and re-enable the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) pata_macio_reset_hw(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* Sanitize drive timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pata_macio_apply_timings(priv->host->ports[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* We want our IRQ back ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) enable_irq(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Let the libata core take it from there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ata_host_resume(priv->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static struct scsi_host_template pata_macio_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ATA_BASE_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .sg_tablesize = MAX_DCMDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* We may not need that strict one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .dma_boundary = ATA_DMA_BOUNDARY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Not sure what the real max is but we know it's less than 64K, let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * use 64K minus 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .max_segment_size = MAX_DBDMA_SEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .slave_configure = pata_macio_slave_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static struct ata_port_operations pata_macio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .freeze = pata_macio_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .set_piomode = pata_macio_set_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .set_dmamode = pata_macio_set_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .cable_detect = pata_macio_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .sff_dev_select = pata_macio_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .qc_prep = pata_macio_qc_prep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .bmdma_setup = pata_macio_bmdma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .bmdma_start = pata_macio_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .bmdma_stop = pata_macio_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .bmdma_status = pata_macio_bmdma_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .port_start = pata_macio_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .sff_irq_clear = pata_macio_irq_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static void pata_macio_invariants(struct pata_macio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) const int *bidp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Identify the type of controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (of_device_is_compatible(priv->node, "shasta-ata")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) priv->kind = controller_sh_ata6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) priv->timings = pata_macio_shasta_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) priv->kind = controller_un_ata6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) priv->timings = pata_macio_kauai_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) priv->kind = controller_k2_ata6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) priv->timings = pata_macio_kauai_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (of_node_name_eq(priv->node, "ata-4")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) priv->kind = controller_kl_ata4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) priv->timings = pata_macio_kl66_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) priv->kind = controller_kl_ata3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) priv->timings = pata_macio_kl33_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) priv->kind = controller_heathrow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) priv->timings = pata_macio_heathrow_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) priv->kind = controller_ohare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) priv->timings = pata_macio_ohare_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* XXX FIXME --- setup priv->mediabay here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* Get Apple bus ID (for clock and ASIC control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) priv->aapl_bus_id = bidp ? *bidp : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Fixup missing Apple bus ID in case of media-bay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (priv->mediabay && !bidp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) priv->aapl_bus_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void pata_macio_setup_ios(struct ata_ioports *ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) void __iomem * base, void __iomem * dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* cmd_addr is the base of regs for that port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ioaddr->cmd_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* taskfile registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ioaddr->data_addr = base + (ATA_REG_DATA << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ioaddr->error_addr = base + (ATA_REG_ERR << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ioaddr->command_addr = base + (ATA_REG_CMD << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ioaddr->altstatus_addr = base + 0x160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ioaddr->ctl_addr = base + 0x160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ioaddr->bmdma_addr = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct ata_port_info *pinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) pinfo->pio_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) pinfo->mwdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pinfo->udma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) while (priv->timings[i].mode > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) switch(priv->timings[i].mode & 0xf0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) case 0x00: /* PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pinfo->pio_mask |= (mask >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case 0x20: /* MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pinfo->mwdma_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case 0x40: /* UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pinfo->udma_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static int pata_macio_common_init(struct pata_macio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) resource_size_t tfregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) resource_size_t dmaregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) resource_size_t fcregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unsigned long irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct ata_port_info pinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) const struct ata_port_info *ppi[] = { &pinfo, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) void __iomem *dma_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* Fill up privates with various invariants collected from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * device-tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pata_macio_invariants(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Make sure we have sane initial timings in the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) pata_macio_default_timings(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* Allocate libata host for 1 port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) memset(&pinfo, 0, sizeof(struct ata_port_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pmac_macio_calc_timing_masks(priv, &pinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pinfo.flags = ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) pinfo.port_ops = &pata_macio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pinfo.private_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (priv->host == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dev_err(priv->dev, "Failed to allocate ATA port structure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Setup the private data in host too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) priv->host->private_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Map base registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (priv->tfregs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_err(priv->dev, "Failed to map ATA ports\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) priv->host->iomap = &priv->tfregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Map DMA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (dmaregs != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dma_regs = devm_ioremap(priv->dev, dmaregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) sizeof(struct dbdma_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (dma_regs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* If chip has local feature control, map those regs too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (fcregs != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (priv->kauai_fcr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_err(priv->dev, "Failed to map ATA FCR register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* Setup port data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) priv->tfregs, dma_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) priv->host->ports[0]->private_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* hard-reset the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pata_macio_reset_hw(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pata_macio_apply_timings(priv->host->ports[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Enable bus master if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (priv->pdev && dma_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pci_set_master(priv->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) macio_ata_names[priv->kind], priv->aapl_bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* Start it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) priv->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) &pata_macio_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int pata_macio_attach(struct macio_dev *mdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) const struct of_device_id *match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct pata_macio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) resource_size_t tfregs, dmaregs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned long irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* Check for broken device-trees */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (macio_resource_count(mdev) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dev_err(&mdev->ofdev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "No addresses for controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Enable managed resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) macio_enable_devres(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* Allocate and init private data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) priv = devm_kzalloc(&mdev->ofdev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) sizeof(struct pata_macio_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) priv->node = of_node_get(mdev->ofdev.dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) priv->mdev = mdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) priv->dev = &mdev->ofdev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Request memory resource for taskfile registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (macio_request_resource(mdev, 0, "pata-macio")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dev_err(&mdev->ofdev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) "Cannot obtain taskfile resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) tfregs = macio_resource_start(mdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* Request resources for DMA registers if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (macio_resource_count(mdev) >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (macio_request_resource(mdev, 1, "pata-macio-dma"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dev_err(&mdev->ofdev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "Cannot obtain DMA resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dmaregs = macio_resource_start(mdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * Fixup missing IRQ for some old implementations with broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * device-trees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * This is a bit bogus, it should be fixed in the device-tree itself,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * via the existing macio fixups, based on the type of interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * controller in the machine. However, I have no test HW for this case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * and this trick works well enough on those old machines...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (macio_irq_count(mdev) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_warn(&mdev->ofdev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) "No interrupts for controller, using 13\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) irq = irq_create_mapping(NULL, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) irq = macio_irq(mdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Prevvent media bay callbacks until fully registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) lock_media_bay(priv->mdev->media_bay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Get register addresses and call common initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) rc = pata_macio_common_init(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) tfregs, /* Taskfile regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dmaregs, /* DBDMA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) 0, /* Feature control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) unlock_media_bay(priv->mdev->media_bay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static int pata_macio_detach(struct macio_dev *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct ata_host *host = macio_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct pata_macio_priv *priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) lock_media_bay(priv->mdev->media_bay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Make sure the mediabay callback doesn't try to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * dead stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) priv->host->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) unlock_media_bay(priv->mdev->media_bay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct ata_host *host = macio_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return pata_macio_do_suspend(host->private_data, mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static int pata_macio_resume(struct macio_dev *mdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct ata_host *host = macio_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return pata_macio_do_resume(host->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #ifdef CONFIG_PMAC_MEDIABAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct ata_host *host = macio_get_drvdata(mdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct ata_eh_info *ehi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (!host || !host->private_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) spin_lock_irqsave(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ehi = &ap->link.eh_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (mb_state == MB_CD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ata_ehi_push_desc(ehi, "mediabay plug");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ata_ehi_hotplugged(ehi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ata_port_freeze(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ata_ehi_push_desc(ehi, "mediabay unplug");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ata_for_each_dev(dev, &ap->link, ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev->flags |= ATA_DFLAG_DETACH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ata_port_abort(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) spin_unlock_irqrestore(ap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #endif /* CONFIG_PMAC_MEDIABAY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int pata_macio_pci_attach(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct pata_macio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) resource_size_t rbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* We cannot use a MacIO controller without its OF device node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) np = pci_device_to_OF_node(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (np == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "Cannot find OF device node for controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Check that it can be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (pcim_enable_device(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) "Cannot enable controller PCI device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* Allocate and init private data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) priv = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) sizeof(struct pata_macio_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) priv->node = of_node_get(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* Get MMIO regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (pci_request_regions(pdev, "pata-macio")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "Cannot obtain PCI resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* Get register addresses and call common initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) rbase = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (pata_macio_common_init(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) rbase + 0x2000, /* Taskfile regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) rbase + 0x1000, /* DBDMA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) rbase, /* Feature control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) pdev->irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static void pata_macio_pci_detach(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return pata_macio_do_suspend(host->private_data, mesg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static int pata_macio_pci_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return pata_macio_do_resume(host->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const struct of_device_id pata_macio_match[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .name = "IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .name = "ATA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .type = "ide",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .type = "ata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) MODULE_DEVICE_TABLE(of, pata_macio_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static struct macio_driver pata_macio_driver =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .name = "pata-macio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .of_match_table = pata_macio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .probe = pata_macio_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .remove = pata_macio_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .suspend = pata_macio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .resume = pata_macio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #ifdef CONFIG_PMAC_MEDIABAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .mediabay_event = pata_macio_mb_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const struct pci_device_id pata_macio_pci_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static struct pci_driver pata_macio_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .name = "pata-pci-macio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .id_table = pata_macio_pci_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .probe = pata_macio_pci_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .remove = pata_macio_pci_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .suspend = pata_macio_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .resume = pata_macio_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static int __init pata_macio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (!machine_is(powermac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) rc = pci_register_driver(&pata_macio_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) rc = macio_register_driver(&pata_macio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pci_unregister_driver(&pata_macio_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static void __exit pata_macio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) macio_unregister_driver(&pata_macio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pci_unregister_driver(&pata_macio_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) module_init(pata_macio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) module_exit(pata_macio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) MODULE_AUTHOR("Benjamin Herrenschmidt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) MODULE_DESCRIPTION("Apple MacIO PATA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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