^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata-legacy.c - Legacy port PATA/SATA controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2005/2006 Red Hat, all rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * An ATA driver for the legacy ATA ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Data Sources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Opti 82C465/82C611 support: Data sheets at opti-inc.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * HT6560 series:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Promise 20230/20620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * http://www.ryston.cz/petr/vlb/pdc20230b.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * http://www.ryston.cz/petr/vlb/pdc20230c.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * http://www.ryston.cz/petr/vlb/pdc20630.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * QDI65x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * http://www.ryston.cz/petr/vlb/qd6500.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * http://www.ryston.cz/petr/vlb/qd6580.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Samuel Thibault <samuel.thibault@ens-lyon.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Unsupported but docs exist:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * This driver handles legacy (that is "ISA/VLB side") IDE ports found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * on PC class systems. There are three hybrid devices that are exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Specific support is included for the ht6560a/ht6560b/opti82c611a/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Support for the Winbond 83759A when operating in advanced mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Multichip mode is not currently supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Use the autospeed and pio_mask options with:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Appian ADI/2 aka CLPD7220 or AIC25VL01.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Winbond W83759A, Promise PDC20230-B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * For now use autospeed and pio_mask as above with the W83759A. This may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DRV_NAME "pata_legacy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRV_VERSION "0.6.5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NR_HOST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) module_param(all, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) BIOS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SNOOP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PDC20230 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) HT6560A = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) HT6560B = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) OPTI611A = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) OPTI46X = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) QDI6500 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) QDI6580 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) QDI6580DP = 9, /* Dual channel mode is different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) W83759A = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) UNKNOWN = -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct legacy_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 clock[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enum controller type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct platform_device *platform_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct legacy_probe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum controller type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct legacy_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ata_port_operations *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int pio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int pflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int (*setup)(struct platform_device *, struct legacy_probe *probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct legacy_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct legacy_probe probe_list[NR_HOST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct legacy_data legacy_data[NR_HOST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct ata_host *legacy_host[NR_HOST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int nr_legacy_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int probe_all; /* Set to check all ISA port ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int autospeed; /* Chip present which snoops speed changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Set to probe QDI controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_PATA_QDI_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int qdi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int qdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int winbond = 1; /* Set to probe Winbond controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) give I/O port if non standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int winbond; /* Set to probe Winbond controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) give I/O port if non standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * legacy_probe_add - Add interface to probe list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @port: Controller port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @type: Controller type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @private: Controller specific info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Add an entry into the probe list for ATA controllers. This is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * to add the default ISA slots and then to build up the table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * further according to other ISA/VLB/Weird device scans
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * An I/O port list is used to keep ordering stable and sane, as we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * don't have any good way to talk about ordering otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int legacy_probe_add(unsigned long port, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum controller type, unsigned long private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct legacy_probe *lp = &probe_list[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct legacy_probe *free = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) for (i = 0; i < NR_HOST; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (lp->port == 0 && free == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) free = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Matching port, or the correct slot for ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (lp->port == port || legacy_port[i] == port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) free = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) lp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (free == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Fill in the entry for later probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) free->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) free->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) free->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) free->private = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * legacy_set_mode - mode setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @link: IDE link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @unused: Device that failed when error is returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Use a non standard set_mode function. We don't want to be tuned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * The BIOS configured everything. Our job is not to fiddle. Just use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * whatever PIO the hardware is using and leave it at that. When we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * get some kind of nice user driven API for control then we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * expand on this as per hdparm in the base kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ata_for_each_dev(dev, link, ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ata_dev_info(dev, "configured for PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev->pio_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev->xfer_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev->xfer_shift = ATA_SHIFT_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev->flags |= ATA_DFLAG_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct scsi_host_template legacy_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct ata_port_operations legacy_base_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .inherits = &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .cable_detect = ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * These ops are used if the user indicates the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * snoops the commands to decide on the mode and handles the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * mode selection "magically" itself. Several legacy controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * do this. The mode range can be set if it is not 0x1F by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * pio_mask as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct ata_port_operations simple_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .sff_data_xfer = ata_sff_data_xfer32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct ata_port_operations legacy_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .sff_data_xfer = ata_sff_data_xfer32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .set_mode = legacy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Promise 20230C and 20620 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * This controller supports PIO0 to PIO2. We set PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * support is weird being DMA to controller and PIO'd to the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * and not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int tries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int pio = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Safe as UP only. Force I/Os to occur together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Unlock the control interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) inb(0x1F5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) outb(inb(0x1F2) | 0x80, 0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) inb(0x3F6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) inb(0x3F6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) while ((inb(0x1F2) & 0x80) && --tries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) outb(inb(0x1F4) & 0x07, 0x1F4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rt = inb(0x1F3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) rt &= 0x07 << (3 * adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rt |= (1 + 3 * pio) << (3 * adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) outb(inb(0x1F2) | 0x01, 0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) inb(0x1F5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned char *buf, unsigned int buflen, int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct ata_device *dev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct ata_port *ap = dev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int slop = buflen & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* 32bit I/O capable *and* we need to write a whole number of dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) && (ap->pflags & ATA_PFLAG_PIO32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Perform the 32bit I/O synchronization sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ioread8(ap->ioaddr.nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ioread8(ap->ioaddr.nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ioread8(ap->ioaddr.nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Now the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (rw == READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (unlikely(slop)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __le32 pad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (rw == READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) memcpy(buf + buflen - slop, &pad, slop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) memcpy(&pad, buf + buflen - slop, slop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) buflen += 4 - slop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) buflen = ata_sff_data_xfer32(qc, buf, buflen, rw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct ata_port_operations pdc20230_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .set_piomode = pdc20230_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .sff_data_xfer = pdc_data_xfer_vlb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Holtek 6560A support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * This controller supports PIO0 to PIO2 (no IORDY even though higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * timings can be loaded).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 active, recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Get the timing data in cycles. For now play safe at 50Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) active = clamp_val(t.active, 2, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) recover = clamp_val(t.recover, 4, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ioread8(ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct ata_port_operations ht6560a_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .set_piomode = ht6560a_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Holtek 6560B support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * setting unless we see an ATAPI device in which case we force it off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * FIXME: need to implement 2nd channel support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 active, recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Get the timing data in cycles. For now play safe at 50Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) active = clamp_val(t.active, 2, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) recover = clamp_val(t.recover, 2, 16) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (adev->class != ATA_DEV_ATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 rconf = inb(0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (rconf & 0x24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) rconf &= ~0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) outb(rconf, 0x3E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ioread8(ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct ata_port_operations ht6560b_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .set_piomode = ht6560b_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Opti core chipset helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * opti_syscfg - read OPTI chipset configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * @reg: Configuration register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Returns the value of an OPTI system board configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static u8 opti_syscfg(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Uniprocessor chipset and must force cycles adjancent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) outb(reg, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) r = inb(0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Opti 82C611A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * This controller supports PIO0 to PIO3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void opti82c611a_set_piomode(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 active, recover, setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int khz[4] = { 50000, 40000, 33000, 25000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Enter configuration mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ioread16(ap->ioaddr.error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ioread16(ap->ioaddr.error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) iowrite8(3, ap->ioaddr.nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Read VLB clock strapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Get the timing data in cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Setup timing is shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct ata_timing tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) active = clamp_val(t.active, 2, 17) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) recover = clamp_val(t.recover, 1, 16) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) setup = clamp_val(t.setup, 1, 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Select the right timing bank for write timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rc = ioread8(ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) rc &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rc |= (adev->devno << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) iowrite8(rc, ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Write the timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Select the right bank for read timings, also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) load the shared timings for address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) rc = ioread8(ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rc &= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rc |= adev->devno; /* Index select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rc |= (setup << 4) | 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) iowrite8(rc, ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Load the read timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Ensure the timing register mode is right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rc = ioread8(ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) rc &= 0x73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rc |= 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) iowrite8(rc, ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Exit command mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) iowrite8(0x83, ap->ioaddr.nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct ata_port_operations opti82c611a_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .set_piomode = opti82c611a_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Opti 82C465MV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * version is dual channel but doesn't have a lot of unique registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 active, recover, setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int khz[4] = { 50000, 40000, 33000, 25000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Get the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Enter configuration mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ioread16(ap->ioaddr.error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ioread16(ap->ioaddr.error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) iowrite8(3, ap->ioaddr.nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Read VLB clock strapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) clock = 1000000000 / khz[sysclk];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Get the timing data in cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Setup timing is shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct ata_timing tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) active = clamp_val(t.active, 2, 17) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) recover = clamp_val(t.recover, 1, 16) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) setup = clamp_val(t.setup, 1, 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Select the right timing bank for write timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) rc = ioread8(ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rc &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) rc |= (adev->devno << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) iowrite8(rc, ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Write the timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Select the right bank for read timings, also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) load the shared timings for address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rc = ioread8(ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rc &= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) rc |= adev->devno; /* Index select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) rc |= (setup << 4) | 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) iowrite8(rc, ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Load the read timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Ensure the timing register mode is right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) rc = ioread8(ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rc &= 0x73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) rc |= 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) iowrite8(rc, ap->ioaddr.lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Exit command mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) iowrite8(0x83, ap->ioaddr.nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* We need to know this for quad device on the MVB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ap->host->private_data = ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * opt82c465mv_qc_issue - command issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * @qc: command pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Called when the libata layer is about to issue a command. We wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * this interface so that we can load the correct ATA timings. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * MVB has a single set of timing registers and these are shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * across channels. As there are two registers we really ought to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * track the last two used values as a sort of register window. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * now we just reload on a channel switch. On the single channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * setup this condition never fires so we do nothing extra.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * FIXME: dual channel needs ->serialize support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* If timings are set and for the wrong channel (2nd test is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) due to a libata shortcoming and will eventually go I hope) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ap->host->private_data != ap->host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) && ap->host->private_data != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) opti82c46x_set_piomode(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct ata_port_operations opti82c46x_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .set_piomode = opti82c46x_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .qc_issue = opti82c46x_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * qdi65x0_set_piomode - PIO setup for QDI65x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * @ap: Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * @adev: Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * In single channel mode the 6580 has one clock per device and we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * avoid the requirement to clock switch. We also have to load the timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * into the right clock according to whether we are master or slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * In dual channel mode the 6580 has one clock per channel and we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * to software clockswitch in qc_issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct legacy_data *ld_qdi = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int active, recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Get the timing data in cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ld_qdi->fast) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) active = 8 - clamp_val(t.active, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) recovery = 18 - clamp_val(t.recover, 3, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) active = 9 - clamp_val(t.active, 2, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) recovery = 15 - clamp_val(t.recover, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) timing = (recovery << 4) | active | 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ld_qdi->clock[adev->devno] = timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ld_qdi->type == QDI6580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) outb(timing, ld_qdi->timing + 2 * adev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) outb(timing, ld_qdi->timing + 2 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Clear the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * qdi_qc_issue - command issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * @qc: command pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Called when the libata layer is about to issue a command. We wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * this interface so that we can load the correct ATA timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct legacy_data *ld_qdi = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (adev->pio_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ld_qdi->last = ld_qdi->clock[adev->devno];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 2 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return ata_sff_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned int buflen, int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct ata_port *ap = adev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int slop = buflen & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) && (ap->pflags & ATA_PFLAG_PIO32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (rw == WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (unlikely(slop)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __le32 pad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (rw == WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) memcpy(&pad, buf + buflen - slop, slop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) memcpy(buf + buflen - slop, &pad, slop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return (buflen + 3) & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ata_sff_data_xfer(qc, buf, buflen, rw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int qdi_port(struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct legacy_probe *lp, struct legacy_data *ld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ld->timing = lp->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static struct ata_port_operations qdi6500_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .set_piomode = qdi65x0_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .qc_issue = qdi_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .sff_data_xfer = vlb32_data_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct ata_port_operations qdi6580_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .set_piomode = qdi65x0_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .sff_data_xfer = vlb32_data_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static struct ata_port_operations qdi6580dp_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .set_piomode = qdi65x0_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .qc_issue = qdi_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .sff_data_xfer = vlb32_data_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static DEFINE_SPINLOCK(winbond_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) spin_lock_irqsave(&winbond_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) outb(reg, port + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) outb(val, port + 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) spin_unlock_irqrestore(&winbond_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static u8 winbond_readcfg(unsigned long port, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) spin_lock_irqsave(&winbond_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) outb(reg, port + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) val = inb(port + 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) spin_unlock_irqrestore(&winbond_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct ata_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct legacy_data *ld_winbond = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int active, recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) reg = winbond_readcfg(ld_winbond->timing, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Get the timing data in cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) timing = (active << 4) | recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) winbond_writecfg(ld_winbond->timing, timing, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Load the setup timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) reg = 0x35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (adev->class != ATA_DEV_ATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) reg |= 0x08; /* FIFO off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!ata_pio_need_iordy(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) reg |= 0x02; /* IORDY off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) reg |= (clamp_val(t.setup, 0, 3) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) winbond_writecfg(ld_winbond->timing, timing + 1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int winbond_port(struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct legacy_probe *lp, struct legacy_data *ld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ld->timing = lp->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static struct ata_port_operations winbond_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .inherits = &legacy_base_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .set_piomode = winbond_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .sff_data_xfer = vlb32_data_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct legacy_controller controllers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {"BIOS", &legacy_port_ops, ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ATA_FLAG_NO_IORDY, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {"Snooping", &simple_port_ops, ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 0, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ATA_FLAG_NO_IORDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ATA_FLAG_NO_IORDY, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ATA_FLAG_NO_IORDY, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 0, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 0, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ATA_FLAG_NO_IORDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {"W83759A", &winbond_port_ops, ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) winbond_port }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * probe_chip_type - Discover controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * @probe: Probe entry to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * Probe an ATA port and identify the type of controller. We don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * check if the controller appears to be driveless at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static __init int probe_chip_type(struct legacy_probe *probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int mask = 1 << probe->slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u8 reg = winbond_readcfg(winbond, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) reg |= 0x80; /* jumpered mode off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) winbond_writecfg(winbond, 0x81, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) reg = winbond_readcfg(winbond, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) reg |= 0xF0; /* local control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) winbond_writecfg(winbond, 0x83, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) reg = winbond_readcfg(winbond, 0x85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) reg |= 0xF0; /* programmable timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) winbond_writecfg(winbond, 0x85, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) reg = winbond_readcfg(winbond, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (reg & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return W83759A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (probe->port == 0x1F0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Probes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) outb(inb(0x1F2) | 0x80, 0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) inb(0x1F5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) inb(0x3F6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) inb(0x3F6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if ((inb(0x1F2) & 0x80) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* PDC20230c or 20630 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) " detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) inb(0x1F5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return PDC20230;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) outb(0x55, 0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) inb(0x1F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (inb(0x1F2) == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) printk(KERN_INFO "PDC20230-B VLB ATA "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "controller detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return BIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (ht6560a & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return HT6560A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ht6560b & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return HT6560B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (opti82c611a & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return OPTI611A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (opti82c46x & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return OPTI46X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (autospeed & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return SNOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return BIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * legacy_init_one - attach a legacy interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * @pl: probe record
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Register an ISA bus IDE interface. Such interfaces are PIO and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * assume do not support IRQ sharing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static __init int legacy_init_one(struct legacy_probe *probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct legacy_controller *controller = &controllers[probe->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int pio_modes = controller->pio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned long io = probe->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 mask = (1 << probe->slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct ata_port_operations *ops = controller->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct legacy_data *ld = &legacy_data[probe->slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct ata_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) void __iomem *io_addr, *ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) iordy |= controller->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (IS_ERR(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) devm_request_region(&pdev->dev, io + 0x0206, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "pata_legacy") == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) io_addr = devm_ioport_map(&pdev->dev, io, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!io_addr || !ctrl_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ld->type = probe->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (controller->setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (controller->setup(pdev, probe, ld) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ap->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ap->pio_mask = pio_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ap->pflags |= controller->pflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ap->ioaddr.cmd_addr = io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ap->ioaddr.altstatus_addr = ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ap->ioaddr.ctl_addr = ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ata_sff_std_ports(&ap->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ap->host->private_data = ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) &legacy_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) async_synchronize_full();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ld->platform_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Nothing found means we drop the port as its probably not there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ata_for_each_dev(dev, &ap->link, ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (!ata_dev_absent(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) legacy_host[probe->slot] = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ld->platform_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * legacy_check_special_cases - ATA special cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * @p: PCI device to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * @master: set this if we find an ATA master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * @master: set this if we find an ATA secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * A small number of vendors implemented early PCI ATA interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * on bridge logic without the ATA interface being PCI visible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * Where we have a matching PCI driver we must skip the relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * device here. If we don't know about it then the legacy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * is the right driver anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int *secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (p->vendor == 0x1078 && p->device == 0x0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) *primary = *secondary = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (p->vendor == 0x1078 && p->device == 0x0002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) *primary = *secondary = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Intel MPIIX - PIO ATA on non PCI side of bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (p->vendor == 0x8086 && p->device == 0x1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u16 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pci_read_config_word(p, 0x6C, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (r & 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* ATA port enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (r & 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) *secondary = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) *primary = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static __init void probe_opti_vlb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* If an OPTI 82C46X is present find out where the channels are */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const char *optis[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "3/463MV", "5MV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "5MVA", "5MVB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u8 chans = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) opti82c46x = 3; /* Assume master and slave first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) optis[ctrl]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (ctrl == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ctrl = opti_syscfg(0xAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Check enabled and this port is the 465MV port. On the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) MVB we may have two channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (ctrl & 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (chans == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) legacy_probe_add(0x1F0, 14, OPTI46X, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) legacy_probe_add(0x170, 15, OPTI46X, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (ctrl & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) legacy_probe_add(0x170, 15, OPTI46X, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) legacy_probe_add(0x1F0, 14, OPTI46X, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) legacy_probe_add(0x1F0, 14, OPTI46X, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* Check card type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if ((r & 0xF0) == 0xC0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* QD6500: single channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (r & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Disabled ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) QDI6500, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* QD6580: dual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!request_region(port + 2 , 2, "pata_qdi")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) release_region(port, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) res = inb(port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* Single channel mode ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (res & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) QDI6580, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) else { /* Dual channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) legacy_probe_add(0x1F0, 14, QDI6580DP, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* port + 0x02, r & 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) release_region(port + 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static __init void probe_qdi_vlb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static const unsigned long qd_port[2] = { 0x30, 0xB0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Check each possible QD65xx base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) unsigned long port = qd_port[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u8 r, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (request_region(port, 2, "pata_qdi")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* Check for a card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* I have no h/w that needs this delay but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) is present in the historic code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) r = inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) outb(0x19, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) res = inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) outb(r, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (res == 0x19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) release_region(port, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Passes the presence test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) r = inb(port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* Check port agrees with port set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if ((r & 2) >> 1 == i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) qdi65_identify_port(r, res, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) release_region(port, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * legacy_init - attach legacy interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * Right now we do not scan the ide0 and ide1 address but should do so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * for non PCI systems or systems with no PCI IDE legacy mode devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * If you fix that note there are special cases to consider like VLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * drivers and CS5510/20.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static __init int legacy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int ct = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int primary = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int secondary = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int pci_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct legacy_probe *pl = &probe_list[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct pci_dev *p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for_each_pci_dev(p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Check for any overlap of the system ATA mappings. Native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) mode controllers stuck on these addresses or some devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) in 'raid' mode won't be found by the storage class test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) for (r = 0; r < 6; r++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (pci_resource_start(p, r) == 0x1f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) primary = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (pci_resource_start(p, r) == 0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) secondary = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* Check for special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) legacy_check_special_cases(p, &primary, &secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* If PCI bus is present then don't probe for tertiary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) legacy ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pci_present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (winbond == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) winbond = 0x130; /* Default port, alt is 1B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (primary == 0 || all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (secondary == 0 || all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) legacy_probe_add(0x170, 15, UNKNOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (probe_all || !pci_present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* ISA/VLB extra ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) legacy_probe_add(0x168, 10, UNKNOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) legacy_probe_add(0x160, 12, UNKNOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (opti82c46x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) probe_opti_vlb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (qdi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) probe_qdi_vlb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) for (i = 0; i < NR_HOST; i++, pl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (pl->port == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (pl->type == UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pl->type = probe_chip_type(pl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pl->slot = slot++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (legacy_init_one(pl) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ct++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ct != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static __exit void legacy_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) for (i = 0; i < nr_legacy_host; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct legacy_data *ld = &legacy_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ata_host_detach(legacy_host[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) platform_device_unregister(ld->platform_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) MODULE_DESCRIPTION("low-level driver for legacy ATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) MODULE_ALIAS("pata_qdi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) MODULE_ALIAS("pata_winbond");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) module_param(probe_all, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) module_param(autospeed, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) module_param(ht6560a, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) module_param(ht6560b, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) module_param(opti82c611a, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) module_param(opti82c46x, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) module_param(qdi, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) module_param(winbond, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) module_param(pio_mask, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) module_param(iordy_mask, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) module_init(legacy_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) module_exit(legacy_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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