^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * PATA port of the controller. The SATA ports are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * driven by AHCI in the usual configuration although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * this driver can handle other setups if we need it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (c) 2006 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRV_NAME "pata_jmicron"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_VERSION "0.1.5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_PATA0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_PATA1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_SATA = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) } port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * jmicron_pre_reset - check for 40/80 pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @link: ATA link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Perform the PATA port setup we need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * On the Jmicron 361/363 there is a single PATA port that can be mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * either as primary or secondary (or neither). We don't do any policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * and setup here. We assume that has been done by init_one and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int jmicron_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 control5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int port_mask = 1<< (4 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int port = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) port_type port_map[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Check if our port is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pci_read_config_dword(pdev, 0x40, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if ((control & port_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* There are two basic mappings. One has the two SATA ports merged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) as master/slave and the secondary as PATA, the other has only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SATA port mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (control & (1 << 23)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) port_map[0] = PORT_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) port_map[1] = PORT_PATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) port_map[0] = PORT_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) port_map[1] = PORT_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* The 365/366 may have this bit set to map the second PATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) as the internal primary channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pci_read_config_dword(pdev, 0x80, &control5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (control5 & (1<<24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) port_map[0] = PORT_PATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* The two ports may then be logically swapped by the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (control & (1 << 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) port = port ^ 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Now we know which physical port we are talking about we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * actually do our cable checking etc. Thankfully we don't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * to do the plumbing for other cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) switch (port_map[port]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case PORT_PATA0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if ((control & (1 << 5)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (control & (1 << 3)) /* 40/80 pin primary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ap->cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ap->cbl = ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case PORT_PATA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Bit 21 is set if the port is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if ((control5 & (1 << 21)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (control5 & (1 << 19)) /* 40/80 pin secondary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ap->cbl = ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ap->cbl = ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case PORT_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ap->cbl = ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* No PIO or DMA methods needed for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct scsi_host_template jmicron_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct ata_port_operations jmicron_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .prereset = jmicron_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * jmicron_init_one - Register Jmicron ATA PCI device with kernel services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @pdev: PCI device to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @ent: Entry in jmicron_pci_tbl matching with @pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Called from kernel PCI layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * LOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Inherited from PCI layer (may sleep).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * RETURNS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Zero on success, or -ERRNO value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int jmicron_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct ata_port_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .port_ops = &jmicron_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct ata_port_info *ppi[] = { &info, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ata_pci_bmdma_init_one(pdev, ppi, &jmicron_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct pci_device_id jmicron_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct pci_driver jmicron_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .id_table = jmicron_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .probe = jmicron_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .resume = ata_pci_device_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) module_pci_driver(jmicron_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MODULE_DESCRIPTION("SCSI low-level driver for Jmicron PATA ports");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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