Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ixp4xx PATA/Compact Flash driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2006-07 Tower Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Alessandro Zummo <a.zummo@towertech.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * An ATA driver to handle a Compact Flash connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * to the ixp4xx expansion bus in TrueIDE mode. The CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * must have it chip selects connected to two CS lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * on the ixp4xx. In the irq is not available, you might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * want to modify both this driver and libata to run in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DRV_NAME	"pata_ixp4xx_cf"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRV_VERSION	"0.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static int ixp4xx_set_mode(struct ata_link *link, struct ata_device **error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	ata_for_each_dev(dev, link, ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		ata_dev_info(dev, "configured for PIO0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		dev->pio_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		dev->xfer_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		dev->xfer_shift = ATA_SHIFT_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		dev->flags |= ATA_DFLAG_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static unsigned int ixp4xx_mmio_data_xfer(struct ata_queued_cmd *qc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 				unsigned char *buf, unsigned int buflen, int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned int words = buflen >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u16 *buf16 = (u16 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct ata_port *ap = qc->dev->link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	void __iomem *mmio = ap->ioaddr.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct ixp4xx_pata_data *data = dev_get_platdata(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* set the expansion bus in 16bit mode and restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 * 8 bit mode after the transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	*data->cs0_cfg &= ~(0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* Transfer multiple of 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (rw == READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		for (i = 0; i < words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			buf16[i] = readw(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		for (i = 0; i < words; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			writew(buf16[i], mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* Transfer trailing 1 byte, if any. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (unlikely(buflen & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		u16 align_buf[1] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		unsigned char *trailing_buf = buf + buflen - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		if (rw == READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			align_buf[0] = readw(mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			memcpy(trailing_buf, align_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			memcpy(align_buf, trailing_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			writew(align_buf[0], mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		words++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	*data->cs0_cfg |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return words << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct scsi_host_template ixp4xx_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static struct ata_port_operations ixp4xx_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.inherits		= &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.sff_data_xfer		= ixp4xx_mmio_data_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.cable_detect		= ata_cable_40wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.set_mode		= ixp4xx_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void ixp4xx_setup_port(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			      struct ixp4xx_pata_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			      unsigned long raw_cs0, unsigned long raw_cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct ata_ioports *ioaddr = &ap->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned long raw_cmd = raw_cs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned long raw_ctl = raw_cs1 + 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ioaddr->cmd_addr	= data->cs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ioaddr->altstatus_addr	= data->cs1 + 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ioaddr->ctl_addr	= data->cs1 + 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ata_sff_std_ports(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifndef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* adjust the addresses to handle the address swizzling of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * ixp4xx in little endian mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	*(unsigned long *)&ioaddr->data_addr		^= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	*(unsigned long *)&ioaddr->cmd_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	*(unsigned long *)&ioaddr->altstatus_addr	^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	*(unsigned long *)&ioaddr->ctl_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	*(unsigned long *)&ioaddr->error_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	*(unsigned long *)&ioaddr->feature_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	*(unsigned long *)&ioaddr->nsect_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	*(unsigned long *)&ioaddr->lbal_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	*(unsigned long *)&ioaddr->lbam_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	*(unsigned long *)&ioaddr->lbah_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	*(unsigned long *)&ioaddr->device_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	*(unsigned long *)&ioaddr->status_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	*(unsigned long *)&ioaddr->command_addr		^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	raw_cmd ^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	raw_ctl ^= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", raw_cmd, raw_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int ixp4xx_pata_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct resource *cs0, *cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct ixp4xx_pata_data *data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (!cs0 || !cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* allocate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* acquire resources and fill host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	data->cs0 = devm_ioremap(&pdev->dev, cs0->start, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	data->cs1 = devm_ioremap(&pdev->dev, cs1->start, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (!data->cs0 || !data->cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	else if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Setup expansion bus chip selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	*data->cs0_cfg = data->cs0_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	*data->cs1_cfg = data->cs1_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ap->ops	= &ixp4xx_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ap->flags |= ATA_FLAG_NO_ATAPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ixp4xx_setup_port(ap, data, cs0->start, cs1->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ata_print_version_once(&pdev->dev, DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* activate host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return ata_host_activate(host, irq, ata_sff_interrupt, 0, &ixp4xx_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct platform_driver ixp4xx_pata_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.driver	 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.name   = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.probe		= ixp4xx_pata_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.remove		= ata_platform_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) module_platform_driver(ixp4xx_pata_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_DESCRIPTION("low-level driver for ixp4xx Compact Flash PATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_ALIAS("platform:" DRV_NAME);