^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * pata_it821x.c - IT821x PATA for new ATA layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2005 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) 2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it821x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2004 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Based in part on the ITE vendor provided SCSI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Documentation available from IT8212F_V04.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=5,91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Some other documents are NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * The ITE8212 isn't exactly a standard IDE controller. It has two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * modes. In pass through mode then it is an IDE controller. In its smart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * mode its actually quite a capable hardware raid controller disguised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * as an IDE controller. Smart mode only understands DMA read/write and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * identify, none of the fancier commands apply. The IT8211 is identical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * in other respects but lacks the raid mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * o Rev 0x10 also requires master/slave hold the same DMA timings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * cannot do ATAPI MWDMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * o The identify data for raid volumes lacks CHS info (technically ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * but also fails to set the LBA28 and other bits. We fix these in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * the IDE probe quirk code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * raid then the controller firmware dies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * o Smart mode without RAID doesn't clear all the necessary identify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * bits to reduce the command set to the one used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This has a few impacts on the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * - In pass through mode we do all the work you would expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * - In smart mode the clocking set up is done by the controller generally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * but we must watch the other limits and filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * - There are a few extra vendor commands that actually talk to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * controller but only work PIO with no IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Vendor areas of the identify block in smart mode are used for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * timing and policy set up. Each HDD in raid mode also has a serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * block on the disk. The hardware extra commands are get/set chip status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * rebuild, get rebuild status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * In Linux the driver supports pass through mode as if the device was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * just another IDE controller. If the smart mode is running then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * volumes are managed by the controller firmware and each IDE "disk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * is a raid volume. Even more cute - the controller can do automated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * hotplug and rebuild.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The pass through controller itself is a little demented. It has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * flaw that it has a single set of PIO/MWDMA timings per channel so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * non UDMA devices restrict each others performance. It also has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * single clock source per channel so mixed UDMA100/133 performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * isn't perfect and we have to pick a clock. Thankfully none of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * matters in smart mode. ATAPI DMA is not currently supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * - ATAPI and other speed filtering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - RAID configuration ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DRV_NAME "pata_it821x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DRV_VERSION "0.4.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct it821x_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int smart:1, /* Are we in smart raid mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) timing10:1; /* Rev 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 clock_mode; /* 0, ATA_50 or ATA_66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 want[2][2]; /* Mode/Pri log for master slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* We need these for switching the clock when DMA goes on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) The high byte is the 66Mhz timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 pio[2]; /* Cached PIO values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 mwdma[2]; /* Cached MWDMA values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 udma[2]; /* Cached UDMA values (per drive) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 last_device; /* Master or slave loaded ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ATA_66 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ATA_50 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ATA_ANY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define UDMA_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MWDMA_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * We allow users to force the card into non raid mode without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * flashing the alternative BIOS. This is also necessary right now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * for embedded platforms that cannot run a PC BIOS but are using this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int it8212_noraid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * it821x_program - program the PIO/MWDMA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @adev: Device to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Program the PIO/MWDMA timing for this channel according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * current clock. These share the same register so are managed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * the DMA start/stop sequence as with the old driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int channel = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Program PIO/MWDMA timing bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (itdev->clock_mode == ATA_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) conf = timing >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) conf = timing & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pci_write_config_byte(pdev, 0x54 + 4 * channel, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * it821x_program_udma - program the UDMA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @adev: ATA device to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Program the UDMA timing for this drive according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * current clock. Handles the dual clocks and also knows about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * the errata on the 0x10 revision. The UDMA errata is partly handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * here and partly in start_dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int channel = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int unit = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Program UDMA timing bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (itdev->clock_mode == ATA_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) conf = timing >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) conf = timing & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (itdev->timing10 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Early revision must be programmed for both together */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pci_write_config_byte(pdev, 0x56 + 4 * channel, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * it821x_clock_strategy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @adev: ATA device being updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Select between the 50 and 66Mhz base clocks to get the best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * results for this interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 unit = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct ata_device *pair = ata_dev_pair(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int clock, altclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Look for the most wanted clocking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (itdev->want[0][0] > itdev->want[1][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clock = itdev->want[0][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) altclock = itdev->want[1][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clock = itdev->want[1][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) altclock = itdev->want[0][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Master doesn't care does the slave ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (clock == ATA_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clock = altclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Nobody cares - keep the same clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (clock == ATA_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* No change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (clock == itdev->clock_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Load this into the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (clock == ATA_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) itdev->clock_mode = ATA_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) itdev->clock_mode = ATA_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pci_read_config_byte(pdev, 0x50, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) v &= ~(1 << (1 + ap->port_no));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) v |= sel << (1 + ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pci_write_config_byte(pdev, 0x50, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Reprogram the UDMA/PIO of the pair drive for the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * MWDMA will be dealt with by the dma switcher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (pair && itdev->udma[1-unit] != UDMA_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) it821x_program_udma(ap, pair, itdev->udma[1-unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) it821x_program(ap, pair, itdev->pio[1-unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Reprogram the UDMA/PIO of our drive for the switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * MWDMA will be dealt with by the dma switcher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (itdev->udma[unit] != UDMA_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) it821x_program_udma(ap, adev, itdev->udma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) it821x_program(ap, adev, itdev->pio[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * it821x_passthru_set_piomode - set PIO mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Configure for PIO mode. This is complicated as the register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * shared by PIO and MWDMA and for both channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Spec says 89 ref driver uses 88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int unit = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int mode_wanted = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) itdev->want[unit][1] = pio_want[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) itdev->want[unit][0] = 1; /* PIO is lowest priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) itdev->pio[unit] = pio[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) it821x_clock_strategy(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) it821x_program(ap, adev, itdev->pio[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * it821x_passthru_set_dmamode - set initial DMA mode data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Set up the DMA modes. The actions taken depend heavily on the mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * to use. If UDMA is used as is hopefully the usual case then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * timing register is private and we need only consider the clock. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * we are using MWDMA then we have to manage the setting ourself as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * we switch devices and mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const u16 dma[] = { 0x8866, 0x3222, 0x3121 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int channel = ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int unit = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (adev->dma_mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int mode_wanted = adev->dma_mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) itdev->want[unit][1] = udma_want[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) itdev->want[unit][0] = 3; /* UDMA is high priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) itdev->mwdma[unit] = MWDMA_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) itdev->udma[unit] = udma[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (mode_wanted >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* UDMA on. Again revision 0x10 must do the pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pci_read_config_byte(pdev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (itdev->timing10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) conf &= channel ? 0x9F: 0xE7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) conf &= ~ (1 << (3 + 2 * channel + unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pci_write_config_byte(pdev, 0x50, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) it821x_clock_strategy(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) it821x_program_udma(ap, adev, itdev->udma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int mode_wanted = adev->dma_mode - XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) itdev->want[unit][1] = mwdma_want[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) itdev->want[unit][0] = 2; /* MWDMA is low priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) itdev->mwdma[unit] = dma[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) itdev->udma[unit] = UDMA_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* UDMA bits off - Revision 0x10 do them in pairs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pci_read_config_byte(pdev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (itdev->timing10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) conf |= channel ? 0x60: 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) conf |= 1 << (3 + 2 * channel + unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pci_write_config_byte(pdev, 0x50, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) it821x_clock_strategy(ap, adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * it821x_passthru_dma_start - DMA start callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @qc: Command in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Usually drivers set the DMA timing at the point the set_dmamode call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * is made. IT821x however requires we load new timings on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * transitions in some cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int unit = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (itdev->mwdma[unit] != MWDMA_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) it821x_program(ap, adev, itdev->mwdma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) it821x_program_udma(ap, adev, itdev->udma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ata_bmdma_start(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * it821x_passthru_dma_stop - DMA stop callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @qc: ATA command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * We loaded new timings in dma_start, as a result we need to restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * the PIO timings in dma_stop so that the next command issue gets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * right clock values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct ata_device *adev = qc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int unit = adev->devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ata_bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (itdev->mwdma[unit] != MWDMA_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) it821x_program(ap, adev, itdev->pio[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * it821x_passthru_dev_select - Select master/slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @device: Device number (not pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Device selection hook. If necessary perform clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void it821x_passthru_dev_select(struct ata_port *ap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (itdev && device != itdev->last_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct ata_device *adev = &ap->link.device[device];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) it821x_program(ap, adev, itdev->pio[adev->devno]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) itdev->last_device = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ata_sff_dev_select(ap, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * it821x_smart_qc_issue - wrap qc issue prot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * @qc: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Wrap the command issue sequence for the IT821x. We need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * perform out own device selection timing loads before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * usual happenings kick off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) switch(qc->tf.command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Commands the firmware supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case ATA_CMD_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case ATA_CMD_READ_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case ATA_CMD_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case ATA_CMD_WRITE_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case ATA_CMD_PIO_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case ATA_CMD_PIO_READ_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case ATA_CMD_PIO_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case ATA_CMD_PIO_WRITE_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case ATA_CMD_READ_MULTI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case ATA_CMD_READ_MULTI_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case ATA_CMD_WRITE_MULTI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case ATA_CMD_WRITE_MULTI_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case ATA_CMD_ID_ATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case ATA_CMD_INIT_DEV_PARAMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case 0xFC: /* Internal 'report rebuild state' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Arguably should just no-op this one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case ATA_CMD_SET_FEATURES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ata_bmdma_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return AC_ERR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * it821x_passthru_qc_issue - wrap qc issue prot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @qc: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Wrap the command issue sequence for the IT821x. We need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * perform out own device selection timing loads before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * usual happenings kick off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) it821x_passthru_dev_select(qc->ap, qc->dev->devno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ata_bmdma_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * it821x_smart_set_mode - mode setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * @link: interface to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * @unused: device that failed (error only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * Use a non standard set_mode function. We don't want to be tuned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * The BIOS configured everything. Our job is not to fiddle. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * read the dma enabled bits from the PCI configuration of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * and respect them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct ata_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ata_for_each_dev(dev, link, ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* We don't really care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev->pio_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev->dma_mode = XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* We do need the right mode information for DMA or PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) and this comes from the current configuration flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ata_id_has_dma(dev->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ata_dev_info(dev, "configured for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev->xfer_mode = XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev->xfer_shift = ATA_SHIFT_MWDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev->flags &= ~ATA_DFLAG_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ata_dev_info(dev, "configured for PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev->xfer_mode = XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev->xfer_shift = ATA_SHIFT_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev->flags |= ATA_DFLAG_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * it821x_dev_config - Called each device identify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * @adev: Device that has just been identified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Perform the initial setup needed for each device that is chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * special. In our case we need to lock the sector count to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * blowing the brains out of the firmware with large LBA48 requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void it821x_dev_config(struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (adev->max_sectors > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) adev->max_sectors = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (strstr(model_num, "Integrated Technology Express")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* RAID mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ata_dev_info(adev, "%sRAID%d volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) adev->id[147] ? "Bootable " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) adev->id[129]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (adev->id[129] != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pr_cont("(%dK stripe)", adev->id[146]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* This is a controller firmware triggered funny, don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) report the drive faulty! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) adev->horkage &= ~ATA_HORKAGE_DIAGNOSTIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* No HPA in 'smart' mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) adev->horkage |= ATA_HORKAGE_BROKEN_HPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * it821x_read_id - Hack identify data up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * @adev: device to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * @tf: proposed taskfile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @id: buffer for returned ident data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Query the devices on this firmware driven port and slightly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * mash the identify data to stop us and common tools trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * use features not firmware supported. The firmware itself does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * some masking (eg SMART) but not enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static unsigned int it821x_read_id(struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct ata_taskfile *tf, u16 *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned char model_num[ATA_ID_PROD_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) err_mask = ata_do_dev_read_id(adev, tf, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (err_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ata_id_c_string(id, model_num, ATA_ID_PROD, sizeof(model_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) id[83] &= ~(1 << 12); /* Cache flush is firmware handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) id[83] &= ~(1 << 13); /* Ditto for LBA48 flushes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) id[84] &= ~(1 << 6); /* No FUA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) id[85] &= ~(1 << 10); /* No HPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) id[76] = 0; /* No NCQ/AN etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (strstr(model_num, "Integrated Technology Express")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Set feature bits the firmware neglects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) id[49] |= 0x0300; /* LBA, DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) id[83] &= 0x7FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) id[83] |= 0x4400; /* Word 83 is valid and LBA48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) id[86] |= 0x0400; /* LBA48 on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) id[ATA_ID_MAJOR_VER] |= 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Clear the serial number because it's different each boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) which breaks validation on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * it821x_check_atapi_dma - ATAPI DMA handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * @qc: Command we are about to issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Decide if this ATAPI command can be issued by DMA on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * controller. Return 0 if it can be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct it821x_dev *itdev = ap->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Only use dma for transfers to/from the media. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (ata_qc_raw_nbytes(qc) < 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* No ATAPI DMA in smart mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (itdev->smart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* No ATAPI DMA on rev 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (itdev->timing10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Cool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * it821x_display_disk - display disk setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @n: Device number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * @buf: Buffer block from firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Produce a nice informative display of the device setup as provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * by the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static void it821x_display_disk(int n, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned char id[41];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) const char *mtype = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) char mbuf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) const char *cbl = "(40 wire cable)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const char *types[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "RAID0", "RAID1", "RAID 0+1", "JBOD", "DISK"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (buf[52] > 4) /* No Disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ata_id_c_string((u16 *)buf, id, 0, 41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (buf[51]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mode = ffs(buf[51]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mtype = "UDMA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else if (buf[49]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mode = ffs(buf[49]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mtype = "MWDMA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (buf[76])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cbl = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) snprintf(mbuf, 8, "%5s%d", mtype, mode - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) strcpy(mbuf, "PIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (buf[52] == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) printk(KERN_INFO "%d: %-6s %-8s %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) n, mbuf, types[buf[52]], id, cbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) printk(KERN_INFO "%d: %-6s %-8s Volume: %1d %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) n, mbuf, types[buf[52]], buf[53], id, cbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (buf[125] < 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) printk(KERN_INFO "%d: Rebuilding: %d%%\n", n, buf[125]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * it821x_firmware_command - issue firmware command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * @ap: IT821x port to interrogate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * @cmd: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * @len: length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Issue firmware commands expecting data back from the controller. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * use this to issue commands that do not go via the normal paths. Other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * commands such as 0xFC can be issued normally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u16 *buf = kmalloc(len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* This isn't quite a normal ATA command as we are talking to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) firmware not the drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ap->ctl |= ATA_NIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ata_wait_idle(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) iowrite8(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) iowrite8(cmd, ap->ioaddr.command_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* This should be almost immediate but a little paranoia goes a long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) while(n++ < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) status = ioread8(ap->ioaddr.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (status & ATA_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) printk(KERN_ERR "it821x_firmware_command: rejected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (status & ATA_DRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ioread16_rep(ap->ioaddr.data_addr, buf, len/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return (u8 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) printk(KERN_ERR "it821x_firmware_command: timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * it821x_probe_firmware - firmware reporting/setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * @ap: IT821x port being probed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Probe the firmware of the controller by issuing firmware command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * 0xFA and analysing the returned data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void it821x_probe_firmware(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* This is a bit ugly as we can't just issue a task file to a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) as this is controller magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) buf = it821x_firmware_command(ap, 0xFA, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (buf != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) printk(KERN_INFO "pata_it821x: Firmware %02X/%02X/%02X%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) buf[505],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) buf[506],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) buf[507],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) buf[508]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) it821x_display_disk(i, buf + 128 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * it821x_port_start - port setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * @ap: ATA port being set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * The it821x needs to maintain private data structures and also to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * use the standard PCI interface which lacks support for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * functionality. We instead set up the private data on the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * start hook, and tear it down on port stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int it821x_port_start(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct it821x_dev *itdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int ret = ata_bmdma_port_start(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (itdev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ap->private_data = itdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pci_read_config_byte(pdev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (conf & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) itdev->smart = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Long I/O's although allowed in LBA48 space cause the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) onboard firmware to enter the twighlight zone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* No ATAPI DMA in this mode either */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ap->port_no == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) it821x_probe_firmware(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Pull the current clocks from 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (conf & (1 << (1 + ap->port_no)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) itdev->clock_mode = ATA_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) itdev->clock_mode = ATA_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) itdev->want[0][1] = ATA_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) itdev->want[1][1] = ATA_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) itdev->last_device = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (pdev->revision == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) itdev->timing10 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Need to disable ATAPI DMA for this case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!itdev->smart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * it821x_rdc_cable - Cable detect for RDC1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * @ap: port we are checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Return the RDC1010 cable type. Unlike the IT821x we know how to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * this and can do host side cable detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int it821x_rdc_cable(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u16 r40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pci_read_config_word(pdev, 0x40, &r40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (r40 & (1 << (2 + ap->port_no)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static struct scsi_host_template it821x_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static struct ata_port_operations it821x_smart_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .check_atapi_dma= it821x_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .qc_issue = it821x_smart_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .cable_detect = ata_cable_80wire,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .set_mode = it821x_smart_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .dev_config = it821x_dev_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .read_id = it821x_read_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .port_start = it821x_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static struct ata_port_operations it821x_passthru_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .check_atapi_dma= it821x_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .sff_dev_select = it821x_passthru_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .bmdma_start = it821x_passthru_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .bmdma_stop = it821x_passthru_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .qc_issue = it821x_passthru_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .cable_detect = ata_cable_unknown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .set_piomode = it821x_passthru_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .set_dmamode = it821x_passthru_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .port_start = it821x_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static struct ata_port_operations it821x_rdc_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .check_atapi_dma= it821x_check_atapi_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .sff_dev_select = it821x_passthru_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .bmdma_start = it821x_passthru_bmdma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .bmdma_stop = it821x_passthru_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .qc_issue = it821x_passthru_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .cable_detect = it821x_rdc_cable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .set_piomode = it821x_passthru_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .set_dmamode = it821x_passthru_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .port_start = it821x_port_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static void it821x_disable_raid(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Neither the RDC nor the IT8211 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (pdev->vendor != PCI_VENDOR_ID_ITE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pdev->device != PCI_DEVICE_ID_ITE_8212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Reset local CPU, and set BIOS not ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pci_write_config_byte(pdev, 0x5E, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Set to bypass mode, and reset PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pci_write_config_byte(pdev, 0x50, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pci_write_config_word(pdev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PCI_COMMAND_PARITY | PCI_COMMAND_IO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pci_write_config_word(pdev, 0x40, 0xA0F3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pci_write_config_dword(pdev,0x4C, 0x02040204);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pci_write_config_byte(pdev, 0x42, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const struct ata_port_info info_smart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .port_ops = &it821x_smart_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const struct ata_port_info info_passthru = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .port_ops = &it821x_passthru_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const struct ata_port_info info_rdc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .port_ops = &it821x_rdc_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const struct ata_port_info info_rdc_11 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* No UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .port_ops = &it821x_rdc_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) const struct ata_port_info *ppi[] = { NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const char *mode[2] = { "pass through", "smart" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (pdev->vendor == PCI_VENDOR_ID_RDC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Deal with Vortex86SX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (pdev->revision == 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ppi[0] = &info_rdc_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ppi[0] = &info_rdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Force the card into bypass mode if so requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (it8212_noraid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) it821x_disable_raid(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) pci_read_config_byte(pdev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) conf &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) printk(KERN_INFO DRV_NAME": controller in %s mode.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mode[conf]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (conf == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ppi[0] = &info_passthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ppi[0] = &info_smart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return ata_pci_bmdma_init_one(pdev, ppi, &it821x_sht, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int it821x_reinit_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct ata_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rc = ata_pci_device_do_resume(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Resume - turn raid back off if need be */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (it8212_noraid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) it821x_disable_raid(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct pci_device_id it821x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static struct pci_driver it821x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .id_table = it821x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .probe = it821x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .remove = ata_pci_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .suspend = ata_pci_device_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .resume = it821x_reinit_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) module_pci_driver(it821x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MODULE_DEVICE_TABLE(pci, it821x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) MODULE_VERSION(DRV_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) module_param_named(noraid, it8212_noraid, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MODULE_PARM_DESC(noraid, "Force card into bypass mode");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags