Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Freescale iMX PATA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2011 Arnaud Patard <arnaud.patard@rtp-net.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on pata_platform - Copyright (C) 2006 - 2007  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * - dmaengine support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/ata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRV_NAME "pata_imx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PATA_IMX_ATA_TIME_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PATA_IMX_ATA_TIME_ON		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PATA_IMX_ATA_TIME_1		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PATA_IMX_ATA_TIME_2W		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PATA_IMX_ATA_TIME_2R		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PATA_IMX_ATA_TIME_AX		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PATA_IMX_ATA_TIME_PIO_RDX	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PATA_IMX_ATA_TIME_4		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PATA_IMX_ATA_TIME_9		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PATA_IMX_ATA_CONTROL		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PATA_IMX_ATA_CTRL_FIFO_RST_B	(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PATA_IMX_ATA_CTRL_ATA_RST_B	(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PATA_IMX_ATA_CTRL_IORDY_EN	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PATA_IMX_ATA_INT_EN		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PATA_IMX_ATA_INTR_ATA_INTRQ2	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PATA_IMX_DRIVE_DATA		0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PATA_IMX_DRIVE_CONTROL		0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static u32 pio_t4[] = { 30,  20,  15,  10,  10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static u32 pio_t9[] = { 20,  15,  10,  10,  10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static u32 pio_tA[] = { 35,  35,  35,  35,  35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct pata_imx_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* timings/interrupt/control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	void __iomem *host_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32 ata_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void pata_imx_set_timing(struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				struct pata_imx_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct ata_timing timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 T, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	clkrate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (adev->pio_mode < XFER_PIO_0 || adev->pio_mode > XFER_PIO_4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	    !clkrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	T = 1000000000 / clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	mode = adev->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	writeb(1, priv->host_regs + PATA_IMX_ATA_TIME_PIO_RDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	writeb(pio_tA[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_AX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static void pata_imx_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct pata_imx_priv *priv = ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	pata_imx_set_timing(adev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	val = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (ata_pio_need_iordy(adev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		val |= PATA_IMX_ATA_CTRL_IORDY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		val &= ~PATA_IMX_ATA_CTRL_IORDY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	__raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct scsi_host_template pata_imx_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	ATA_PIO_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct ata_port_operations pata_imx_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.inherits		= &ata_sff_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.sff_data_xfer		= ata_sff_data_xfer32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.cable_detect		= ata_cable_unknown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.set_piomode		= pata_imx_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void pata_imx_setup_port(struct ata_ioports *ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* Fixup the port shift for platforms that need it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ioaddr->data_addr	= ioaddr->cmd_addr + (ATA_REG_DATA    << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ioaddr->error_addr	= ioaddr->cmd_addr + (ATA_REG_ERR     << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ioaddr->feature_addr	= ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ioaddr->nsect_addr	= ioaddr->cmd_addr + (ATA_REG_NSECT   << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ioaddr->lbal_addr	= ioaddr->cmd_addr + (ATA_REG_LBAL    << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ioaddr->lbam_addr	= ioaddr->cmd_addr + (ATA_REG_LBAM    << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ioaddr->lbah_addr	= ioaddr->cmd_addr + (ATA_REG_LBAH    << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ioaddr->device_addr	= ioaddr->cmd_addr + (ATA_REG_DEVICE  << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ioaddr->status_addr	= ioaddr->cmd_addr + (ATA_REG_STATUS  << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ioaddr->command_addr	= ioaddr->cmd_addr + (ATA_REG_CMD     << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int pata_imx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct ata_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct ata_port *ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct pata_imx_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct resource *io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	priv = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				sizeof(struct pata_imx_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	priv->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		dev_err(&pdev->dev, "Failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	host = ata_host_alloc(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (!host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	host->private_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ap = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ap->ops = &pata_imx_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	ap->pio_mask = ATA_PIO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ap->flags |= ATA_FLAG_SLAVE_POSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	priv->host_regs = devm_ioremap_resource(&pdev->dev, io_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (IS_ERR(priv->host_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		ret = PTR_ERR(priv->host_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ap->ioaddr.cmd_addr = priv->host_regs + PATA_IMX_DRIVE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ap->ioaddr.ctl_addr = priv->host_regs + PATA_IMX_DRIVE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	pata_imx_setup_port(&ap->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		(unsigned long long)io_res->start + PATA_IMX_DRIVE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		(unsigned long long)io_res->start + PATA_IMX_DRIVE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* deassert resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__raw_writel(PATA_IMX_ATA_CTRL_FIFO_RST_B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			PATA_IMX_ATA_CTRL_ATA_RST_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			priv->host_regs + PATA_IMX_ATA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			priv->host_regs + PATA_IMX_ATA_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* activate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ret = ata_host_activate(host, irq, ata_sff_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				&pata_imx_sht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int pata_imx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct ata_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct pata_imx_priv *priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ata_host_detach(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int pata_imx_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct pata_imx_priv *priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = ata_host_suspend(host, PMSG_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		priv->ata_ctl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			__raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int pata_imx_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct ata_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct pata_imx_priv *priv = host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	__raw_writel(priv->ata_ctl, priv->host_regs + PATA_IMX_ATA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			priv->host_regs + PATA_IMX_ATA_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ata_host_resume(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static SIMPLE_DEV_PM_OPS(pata_imx_pm_ops, pata_imx_suspend, pata_imx_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct of_device_id imx_pata_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.compatible = "fsl,imx27-pata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DEVICE_TABLE(of, imx_pata_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct platform_driver pata_imx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.probe		= pata_imx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.remove		= pata_imx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.of_match_table	= imx_pata_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.pm		= &pata_imx_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_platform_driver(pata_imx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DESCRIPTION("low-level driver for iMX PATA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MODULE_ALIAS("platform:" DRV_NAME);