^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This driver is heavily based upon:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Portions Copyright (C) 2001 Sun Microsystems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Portions Copyright (C) 2003 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Work out best PLL policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/libata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRV_NAME "pata_hpt3x2n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_VERSION "0.3.15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) HPT_PCI_FAST = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PCI66 = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) USE_DPLL = (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct hpt_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 xfer_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct hpt_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct hpt_clock *clocks[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* key for bus clock timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 28 UDMA enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 29 DMA enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 30 PIO_MST enable. If set, the chip is in bus master mode during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * PIO xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 31 FIFO enable. Only for PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* 66MHz DPLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct hpt_clock hpt3x2n_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { XFER_UDMA_7, 0x1c869c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { XFER_UDMA_6, 0x1c869c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { XFER_UDMA_5, 0x1c8a9c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { XFER_UDMA_4, 0x1c8a9c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { XFER_UDMA_3, 0x1c8e9c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { XFER_UDMA_2, 0x1c929c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { XFER_UDMA_1, 0x1c9a9c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { XFER_UDMA_0, 0x1c829c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { XFER_MW_DMA_2, 0x2c829c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { XFER_MW_DMA_1, 0x2c829c66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { XFER_MW_DMA_0, 0x2c829d2e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { XFER_PIO_4, 0x0c829c62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { XFER_PIO_3, 0x0c829c84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { XFER_PIO_2, 0x0c829ca6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { XFER_PIO_1, 0x0d029d26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { XFER_PIO_0, 0x0d029d5e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * hpt3x2n_find_mode - reset the hpt3x2n bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @speed: transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Return the 32bit register programming information for this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * that matches the speed provided. For the moment the clocks table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * is hard coded but easy to change. This will be needed if we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * different DPLLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct hpt_clock *clocks = hpt3x2n_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) while (clocks->xfer_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (clocks->xfer_speed == speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return clocks->timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0xffffffffU; /* silence compiler warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * hpt372n_filter - mode selection filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @adev: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @mask: mode mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * The Marvell bridge chips used on the HighPoint SATA cards do not seem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ata_id_is_sata(adev->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * hpt3x2n_cable_detect - Detect the cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @ap: ATA port to detect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Return the cable type attached to this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int hpt3x2n_cable_detect(struct ata_port *ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 scr2, ata66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pci_read_config_byte(pdev, 0x5B, &scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) udelay(10); /* debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Cable register now active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pci_read_config_byte(pdev, 0x5A, &ata66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Restore state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pci_write_config_byte(pdev, 0x5B, scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ata66 & (2 >> ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * hpt3x2n_pre_reset - reset the hpt3x2n bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @link: ATA link to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @deadline: deadline jiffies for the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Perform the initial reset handling for the 3x2n series controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Reset the hardware and state machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ata_port *ap = link->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Reset the state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ata_sff_prereset(link, deadline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 addr1, addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 reg, timing, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) addr2 = 0x51 + 4 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Fast interrupt prediction disable, hold off interrupt disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pci_read_config_byte(pdev, addr2, &fast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) fast &= ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pci_write_config_byte(pdev, addr2, fast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Determine timing mask and find matching mode entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (mode < XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mask = 0xcfc3ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else if (mode < XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mask = 0x31c001ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mask = 0x303c0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) timing = hpt3x2n_find_mode(ap, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pci_read_config_dword(pdev, addr1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) reg = (reg & ~mask) | (timing & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pci_write_config_dword(pdev, addr1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * hpt3x2n_set_piomode - PIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @adev: device on the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Perform PIO mode setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) hpt3x2n_set_mode(ap, adev, adev->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * hpt3x2n_set_dmamode - DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @ap: ATA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @adev: Device being configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Set up the channel for MWDMA or UDMA modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) hpt3x2n_set_mode(ap, adev, adev->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * hpt3x2n_bmdma_end - DMA engine stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @qc: ATA command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Clean up after the HPT3x2n and later DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct pci_dev *pdev = to_pci_dev(ap->host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int mscreg = 0x50 + 2 * ap->port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 bwsr_stat, msc_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pci_read_config_byte(pdev, mscreg, &msc_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (bwsr_stat & (1 << ap->port_no))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ata_bmdma_stop(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * hpt3x2n_set_clock - clock control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @ap: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @source: 0x21 or 0x23 for PLL or PCI sourced clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Switch the ATA bus clock between the PLL and PCI clock sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * while correctly isolating the bus and resetting internal logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * We must use the DPLL for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * - writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * - second channel UDMA7 (SATA ports) or higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * - 66MHz PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * or we will underclock the device and get reduced performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void hpt3x2n_set_clock(struct ata_port *ap, int source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Tristate the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) iowrite8(0x80, bmdma+0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) iowrite8(0x80, bmdma+0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Switch clock and reset channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) iowrite8(source, bmdma+0x7B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) iowrite8(0xC0, bmdma+0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Reset state machines, avoid enabling the disabled channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Complete reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) iowrite8(0x00, bmdma+0x79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Reconnect channels to bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) iowrite8(0x00, bmdma+0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) iowrite8(0x00, bmdma+0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) long flags = (long)ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* See if we should use the DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (writing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return USE_DPLL; /* Needed for write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (flags & PCI66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return USE_DPLL; /* Needed at 66Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int rc, flags = (long)ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* First apply the usual rules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rc = ata_std_qc_defer(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if ((flags & USE_DPLL) != dpll && alt->qc_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ATA_DEFER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct ata_port *ap = qc->ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int flags = (long)ap->host->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if ((flags & USE_DPLL) != dpll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) flags &= ~USE_DPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) flags |= dpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ap->host->private_data = (void *)(long)flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ata_bmdma_qc_issue(qc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct scsi_host_template hpt3x2n_sht = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ATA_BMDMA_SHT(DRV_NAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Configuration for HPT302N/371N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct ata_port_operations hpt3xxn_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .inherits = &ata_bmdma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .bmdma_stop = hpt3x2n_bmdma_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .qc_defer = hpt3x2n_qc_defer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .qc_issue = hpt3x2n_qc_issue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .cable_detect = hpt3x2n_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .set_piomode = hpt3x2n_set_piomode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .set_dmamode = hpt3x2n_set_dmamode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .prereset = hpt3x2n_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct ata_port_operations hpt372n_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .inherits = &hpt3xxn_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .mode_filter = &hpt372n_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * succeeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 reg5b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 reg5c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) for (tries = 0; tries < 0x5000; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pci_read_config_byte(dev, 0x5b, ®5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (reg5b & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* See if it stays set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (tries = 0; tries < 0x1000; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pci_read_config_byte(dev, 0x5b, ®5b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Failed ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if ((reg5b & 0x80) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Turn off tuning, we have the DPLL set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pci_read_config_dword(dev, 0x5c, ®5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Never went stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int hpt3x2n_pci_clock(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 fcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned long iobase = pci_resource_start(pdev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if ((fcnt >> 12) != 0xABCDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u16 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pr_warn("BIOS clock data not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* This is the process the HPT371 BIOS is reported to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pci_read_config_word(pdev, 0x78, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) total += sr & 0x1FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) udelay(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) fcnt = total / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fcnt &= 0x1FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) freq = (fcnt * 77) / 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Clamp to bands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (freq < 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (freq < 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (freq < 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * hpt3x2n_init_one - Initialise an HPT37X/302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * @id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Initialise an HPT3x2n device. There are some interesting complications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * here. Firstly the chip may report 366 and be one of several variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Secondly all the timings depend on the clock for the chip which we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * detect and look up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * This is the known chip mappings. It may be missing a couple of later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * releases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Chip version PCI Rev Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * HPT372 4 (HPT366) 5 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * HPT372N 4 (HPT366) 6 UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * HPT372 5 (HPT372) 1 Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * HPT372N 5 (HPT372) 2 UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * HPT302 6 (HPT302) * Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * HPT302N 6 (HPT302) > 1 UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * HPT371 7 (HPT371) * Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * HPT371N 7 (HPT371) > 1 UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * HPT374 8 (HPT374) * Other driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * HPT372N 9 (HPT372N) * UDMA133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * (1) UDMA133 support depends on the bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* HPT372N - UDMA133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct ata_port_info info_hpt372n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .port_ops = &hpt372n_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* HPT302N and HPT371N - UDMA133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const struct ata_port_info info_hpt3xxn = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .flags = ATA_FLAG_SLAVE_POSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .port_ops = &hpt3xxn_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u8 rev = dev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int pci_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int f_low, f_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned long iobase = pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) void *hpriv = (void *)USE_DPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) rc = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case PCI_DEVICE_ID_TTI_HPT366:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* 372N if rev >= 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (rev < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) goto hpt372n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case PCI_DEVICE_ID_TTI_HPT371:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* 371N if rev >= 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (rev < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case PCI_DEVICE_ID_TTI_HPT372:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* 372N if rev >= 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (rev < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto hpt372n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case PCI_DEVICE_ID_TTI_HPT302:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* 302N if rev >= 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (rev < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case PCI_DEVICE_ID_TTI_HPT372N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hpt372n:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ppi[0] = &info_hpt372n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pr_err("PCI table is bogus, please report (%d)\n", dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Ok so this is a chip we support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pci_read_config_byte(dev, 0x5A, &irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) irqmask &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pci_write_config_byte(dev, 0x5a, irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * HPT371 chips physically have only one channel, the secondary one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * but the primary channel registers do exist! Go figure...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * So, we manually disable the non-existing channel here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * (if the BIOS hasn't done this already).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 mcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pci_read_config_byte(dev, 0x50, &mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mcr1 &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pci_write_config_byte(dev, 0x50, mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * 50 for UDMA100. Right now we always use 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pci_mhz = hpt3x2n_pci_clock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) f_high = f_low + 2; /* Tolerance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* PLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pci_write_config_byte(dev, 0x5B, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Unlike the 37x we don't try jiggling the frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) for (adjust = 0; adjust < 8; adjust++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (hpt3xn_calibrate_dpll(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (adjust == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pr_err("DPLL did not stabilize!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * Set our private data up. We only need a few flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * so we use it directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (pci_mhz > 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hpriv = (void *)(PCI66 | USE_DPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * the MISC. register to stretch the UltraDMA Tss timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * NOTE: This register is only writeable via I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Now kick off ATA set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct pci_device_id hpt3x2n[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct pci_driver hpt3x2n_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .id_table = hpt3x2n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .probe = hpt3x2n_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .remove = ata_pci_remove_one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) module_pci_driver(hpt3x2n_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MODULE_DEVICE_TABLE(pci, hpt3x2n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MODULE_VERSION(DRV_VERSION);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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